commit 44b8f74b0088df22f30e0718f6aefa9fb87702f6
author Weiwei Li <liweiwei@iscas.ac.cn> Fri Apr 07 09:47:42 2023 +0800
committer Alistair Francis <alistair.francis@wdc.com> Fri May 05 10:49:50 2023 +1000
tree 10f29752d34a2c3f63ff349dec28707324b00185
parent 04803c3ddb37a8c84392452c3596bd1c4474904d

target/riscv: Use PRV_RESERVED instead of PRV_H

PRV_H has no real meaning, but just a reserved privilege mode currently.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230407014743.18779-3-liweiwei@iscas.ac.cn>
[ Changes by AF:
 - Convert one missing use of PRV_H
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

target/riscv/cpu.h

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index f47c3fc..86e08d1 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -684,7 +684,7 @@
         case PRV_U:
             xl = get_field(env->mstatus, MSTATUS64_UXL);
             break;
-        default: /* PRV_S | PRV_H */
+        default: /* PRV_S */
             xl = get_field(env->mstatus, MSTATUS64_SXL);
             break;
         }

target/riscv/cpu_bits.h

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 101702c..a16bfaf 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -608,7 +608,7 @@
 /* Privilege modes */
 #define PRV_U 0
 #define PRV_S 1
-#define PRV_H 2 /* Reserved */
+#define PRV_RESERVED 2
 #define PRV_M 3
 
 /* RV32 satp CSR field masks */

target/riscv/cpu_helper.c

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 2310c79..29ac795 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -650,7 +650,7 @@
     if (newpriv > PRV_M) {
         g_assert_not_reached();
     }
-    if (newpriv == PRV_H) {
+    if (newpriv == PRV_RESERVED) {
         newpriv = PRV_U;
     }
     if (icount_enabled() && newpriv != env->priv) {

target/riscv/gdbstub.c

diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index fa537ae..524bede 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -203,7 +203,7 @@
     if (n == 0) {
 #ifndef CONFIG_USER_ONLY
         cs->priv = ldtul_p(mem_buf) & 0x3;
-        if (cs->priv == PRV_H) {
+        if (cs->priv == PRV_RESERVED) {
             cs->priv = PRV_S;
         }
 #endif

target/riscv/op_helper.c

diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index b8a03af..bd21c6e 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -141,7 +141,7 @@
     }
 
     if (env->virt_enabled &&
-        (((env->priv < PRV_H) && !get_field(env->henvcfg, envbits)) ||
+        (((env->priv <= PRV_S) && !get_field(env->henvcfg, envbits)) ||
          ((env->priv < PRV_S) && !get_field(env->senvcfg, envbits)))) {
         riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, ra);
     }