tcg: Change translator-side labels to a pointer
This is improved type checking for the translators -- it's no longer
possible to accidentally swap arguments to the branch functions.
Note that the code generating backends still manipulate labels as int.
With notable exceptions, the scope of the change is just a few lines
for each target, so it's not worth building extra machinery to do this
change in per-target increments.
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Cc: Michael Walle <michael@walle.cc>
Cc: Leon Alrae <leon.alrae@imgtec.com>
Cc: Anthony Green <green@moxielogic.com>
Cc: Jia Liu <proljc@gmail.com>
Cc: Alexander Graf <agraf@suse.de>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Blue Swirl <blauwirbel@gmail.com>
Cc: Guan Xuetao <gxt@mprc.pku.edu.cn>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Richard Henderson <rth@twiddle.net>
diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h
index 6e5b012..05d89d3 100644
--- a/include/exec/gen-icount.h
+++ b/include/exec/gen-icount.h
@@ -6,8 +6,8 @@
/* Helpers for instruction counting code generation. */
static TCGArg *icount_arg;
-static int icount_label;
-static int exitreq_label;
+static TCGLabel *icount_label;
+static TCGLabel *exitreq_label;
static inline void gen_tb_start(TranslationBlock *tb)
{
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 9c77d46..efeeb05 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -388,7 +388,7 @@
/* ??? In system mode we are never multi-threaded, so CAS can be
implemented via a non-atomic load-compare-store sequence. */
{
- int lab_fail, lab_done;
+ TCGLabel *lab_fail, *lab_done;
TCGv val;
lab_fail = gen_new_label();
@@ -465,7 +465,7 @@
TCGv cmp, int32_t disp)
{
uint64_t dest = ctx->pc + (disp << 2);
- int lab_true = gen_new_label();
+ TCGLabel *lab_true = gen_new_label();
if (use_goto_tb(ctx, dest)) {
tcg_gen_brcondi_i64(cond, cmp, 0, lab_true);
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 34b489f..0b192a1 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -1096,7 +1096,7 @@
{
unsigned int sf, op, rt;
uint64_t addr;
- int label_match;
+ TCGLabel *label_match;
TCGv_i64 tcg_cmp;
sf = extract32(insn, 31, 1);
@@ -1125,7 +1125,7 @@
{
unsigned int bit_pos, op, rt;
uint64_t addr;
- int label_match;
+ TCGLabel *label_match;
TCGv_i64 tcg_cmp;
bit_pos = (extract32(insn, 31, 1) << 5) | extract32(insn, 19, 5);
@@ -1164,7 +1164,7 @@
if (cond < 0x0e) {
/* genuinely conditional branches */
- int label_match = gen_new_label();
+ TCGLabel *label_match = gen_new_label();
arm_gen_test_cc(cond, label_match);
gen_goto_tb(s, 0, s->pc);
gen_set_label(label_match);
@@ -1711,8 +1711,8 @@
* }
* env->exclusive_addr = -1;
*/
- int fail_label = gen_new_label();
- int done_label = gen_new_label();
+ TCGLabel *fail_label = gen_new_label();
+ TCGLabel *done_label = gen_new_label();
TCGv_i64 addr = tcg_temp_local_new_i64();
TCGv_i64 tmp;
@@ -3537,7 +3537,7 @@
static void disas_cc(DisasContext *s, uint32_t insn)
{
unsigned int sf, op, y, cond, rn, nzcv, is_imm;
- int label_continue = -1;
+ TCGLabel *label_continue = NULL;
TCGv_i64 tcg_tmp, tcg_y, tcg_rn;
if (!extract32(insn, 29, 1)) {
@@ -3557,7 +3557,7 @@
nzcv = extract32(insn, 0, 4);
if (cond < 0x0e) { /* not always */
- int label_match = gen_new_label();
+ TCGLabel *label_match = gen_new_label();
label_continue = gen_new_label();
arm_gen_test_cc(cond, label_match);
/* nomatch: */
@@ -3630,8 +3630,8 @@
/* OPTME: we could use movcond here, at the cost of duplicating
* a lot of the arm_gen_test_cc() logic.
*/
- int label_match = gen_new_label();
- int label_continue = gen_new_label();
+ TCGLabel *label_match = gen_new_label();
+ TCGLabel *label_continue = gen_new_label();
arm_gen_test_cc(cond, label_match);
/* nomatch: */
@@ -4104,7 +4104,7 @@
{
unsigned int mos, type, rm, cond, rn, op, nzcv;
TCGv_i64 tcg_flags;
- int label_continue = -1;
+ TCGLabel *label_continue = NULL;
mos = extract32(insn, 29, 3);
type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
@@ -4124,7 +4124,7 @@
}
if (cond < 0x0e) { /* not always */
- int label_match = gen_new_label();
+ TCGLabel *label_match = gen_new_label();
label_continue = gen_new_label();
arm_gen_test_cc(cond, label_match);
/* nomatch: */
@@ -4165,7 +4165,7 @@
static void disas_fp_csel(DisasContext *s, uint32_t insn)
{
unsigned int mos, type, rm, cond, rn, rd;
- int label_continue = -1;
+ TCGLabel *label_continue = NULL;
mos = extract32(insn, 29, 3);
type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
@@ -4184,7 +4184,7 @@
}
if (cond < 0x0e) { /* not always */
- int label_match = gen_new_label();
+ TCGLabel *label_match = gen_new_label();
label_continue = gen_new_label();
arm_gen_test_cc(cond, label_match);
/* nomatch: */
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 36868ed..381d896 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -736,10 +736,10 @@
* generate a conditional branch based on ARM condition code cc.
* This is common between ARM and Aarch64 targets.
*/
-void arm_gen_test_cc(int cc, int label)
+void arm_gen_test_cc(int cc, TCGLabel *label)
{
TCGv_i32 tmp;
- int inv;
+ TCGLabel *inv;
switch (cc) {
case 0: /* eq: Z */
@@ -7440,8 +7440,8 @@
{
TCGv_i32 tmp;
TCGv_i64 val64, extaddr;
- int done_label;
- int fail_label;
+ TCGLabel *done_label;
+ TCGLabel *fail_label;
/* if (env->exclusive_addr == addr && env->exclusive_val == [addr]) {
[addr] = {Rt};
diff --git a/target-arm/translate.h b/target-arm/translate.h
index a1eb5b5..9829576 100644
--- a/target-arm/translate.h
+++ b/target-arm/translate.h
@@ -9,7 +9,7 @@
/* Nonzero if this instruction has been conditionally skipped. */
int condjmp;
/* The label that will be jumped to when the instruction is skipped. */
- int condlabel;
+ TCGLabel *condlabel;
/* Thumb-2 conditional execution bits. */
int condexec_mask;
int condexec_cond;
@@ -119,6 +119,6 @@
}
#endif
-void arm_gen_test_cc(int cc, int label);
+void arm_gen_test_cc(int cc, TCGLabel *label);
#endif /* TARGET_ARM_TRANSLATE_H */
diff --git a/target-cris/translate.c b/target-cris/translate.c
index 47abcef..687c88b 100644
--- a/target-cris/translate.c
+++ b/target-cris/translate.c
@@ -311,9 +311,7 @@
static void t_gen_cris_dstep(TCGv d, TCGv a, TCGv b)
{
- int l1;
-
- l1 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
/*
* d <<= 1
@@ -509,9 +507,7 @@
static void t_gen_cc_jmp(TCGv pc_true, TCGv pc_false)
{
- int l1;
-
- l1 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
/* Conditional jmp. */
tcg_gen_mov_tl(env_pc, pc_false);
@@ -774,8 +770,7 @@
break;
case CC_OP_BOUND:
{
- int l1;
- l1 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
tcg_gen_mov_tl(dst, a);
tcg_gen_brcond_tl(TCG_COND_LEU, a, b, l1);
tcg_gen_mov_tl(dst, b);
@@ -1488,10 +1483,8 @@
cc_name(cond), dc->op1);
if (cond != CC_A) {
- int l1;
-
+ TCGLabel *l1 = gen_new_label();
gen_tst_cc(dc, cpu_R[dc->op1], cond);
- l1 = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_R[dc->op1], 0, l1);
tcg_gen_movi_tl(cpu_R[dc->op1], 1);
gen_set_label(l1);
@@ -3040,9 +3033,7 @@
#if !defined(CONFIG_USER_ONLY)
/* Single-stepping ? */
if (dc->tb_flags & S_FLAG) {
- int l1;
-
- l1 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_NE, cpu_PR[PR_SPC], dc->pc, l1);
/* We treat SPC as a break with an odd trap vector. */
cris_evaluate_flags(dc);
@@ -3256,9 +3247,7 @@
}
if (dc->jmp == JMP_DIRECT_CC) {
- int l1;
-
- l1 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
cris_evaluate_flags(dc);
/* Conditional jmp. */
diff --git a/target-cris/translate_v10.c b/target-cris/translate_v10.c
index efb3639..b742c4c 100644
--- a/target-cris/translate_v10.c
+++ b/target-cris/translate_v10.c
@@ -65,7 +65,7 @@
static void gen_store_v10_conditional(DisasContext *dc, TCGv addr, TCGv val,
unsigned int size, int mem_index)
{
- int l1 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
TCGv taddr = tcg_temp_local_new();
TCGv tval = tcg_temp_local_new();
TCGv t1 = tcg_temp_local_new();
@@ -537,10 +537,8 @@
if (cond != CC_A)
{
- int l1;
-
+ TCGLabel *l1 = gen_new_label();
gen_tst_cc (dc, cpu_R[dc->src], cond);
- l1 = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_R[dc->src], 0, l1);
tcg_gen_movi_tl(cpu_R[dc->src], 1);
gen_set_label(l1);
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 094cec0..305ce50 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -613,14 +613,14 @@
gen_ext_tl(reg, reg, ot, true);
}
-static inline void gen_op_jnz_ecx(TCGMemOp size, int label1)
+static inline void gen_op_jnz_ecx(TCGMemOp size, TCGLabel *label1)
{
tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]);
gen_extu(size, cpu_tmp0);
tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, label1);
}
-static inline void gen_op_jz_ecx(TCGMemOp size, int label1)
+static inline void gen_op_jz_ecx(TCGMemOp size, TCGLabel *label1)
{
tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]);
gen_extu(size, cpu_tmp0);
@@ -1078,7 +1078,7 @@
/* generate a conditional jump to label 'l1' according to jump opcode
value 'b'. In the fast case, T0 is guaranted not to be used. */
-static inline void gen_jcc1_noeob(DisasContext *s, int b, int l1)
+static inline void gen_jcc1_noeob(DisasContext *s, int b, TCGLabel *l1)
{
CCPrepare cc = gen_prepare_cc(s, b, cpu_T[0]);
@@ -1096,7 +1096,7 @@
/* Generate a conditional jump to label 'l1' according to jump opcode
value 'b'. In the fast case, T0 is guaranted not to be used.
A translation block must end soon. */
-static inline void gen_jcc1(DisasContext *s, int b, int l1)
+static inline void gen_jcc1(DisasContext *s, int b, TCGLabel *l1)
{
CCPrepare cc = gen_prepare_cc(s, b, cpu_T[0]);
@@ -1115,12 +1115,10 @@
/* XXX: does not work with gdbstub "ice" single step - not a
serious problem */
-static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip)
+static TCGLabel *gen_jz_ecx_string(DisasContext *s, target_ulong next_eip)
{
- int l1, l2;
-
- l1 = gen_new_label();
- l2 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
+ TCGLabel *l2 = gen_new_label();
gen_op_jnz_ecx(s->aflag, l1);
gen_set_label(l2);
gen_jmp_tb(s, next_eip, 1);
@@ -1213,7 +1211,7 @@
static inline void gen_repz_ ## op(DisasContext *s, TCGMemOp ot, \
target_ulong cur_eip, target_ulong next_eip) \
{ \
- int l2;\
+ TCGLabel *l2; \
gen_update_cc_op(s); \
l2 = gen_jz_ecx_string(s, next_eip); \
gen_ ## op(s, ot); \
@@ -1231,7 +1229,7 @@
target_ulong next_eip, \
int nz) \
{ \
- int l2;\
+ TCGLabel *l2; \
gen_update_cc_op(s); \
l2 = gen_jz_ecx_string(s, next_eip); \
gen_ ## op(s, ot); \
@@ -2227,7 +2225,7 @@
static inline void gen_jcc(DisasContext *s, int b,
target_ulong val, target_ulong next_eip)
{
- int l1, l2;
+ TCGLabel *l1, *l2;
if (s->jmp_opt) {
l1 = gen_new_label();
@@ -5152,7 +5150,7 @@
case 0x1b0:
case 0x1b1: /* cmpxchg Ev, Gv */
{
- int label1, label2;
+ TCGLabel *label1, *label2;
TCGv t0, t1, t2, a0;
ot = mo_b_d(b, dflag);
@@ -6196,7 +6194,8 @@
case 0x10 ... 0x13: /* fcmovxx */
case 0x18 ... 0x1b:
{
- int op1, l1;
+ int op1;
+ TCGLabel *l1;
static const uint8_t fcmov_cc[8] = {
(JCC_B << 1),
(JCC_Z << 1),
@@ -7017,7 +7016,7 @@
case 0xe2: /* loop */
case 0xe3: /* jecxz */
{
- int l1, l2, l3;
+ TCGLabel *l1, *l2, *l3;
tval = (int8_t)insn_get(env, s, MO_8);
next_eip = s->pc - s->cs_base;
@@ -7515,7 +7514,7 @@
} else
#endif
{
- int label1;
+ TCGLabel *label1;
TCGv t0, t1, t2, a0;
if (!s->pe || s->vm86)
@@ -7564,7 +7563,7 @@
case 0x102: /* lar */
case 0x103: /* lsl */
{
- int label1;
+ TCGLabel *label1;
TCGv t0;
if (!s->pe || s->vm86)
goto illegal_op;
diff --git a/target-lm32/translate.c b/target-lm32/translate.c
index 9d087b9..81a204f 100644
--- a/target-lm32/translate.c
+++ b/target-lm32/translate.c
@@ -219,7 +219,7 @@
/* restore IE.IE in case of an eret */
if (dc->r0 == R_EA) {
TCGv t0 = tcg_temp_new();
- int l1 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
tcg_gen_andi_tl(t0, cpu_ie, IE_EIE);
tcg_gen_ori_tl(cpu_ie, cpu_ie, IE_IE);
tcg_gen_brcondi_tl(TCG_COND_EQ, t0, IE_EIE, l1);
@@ -228,7 +228,7 @@
tcg_temp_free(t0);
} else if (dc->r0 == R_BA) {
TCGv t0 = tcg_temp_new();
- int l1 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
tcg_gen_andi_tl(t0, cpu_ie, IE_BIE);
tcg_gen_ori_tl(cpu_ie, cpu_ie, IE_IE);
tcg_gen_brcondi_tl(TCG_COND_EQ, t0, IE_BIE, l1);
@@ -252,9 +252,7 @@
static inline void gen_cond_branch(DisasContext *dc, int cond)
{
- int l1;
-
- l1 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
tcg_gen_brcond_tl(cond, cpu_R[dc->r0], cpu_R[dc->r1], l1);
gen_goto_tb(dc, 0, dc->pc + 4);
gen_set_label(l1);
@@ -428,7 +426,7 @@
static void dec_divu(DisasContext *dc)
{
- int l1;
+ TCGLabel *l1;
LOG_DIS("divu r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
@@ -508,7 +506,7 @@
static void dec_modu(DisasContext *dc)
{
- int l1;
+ TCGLabel *l1;
LOG_DIS("modu r%d, r%d, %d\n", dc->r2, dc->r0, dc->r1);
@@ -769,8 +767,8 @@
}
tcg_gen_sari_tl(cpu_R[dc->r1], cpu_R[dc->r0], dc->imm5);
} else {
- int l1 = gen_new_label();
- int l2 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
+ TCGLabel *l2 = gen_new_label();
TCGv t0 = tcg_temp_local_new();
tcg_gen_andi_tl(t0, cpu_R[dc->r1], 0x1f);
@@ -805,8 +803,8 @@
}
tcg_gen_shri_tl(cpu_R[dc->r1], cpu_R[dc->r0], dc->imm5);
} else {
- int l1 = gen_new_label();
- int l2 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
+ TCGLabel *l2 = gen_new_label();
TCGv t0 = tcg_temp_local_new();
tcg_gen_andi_tl(t0, cpu_R[dc->r1], 0x1f);
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index a39b495..4959b97 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -679,7 +679,7 @@
}
/* This generates a conditional branch, clobbering all temporaries. */
-static void gen_jmpcc(DisasContext *s, int cond, int l1)
+static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1)
{
TCGv tmp;
@@ -784,7 +784,7 @@
DISAS_INSN(scc)
{
- int l1;
+ TCGLabel *l1;
int cond;
TCGv reg;
@@ -1658,7 +1658,7 @@
int32_t offset;
uint32_t base;
int op;
- int l1;
+ TCGLabel *l1;
base = s->pc;
op = (insn >> 8) & 0xf;
@@ -2395,7 +2395,7 @@
uint32_t offset;
uint32_t addr;
TCGv flag;
- int l1;
+ TCGLabel *l1;
addr = s->pc;
offset = cpu_ldsw_code(env, s->pc);
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index 5ff3833..4068946 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -313,7 +313,7 @@
static void dec_pattern(DisasContext *dc)
{
unsigned int mode;
- int l1;
+ TCGLabel *l1;
if ((dc->tb_flags & MSR_EE_FLAG)
&& (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
@@ -1038,7 +1038,7 @@
static void dec_store(DisasContext *dc)
{
TCGv t, *addr, swx_addr;
- int swx_skip = 0;
+ TCGLabel *swx_skip = NULL;
unsigned int size, rev = 0, ex = 0;
TCGMemOp mop;
@@ -1192,9 +1192,7 @@
static void eval_cond_jmp(DisasContext *dc, TCGv pc_true, TCGv pc_false)
{
- int l1;
-
- l1 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
/* Conditional jmp. */
tcg_gen_mov_tl(cpu_SR[SR_PC], pc_false);
tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, l1);
@@ -1773,10 +1771,8 @@
gen_goto_tb(dc, 0, dc->jmp_pc);
dc->is_jmp = DISAS_TB_JUMP;
} else if (dc->jmp == JMP_DIRECT_CC) {
- int l1;
-
+ TCGLabel *l1 = gen_new_label();
t_sync_flags(dc);
- l1 = gen_new_label();
/* Conditional jmp. */
tcg_gen_brcondi_tl(TCG_COND_NE, env_btaken, 0, l1);
gen_goto_tb(dc, 1, dc->pc);
diff --git a/target-mips/translate.c b/target-mips/translate.c
index ca51149..9059bfd 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -1998,8 +1998,8 @@
static inline void op_st_##insn(TCGv arg1, TCGv arg2, int rt, DisasContext *ctx) \
{ \
TCGv t0 = tcg_temp_new(); \
- int l1 = gen_new_label(); \
- int l2 = gen_new_label(); \
+ TCGLabel *l1 = gen_new_label(); \
+ TCGLabel *l2 = gen_new_label(); \
\
tcg_gen_andi_tl(t0, arg2, almask); \
tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); \
@@ -2428,7 +2428,7 @@
TCGv t0 = tcg_temp_local_new();
TCGv t1 = tcg_temp_new();
TCGv t2 = tcg_temp_new();
- int l1 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
gen_load_gpr(t1, rs);
tcg_gen_addi_tl(t0, t1, uimm);
@@ -2464,7 +2464,7 @@
TCGv t0 = tcg_temp_local_new();
TCGv t1 = tcg_temp_new();
TCGv t2 = tcg_temp_new();
- int l1 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
gen_load_gpr(t1, rs);
tcg_gen_addi_tl(t0, t1, uimm);
@@ -2694,7 +2694,7 @@
TCGv t0 = tcg_temp_local_new();
TCGv t1 = tcg_temp_new();
TCGv t2 = tcg_temp_new();
- int l1 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
gen_load_gpr(t1, rs);
gen_load_gpr(t2, rt);
@@ -2732,7 +2732,7 @@
TCGv t0 = tcg_temp_local_new();
TCGv t1 = tcg_temp_new();
TCGv t2 = tcg_temp_new();
- int l1 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
gen_load_gpr(t1, rs);
gen_load_gpr(t2, rt);
@@ -2772,7 +2772,7 @@
TCGv t0 = tcg_temp_local_new();
TCGv t1 = tcg_temp_new();
TCGv t2 = tcg_temp_new();
- int l1 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
gen_load_gpr(t1, rs);
gen_load_gpr(t2, rt);
@@ -2808,7 +2808,7 @@
TCGv t0 = tcg_temp_local_new();
TCGv t1 = tcg_temp_new();
TCGv t2 = tcg_temp_new();
- int l1 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
gen_load_gpr(t1, rs);
gen_load_gpr(t2, rt);
@@ -3846,9 +3846,9 @@
case OPC_DIV_G_2E:
case OPC_DIV_G_2F:
{
- int l1 = gen_new_label();
- int l2 = gen_new_label();
- int l3 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
+ TCGLabel *l2 = gen_new_label();
+ TCGLabel *l3 = gen_new_label();
tcg_gen_ext32s_tl(t0, t0);
tcg_gen_ext32s_tl(t1, t1);
tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
@@ -3869,8 +3869,8 @@
case OPC_DIVU_G_2E:
case OPC_DIVU_G_2F:
{
- int l1 = gen_new_label();
- int l2 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
+ TCGLabel *l2 = gen_new_label();
tcg_gen_ext32u_tl(t0, t0);
tcg_gen_ext32u_tl(t1, t1);
tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
@@ -3886,9 +3886,9 @@
case OPC_MOD_G_2E:
case OPC_MOD_G_2F:
{
- int l1 = gen_new_label();
- int l2 = gen_new_label();
- int l3 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
+ TCGLabel *l2 = gen_new_label();
+ TCGLabel *l3 = gen_new_label();
tcg_gen_ext32u_tl(t0, t0);
tcg_gen_ext32u_tl(t1, t1);
tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
@@ -3907,8 +3907,8 @@
case OPC_MODU_G_2E:
case OPC_MODU_G_2F:
{
- int l1 = gen_new_label();
- int l2 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
+ TCGLabel *l2 = gen_new_label();
tcg_gen_ext32u_tl(t0, t0);
tcg_gen_ext32u_tl(t1, t1);
tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
@@ -3935,9 +3935,9 @@
case OPC_DDIV_G_2E:
case OPC_DDIV_G_2F:
{
- int l1 = gen_new_label();
- int l2 = gen_new_label();
- int l3 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
+ TCGLabel *l2 = gen_new_label();
+ TCGLabel *l3 = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
tcg_gen_movi_tl(cpu_gpr[rd], 0);
tcg_gen_br(l3);
@@ -3955,8 +3955,8 @@
case OPC_DDIVU_G_2E:
case OPC_DDIVU_G_2F:
{
- int l1 = gen_new_label();
- int l2 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
+ TCGLabel *l2 = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
tcg_gen_movi_tl(cpu_gpr[rd], 0);
tcg_gen_br(l2);
@@ -3969,9 +3969,9 @@
case OPC_DMOD_G_2E:
case OPC_DMOD_G_2F:
{
- int l1 = gen_new_label();
- int l2 = gen_new_label();
- int l3 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
+ TCGLabel *l2 = gen_new_label();
+ TCGLabel *l3 = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2);
tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2);
@@ -3987,8 +3987,8 @@
case OPC_DMODU_G_2E:
case OPC_DMODU_G_2F:
{
- int l1 = gen_new_label();
- int l2 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
+ TCGLabel *l2 = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
tcg_gen_movi_tl(cpu_gpr[rd], 0);
tcg_gen_br(l2);
@@ -4204,7 +4204,7 @@
case OPC_DADD_CP2:
{
TCGv_i64 t2 = tcg_temp_new_i64();
- int lab = gen_new_label();
+ TCGLabel *lab = gen_new_label();
tcg_gen_mov_i64(t2, t0);
tcg_gen_add_i64(t0, t1, t2);
@@ -4227,7 +4227,7 @@
case OPC_DSUB_CP2:
{
TCGv_i64 t2 = tcg_temp_new_i64();
- int lab = gen_new_label();
+ TCGLabel *lab = gen_new_label();
tcg_gen_mov_i64(t2, t0);
tcg_gen_sub_i64(t0, t1, t2);
@@ -4338,7 +4338,7 @@
break;
}
} else {
- int l1 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
switch (opc) {
case OPC_TEQ:
@@ -8430,7 +8430,7 @@
static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf)
{
- int l1;
+ TCGLabel *l1;
TCGCond cond;
TCGv_i32 t0;
@@ -8461,7 +8461,7 @@
{
int cond;
TCGv_i32 t0 = tcg_temp_new_i32();
- int l1 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
if (tf)
cond = TCG_COND_EQ;
@@ -8481,7 +8481,7 @@
int cond;
TCGv_i32 t0 = tcg_temp_new_i32();
TCGv_i64 fp0;
- int l1 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
if (tf)
cond = TCG_COND_EQ;
@@ -8503,8 +8503,8 @@
{
int cond;
TCGv_i32 t0 = tcg_temp_new_i32();
- int l1 = gen_new_label();
- int l2 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
+ TCGLabel *l2 = gen_new_label();
if (tf)
cond = TCG_COND_EQ;
@@ -8869,7 +8869,7 @@
case OPC_MOVZ_S:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
{
- int l1 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
TCGv_i32 fp0;
if (ft != 0) {
@@ -8886,7 +8886,7 @@
case OPC_MOVN_S:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
{
- int l1 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
TCGv_i32 fp0;
if (ft != 0) {
@@ -9414,7 +9414,7 @@
case OPC_MOVZ_D:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
{
- int l1 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
TCGv_i64 fp0;
if (ft != 0) {
@@ -9431,7 +9431,7 @@
case OPC_MOVN_D:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
{
- int l1 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
TCGv_i64 fp0;
if (ft != 0) {
@@ -9852,7 +9852,7 @@
case OPC_MOVZ_PS:
check_cp1_64bitmode(ctx);
{
- int l1 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
TCGv_i64 fp0;
if (ft != 0)
@@ -9868,7 +9868,7 @@
case OPC_MOVN_PS:
check_cp1_64bitmode(ctx);
{
- int l1 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
TCGv_i64 fp0;
if (ft != 0) {
@@ -10212,8 +10212,8 @@
TCGv t0 = tcg_temp_local_new();
TCGv_i32 fp = tcg_temp_new_i32();
TCGv_i32 fph = tcg_temp_new_i32();
- int l1 = gen_new_label();
- int l2 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
+ TCGLabel *l2 = gen_new_label();
gen_load_gpr(t0, fr);
tcg_gen_andi_tl(t0, t0, 0x7);
@@ -10562,7 +10562,7 @@
/* Conditional branch */
MIPS_DEBUG("conditional branch");
{
- int l1 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1);
gen_goto_tb(ctx, 1, ctx->pc + insn_bytes);
@@ -15998,7 +15998,7 @@
gen_branch(ctx, 4);
} else {
/* Conditional compact branch */
- int fs = gen_new_label();
+ TCGLabel *fs = gen_new_label();
save_cpu_state(ctx, 0);
switch (opc) {
@@ -18443,7 +18443,7 @@
/* Handle blikely not taken case */
if ((ctx->hflags & MIPS_HFLAG_BMASK_BASE) == MIPS_HFLAG_BL) {
- int l1 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
MIPS_DEBUG("blikely condition (" TARGET_FMT_lx ")", ctx->pc + 4);
tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1);
diff --git a/target-moxie/translate.c b/target-moxie/translate.c
index c416eca..e3e9139 100644
--- a/target-moxie/translate.c
+++ b/target-moxie/translate.c
@@ -169,7 +169,7 @@
#define BRANCH(cond) \
do { \
- int l1 = gen_new_label(); \
+ TCGLabel *l1 = gen_new_label(); \
tcg_gen_brcond_i32(cond, cc_a, cc_b, l1); \
gen_goto_tb(env, ctx, 1, ctx->pc+2); \
gen_set_label(l1); \
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index 6ef447b..dc76789 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@@ -118,9 +118,7 @@
/* Writeback SR_F translation space to execution space. */
static inline void wb_SR_F(void)
{
- int label;
-
- label = gen_new_label();
+ TCGLabel *label = gen_new_label();
tcg_gen_andi_tl(cpu_sr, cpu_sr, ~SR_F);
tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, label);
tcg_gen_ori_tl(cpu_sr, cpu_sr, SR_F);
@@ -226,7 +224,7 @@
case 0x03: /* l.bnf */
case 0x04: /* l.bf */
{
- int lab = gen_new_label();
+ TCGLabel *lab = gen_new_label();
TCGv sr_f = tcg_temp_new();
tcg_gen_movi_tl(jmp_pc, dc->pc+8);
tcg_gen_andi_tl(sr_f, cpu_sr, SR_F);
@@ -272,7 +270,7 @@
case 0x00: /* l.add */
LOG_DIS("l.add r%d, r%d, r%d\n", rd, ra, rb);
{
- int lab = gen_new_label();
+ TCGLabel *lab = gen_new_label();
TCGv_i64 ta = tcg_temp_new_i64();
TCGv_i64 tb = tcg_temp_new_i64();
TCGv_i64 td = tcg_temp_local_new_i64();
@@ -311,7 +309,7 @@
case 0x00:
LOG_DIS("l.addc r%d, r%d, r%d\n", rd, ra, rb);
{
- int lab = gen_new_label();
+ TCGLabel *lab = gen_new_label();
TCGv_i64 ta = tcg_temp_new_i64();
TCGv_i64 tb = tcg_temp_new_i64();
TCGv_i64 tcy = tcg_temp_local_new_i64();
@@ -358,7 +356,7 @@
case 0x00:
LOG_DIS("l.sub r%d, r%d, r%d\n", rd, ra, rb);
{
- int lab = gen_new_label();
+ TCGLabel *lab = gen_new_label();
TCGv_i64 ta = tcg_temp_new_i64();
TCGv_i64 tb = tcg_temp_new_i64();
TCGv_i64 td = tcg_temp_local_new_i64();
@@ -450,10 +448,10 @@
case 0x03: /* l.div */
LOG_DIS("l.div r%d, r%d, r%d\n", rd, ra, rb);
{
- int lab0 = gen_new_label();
- int lab1 = gen_new_label();
- int lab2 = gen_new_label();
- int lab3 = gen_new_label();
+ TCGLabel *lab0 = gen_new_label();
+ TCGLabel *lab1 = gen_new_label();
+ TCGLabel *lab2 = gen_new_label();
+ TCGLabel *lab3 = gen_new_label();
TCGv_i32 sr_ove = tcg_temp_local_new_i32();
if (rb == 0) {
tcg_gen_ori_tl(cpu_sr, cpu_sr, (SR_OV | SR_CY));
@@ -492,9 +490,9 @@
case 0x03: /* l.divu */
LOG_DIS("l.divu r%d, r%d, r%d\n", rd, ra, rb);
{
- int lab0 = gen_new_label();
- int lab1 = gen_new_label();
- int lab2 = gen_new_label();
+ TCGLabel *lab0 = gen_new_label();
+ TCGLabel *lab1 = gen_new_label();
+ TCGLabel *lab2 = gen_new_label();
TCGv_i32 sr_ove = tcg_temp_local_new_i32();
if (rb == 0) {
tcg_gen_ori_tl(cpu_sr, cpu_sr, (SR_OV | SR_CY));
@@ -533,7 +531,7 @@
TCGv_i64 trb = tcg_temp_local_new_i64();
TCGv_i64 high = tcg_temp_new_i64();
TCGv_i32 sr_ove = tcg_temp_local_new_i32();
- int lab = gen_new_label();
+ TCGLabel *lab = gen_new_label();
/* Calculate each result. */
tcg_gen_extu_i32_i64(tra, cpu_R[ra]);
tcg_gen_extu_i32_i64(trb, cpu_R[rb]);
@@ -568,7 +566,7 @@
case 0x00: /* l.cmov */
LOG_DIS("l.cmov r%d, r%d, r%d\n", rd, ra, rb);
{
- int lab = gen_new_label();
+ TCGLabel *lab = gen_new_label();
TCGv res = tcg_temp_local_new();
TCGv sr_f = tcg_temp_new();
tcg_gen_andi_tl(sr_f, cpu_sr, SR_F);
@@ -893,7 +891,7 @@
if (I16 == 0) {
tcg_gen_mov_tl(cpu_R[rd], cpu_R[ra]);
} else {
- int lab = gen_new_label();
+ TCGLabel *lab = gen_new_label();
TCGv_i64 ta = tcg_temp_new_i64();
TCGv_i64 td = tcg_temp_local_new_i64();
TCGv_i32 res = tcg_temp_local_new_i32();
@@ -923,7 +921,7 @@
case 0x28: /* l.addic */
LOG_DIS("l.addic r%d, r%d, %d\n", rd, ra, I16);
{
- int lab = gen_new_label();
+ TCGLabel *lab = gen_new_label();
TCGv_i64 ta = tcg_temp_new_i64();
TCGv_i64 td = tcg_temp_local_new_i64();
TCGv_i64 tcy = tcg_temp_local_new_i64();
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 2a78e99..8f255ea 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -753,7 +753,7 @@
/* isel (PowerPC 2.03 specification) */
static void gen_isel(DisasContext *ctx)
{
- int l1, l2;
+ TCGLabel *l1, *l2;
uint32_t bi = rC(ctx->opcode);
uint32_t mask;
TCGv_i32 t0;
@@ -944,8 +944,8 @@
static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
TCGv arg2, int sign, int compute_ov)
{
- int l1 = gen_new_label();
- int l2 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
+ TCGLabel *l2 = gen_new_label();
TCGv_i32 t0 = tcg_temp_local_new_i32();
TCGv_i32 t1 = tcg_temp_local_new_i32();
@@ -953,7 +953,7 @@
tcg_gen_trunc_tl_i32(t1, arg2);
tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
if (sign) {
- int l3 = gen_new_label();
+ TCGLabel *l3 = gen_new_label();
tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
gen_set_label(l3);
@@ -1019,12 +1019,12 @@
static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
TCGv arg2, int sign, int compute_ov)
{
- int l1 = gen_new_label();
- int l2 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
+ TCGLabel *l2 = gen_new_label();
tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
if (sign) {
- int l3 = gen_new_label();
+ TCGLabel *l3 = gen_new_label();
tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
gen_set_label(l3);
@@ -2715,7 +2715,7 @@
static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
{
- int l1 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
TCGv t0 = tcg_temp_new();
TCGv_i32 t1, t2;
/* NIP cannot be restored if the memory exception comes from an helper */
@@ -3348,7 +3348,7 @@
static void gen_conditional_store(DisasContext *ctx, TCGv EA,
int reg, int size)
{
- int l1;
+ TCGLabel *l1;
tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
l1 = gen_new_label();
@@ -3879,7 +3879,7 @@
static inline void gen_bcond(DisasContext *ctx, int type)
{
uint32_t bo = BO(ctx->opcode);
- int l1;
+ TCGLabel *l1;
TCGv target;
ctx->exception = POWERPC_EXCP_BRANCH;
@@ -4922,8 +4922,8 @@
/* abs - abs. */
static void gen_abs(DisasContext *ctx)
{
- int l1 = gen_new_label();
- int l2 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
+ TCGLabel *l2 = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
tcg_gen_br(l2);
@@ -4937,9 +4937,9 @@
/* abso - abso. */
static void gen_abso(DisasContext *ctx)
{
- int l1 = gen_new_label();
- int l2 = gen_new_label();
- int l3 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
+ TCGLabel *l2 = gen_new_label();
+ TCGLabel *l3 = gen_new_label();
/* Start with XER OV disabled, the most likely case */
tcg_gen_movi_tl(cpu_ov, 0);
tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
@@ -5005,8 +5005,8 @@
/* doz - doz. */
static void gen_doz(DisasContext *ctx)
{
- int l1 = gen_new_label();
- int l2 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
+ TCGLabel *l2 = gen_new_label();
tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
tcg_gen_br(l2);
@@ -5020,8 +5020,8 @@
/* dozo - dozo. */
static void gen_dozo(DisasContext *ctx)
{
- int l1 = gen_new_label();
- int l2 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
+ TCGLabel *l2 = gen_new_label();
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
TCGv t2 = tcg_temp_new();
@@ -5051,8 +5051,8 @@
static void gen_dozi(DisasContext *ctx)
{
target_long simm = SIMM(ctx->opcode);
- int l1 = gen_new_label();
- int l2 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
+ TCGLabel *l2 = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
tcg_gen_br(l2);
@@ -5088,7 +5088,7 @@
/* maskg - maskg. */
static void gen_maskg(DisasContext *ctx)
{
- int l1 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
TCGv t2 = tcg_temp_new();
@@ -5148,7 +5148,7 @@
/* mulo - mulo. */
static void gen_mulo(DisasContext *ctx)
{
- int l1 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
TCGv_i64 t0 = tcg_temp_new_i64();
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv t2 = tcg_temp_new();
@@ -5176,8 +5176,8 @@
/* nabs - nabs. */
static void gen_nabs(DisasContext *ctx)
{
- int l1 = gen_new_label();
- int l2 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
+ TCGLabel *l2 = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
tcg_gen_br(l2);
@@ -5191,8 +5191,8 @@
/* nabso - nabso. */
static void gen_nabso(DisasContext *ctx)
{
- int l1 = gen_new_label();
- int l2 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
+ TCGLabel *l2 = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
tcg_gen_br(l2);
@@ -5317,8 +5317,8 @@
/* sllq - sllq. */
static void gen_sllq(DisasContext *ctx)
{
- int l1 = gen_new_label();
- int l2 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
+ TCGLabel *l2 = gen_new_label();
TCGv t0 = tcg_temp_local_new();
TCGv t1 = tcg_temp_local_new();
TCGv t2 = tcg_temp_local_new();
@@ -5346,7 +5346,7 @@
/* slq - slq. */
static void gen_slq(DisasContext *ctx)
{
- int l1 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
@@ -5370,7 +5370,7 @@
static void gen_sraiq(DisasContext *ctx)
{
int sh = SH(ctx->opcode);
- int l1 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
@@ -5392,8 +5392,8 @@
/* sraq - sraq. */
static void gen_sraq(DisasContext *ctx)
{
- int l1 = gen_new_label();
- int l2 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
+ TCGLabel *l2 = gen_new_label();
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_local_new();
TCGv t2 = tcg_temp_local_new();
@@ -5515,8 +5515,8 @@
/* srlq */
static void gen_srlq(DisasContext *ctx)
{
- int l1 = gen_new_label();
- int l2 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
+ TCGLabel *l2 = gen_new_label();
TCGv t0 = tcg_temp_local_new();
TCGv t1 = tcg_temp_local_new();
TCGv t2 = tcg_temp_local_new();
@@ -5545,7 +5545,7 @@
/* srq */
static void gen_srq(DisasContext *ctx)
{
- int l1 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
@@ -5979,7 +5979,7 @@
if (opc3 & 0x12) {
/* Check overflow and/or saturate */
- int l1 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
if (opc3 & 0x10) {
/* Start with XER OV disabled, the most likely case */
@@ -6394,7 +6394,7 @@
gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
tcg_temp_free(t0);
if (Rc(ctx->opcode)) {
- int l1 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
@@ -6475,7 +6475,7 @@
gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
tcg_temp_free(t0);
if (Rc(ctx->opcode)) {
- int l1 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
@@ -8576,8 +8576,8 @@
static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
{
- int l1 = gen_new_label();
- int l2 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
+ TCGLabel *l2 = gen_new_label();
tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
tcg_gen_neg_i32(ret, arg1);
@@ -8626,12 +8626,10 @@
static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{
- TCGv_i32 t0;
- int l1, l2;
+ TCGLabel *l1 = gen_new_label();
+ TCGLabel *l2 = gen_new_label();
+ TCGv_i32 t0 = tcg_temp_local_new_i32();
- l1 = gen_new_label();
- l2 = gen_new_label();
- t0 = tcg_temp_local_new_i32();
/* No error here: 6 bits are used */
tcg_gen_andi_i32(t0, arg2, 0x3F);
tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
@@ -8645,12 +8643,10 @@
GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{
- TCGv_i32 t0;
- int l1, l2;
+ TCGLabel *l1 = gen_new_label();
+ TCGLabel *l2 = gen_new_label();
+ TCGv_i32 t0 = tcg_temp_local_new_i32();
- l1 = gen_new_label();
- l2 = gen_new_label();
- t0 = tcg_temp_local_new_i32();
/* No error here: 6 bits are used */
tcg_gen_andi_i32(t0, arg2, 0x3F);
tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
@@ -8664,12 +8660,10 @@
GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{
- TCGv_i32 t0;
- int l1, l2;
+ TCGLabel *l1 = gen_new_label();
+ TCGLabel *l2 = gen_new_label();
+ TCGv_i32 t0 = tcg_temp_local_new_i32();
- l1 = gen_new_label();
- l2 = gen_new_label();
- t0 = tcg_temp_local_new_i32();
/* No error here: 6 bits are used */
tcg_gen_andi_i32(t0, arg2, 0x3F);
tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
@@ -8737,10 +8731,10 @@
gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \
} \
- int l1 = gen_new_label(); \
- int l2 = gen_new_label(); \
- int l3 = gen_new_label(); \
- int l4 = gen_new_label(); \
+ TCGLabel *l1 = gen_new_label(); \
+ TCGLabel *l2 = gen_new_label(); \
+ TCGLabel *l3 = gen_new_label(); \
+ TCGLabel *l4 = gen_new_label(); \
\
tcg_gen_ext32s_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
tcg_gen_ext32s_tl(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
@@ -8830,11 +8824,12 @@
static inline void gen_evsel(DisasContext *ctx)
{
- int l1 = gen_new_label();
- int l2 = gen_new_label();
- int l3 = gen_new_label();
- int l4 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
+ TCGLabel *l2 = gen_new_label();
+ TCGLabel *l3 = gen_new_label();
+ TCGLabel *l4 = gen_new_label();
TCGv_i32 t0 = tcg_temp_local_new_i32();
+
tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index c73ea61..4f82edd 100644
--- a/target-s390x/translate.c
+++ b/target-s390x/translate.c
@@ -1177,7 +1177,7 @@
{
ExitStatus ret;
uint64_t dest = s->pc + 2 * imm;
- int lab;
+ TCGLabel *lab;
/* Take care of the special cases first. */
if (c->cond == TCG_COND_NEVER) {
@@ -1953,7 +1953,7 @@
static ExitStatus op_ct(DisasContext *s, DisasOps *o)
{
int m3 = get_field(s->fields, m3);
- int lab = gen_new_label();
+ TCGLabel *lab = gen_new_label();
TCGv_i32 t;
TCGCond c;
@@ -3077,7 +3077,8 @@
{
DisasCompare c;
TCGv_i64 a;
- int lab, r1;
+ TCGLabel *lab;
+ int r1;
disas_jcc(s, &c, get_field(s->fields, m3));
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 4c95ac7..41aa928 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -211,7 +211,7 @@
static inline void gen_branch_slot(uint32_t delayed_pc, int t)
{
TCGv sr;
- int label = gen_new_label();
+ TCGLabel *label = gen_new_label();
tcg_gen_movi_i32(cpu_delayed_pc, delayed_pc);
sr = tcg_temp_new();
tcg_gen_andi_i32(sr, cpu_sr, SR_T);
@@ -224,7 +224,7 @@
static void gen_conditional_jump(DisasContext * ctx,
target_ulong ift, target_ulong ifnott)
{
- int l1;
+ TCGLabel *l1;
TCGv sr;
l1 = gen_new_label();
@@ -239,7 +239,7 @@
/* Delayed conditional jump (bt or bf) */
static void gen_delayed_conditional_jump(DisasContext * ctx)
{
- int l1;
+ TCGLabel *l1;
TCGv ds;
l1 = gen_new_label();
@@ -850,10 +850,10 @@
return;
case 0x400c: /* shad Rm,Rn */
{
- int label1 = gen_new_label();
- int label2 = gen_new_label();
- int label3 = gen_new_label();
- int label4 = gen_new_label();
+ TCGLabel *label1 = gen_new_label();
+ TCGLabel *label2 = gen_new_label();
+ TCGLabel *label3 = gen_new_label();
+ TCGLabel *label4 = gen_new_label();
TCGv shift;
tcg_gen_brcondi_i32(TCG_COND_LT, REG(B7_4), 0, label1);
/* Rm positive, shift to the left */
@@ -885,9 +885,9 @@
return;
case 0x400d: /* shld Rm,Rn */
{
- int label1 = gen_new_label();
- int label2 = gen_new_label();
- int label3 = gen_new_label();
+ TCGLabel *label1 = gen_new_label();
+ TCGLabel *label2 = gen_new_label();
+ TCGLabel *label3 = gen_new_label();
TCGv shift;
tcg_gen_brcondi_i32(TCG_COND_LT, REG(B7_4), 0, label1);
/* Rm positive, shift to the left */
@@ -1554,7 +1554,7 @@
0 -> LDST
*/
if (ctx->features & SH_FEATURE_SH4A) {
- int label = gen_new_label();
+ TCGLabel *label = gen_new_label();
tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
tcg_gen_or_i32(cpu_sr, cpu_sr, cpu_ldst);
tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_ldst, 0, label);
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index bd53950..3708c01 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -945,9 +945,7 @@
static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
target_ulong pc2, TCGv r_cond)
{
- int l1;
-
- l1 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
@@ -960,9 +958,7 @@
static inline void gen_branch_a(DisasContext *dc, target_ulong pc1,
target_ulong pc2, TCGv r_cond)
{
- int l1;
-
- l1 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
@@ -2605,7 +2601,8 @@
if (xop == 0x3a) { /* generate trap */
int cond = GET_FIELD(insn, 3, 6);
TCGv_i32 trap;
- int l1 = -1, mask;
+ TCGLabel *l1 = NULL;
+ int mask;
if (cond == 0) {
/* Trap never. */
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index f720cd7..27777be 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -2491,8 +2491,7 @@
static inline void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r1,
TCGv r2, int16_t address)
{
- int jumpLabel;
- jumpLabel = gen_new_label();
+ TCGLabel *jumpLabel = gen_new_label();
tcg_gen_brcond_tl(cond, r1, r2, jumpLabel);
gen_goto_tb(ctx, 1, ctx->next_pc);
@@ -2511,8 +2510,7 @@
static void gen_loop(DisasContext *ctx, int r1, int32_t offset)
{
- int l1;
- l1 = gen_new_label();
+ TCGLabel *l1 = gen_new_label();
tcg_gen_subi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], 1);
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr_a[r1], -1, l1);
diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c
index db453ef..9efcff5 100644
--- a/target-unicore32/translate.c
+++ b/target-unicore32/translate.c
@@ -33,7 +33,7 @@
/* Nonzero if this instruction has been conditionally skipped. */
int condjmp;
/* The label that will be jumped to when the instruction is skipped. */
- int condlabel;
+ TCGLabel *condlabel;
struct TranslationBlock *tb;
int singlestep_enabled;
#ifndef CONFIG_USER_ONLY
@@ -419,11 +419,11 @@
dead_tmp(shift);
}
-static void gen_test_cc(int cc, int label)
+static void gen_test_cc(int cc, TCGLabel *label)
{
TCGv tmp;
TCGv tmp2;
- int inv;
+ TCGLabel *inv;
switch (cc) {
case 0: /* eq: Z */
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index f112e2a..6e5096c 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -456,7 +456,7 @@
if (option_enabled(dc, XTENSA_OPTION_LOOP) &&
!(dc->tb->flags & XTENSA_TBFLAG_EXCM) &&
dc->next_pc == dc->lend) {
- int label = gen_new_label();
+ TCGLabel *label = gen_new_label();
gen_advance_ccount(dc);
tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_SR[LCOUNT], 0, label);
@@ -479,7 +479,7 @@
static void gen_brcond(DisasContext *dc, TCGCond cond,
TCGv_i32 t0, TCGv_i32 t1, uint32_t offset)
{
- int label = gen_new_label();
+ TCGLabel *label = gen_new_label();
gen_advance_ccount(dc);
tcg_gen_brcond_i32(cond, t0, t1, label);
@@ -808,7 +808,7 @@
tcg_gen_andi_i32(addr, addr, ~0 << shift);
} else if (option_enabled(dc, XTENSA_OPTION_HW_ALIGNMENT) &&
no_hw_alignment) {
- int label = gen_new_label();
+ TCGLabel *label = gen_new_label();
TCGv_i32 tmp = tcg_temp_new_i32();
tcg_gen_andi_i32(tmp, addr, ~(~0 << shift));
tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
@@ -1642,7 +1642,7 @@
if (OP2 >= 12) {
HAS_OPTION(XTENSA_OPTION_32_BIT_IDIV);
- int label = gen_new_label();
+ TCGLabel *label = gen_new_label();
tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0, label);
gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE);
gen_set_label(label);
@@ -1714,8 +1714,8 @@
case 13: /*QUOSi*/
case 15: /*REMSi*/
{
- int label1 = gen_new_label();
- int label2 = gen_new_label();
+ TCGLabel *label1 = gen_new_label();
+ TCGLabel *label2 = gen_new_label();
tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_S], 0x80000000,
label1);
@@ -2468,7 +2468,7 @@
case 14: /*S32C1Iy*/
HAS_OPTION(XTENSA_OPTION_CONDITIONAL_STORE);
if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
- int label = gen_new_label();
+ TCGLabel *label = gen_new_label();
TCGv_i32 tmp = tcg_temp_local_new_i32();
TCGv_i32 addr = tcg_temp_local_new_i32();
TCGv_i32 tpc;
@@ -2746,7 +2746,7 @@
tcg_temp_free(tmp);
if (BRI8_R > 8) {
- int label = gen_new_label();
+ TCGLabel *label = gen_new_label();
tcg_gen_brcondi_i32(
BRI8_R == 9 ? TCG_COND_NE : TCG_COND_GT,
cpu_R[RRI8_S], 0, label);
@@ -3087,7 +3087,7 @@
}
if (dc.icount) {
- int label = gen_new_label();
+ TCGLabel *label = gen_new_label();
tcg_gen_addi_i32(dc.next_icount, cpu_SR[ICOUNT], 1);
tcg_gen_brcondi_i32(TCG_COND_NE, dc.next_icount, 0, label);
diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c
index 4133dcf..1462843 100644
--- a/tcg/i386/tcg-target.c
+++ b/tcg/i386/tcg-target.c
@@ -936,8 +936,8 @@
static void tcg_out_brcond2(TCGContext *s, const TCGArg *args,
const int *const_args, int small)
{
- int label_next;
- label_next = gen_new_label();
+ int label_next = label_arg(gen_new_label());
+
switch(args[4]) {
case TCG_COND_EQ:
tcg_out_brcond32(s, TCG_COND_NE, args[0], args[2], const_args[2],
@@ -1044,8 +1044,8 @@
|| (!const_args[4] && args[0] == args[4])) {
/* When the destination overlaps with one of the argument
registers, don't do anything tricky. */
- label_true = gen_new_label();
- label_over = gen_new_label();
+ label_true = label_arg(gen_new_label());
+ label_over = label_arg(gen_new_label());
new_args[5] = label_true;
tcg_out_brcond2(s, new_args, const_args+1, 1);
@@ -1063,7 +1063,7 @@
tcg_out_movi(s, TCG_TYPE_I32, args[0], 0);
- label_over = gen_new_label();
+ label_over = label_arg(gen_new_label());
new_args[4] = tcg_invert_cond(new_args[4]);
new_args[5] = label_over;
tcg_out_brcond2(s, new_args, const_args+1, 1);
@@ -1082,7 +1082,7 @@
if (have_cmov) {
tcg_out_modrm(s, OPC_CMOVCC | tcg_cond_to_jcc[cond], dest, v1);
} else {
- int over = gen_new_label();
+ int over = label_arg(gen_new_label());
tcg_out_jxx(s, tcg_cond_to_jcc[tcg_invert_cond(cond)], over, 1);
tcg_out_mov(s, TCG_TYPE_I32, dest, v1);
tcg_out_label(s, over, s->code_ptr);
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index afa351d..6674bb4 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -275,19 +275,19 @@
}
}
-void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, int label)
+void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, TCGLabel *l)
{
if (cond == TCG_COND_ALWAYS) {
- tcg_gen_br(label);
+ tcg_gen_br(l);
} else if (cond != TCG_COND_NEVER) {
- tcg_gen_op4ii_i32(INDEX_op_brcond_i32, arg1, arg2, cond, label);
+ tcg_gen_op4ii_i32(INDEX_op_brcond_i32, arg1, arg2, cond, label_arg(l));
}
}
-void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, int label)
+void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLabel *l)
{
TCGv_i32 t0 = tcg_const_i32(arg2);
- tcg_gen_brcond_i32(cond, arg1, t0, label);
+ tcg_gen_brcond_i32(cond, arg1, t0, l);
tcg_temp_free_i32(t0);
}
@@ -1084,28 +1084,29 @@
}
}
-void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, int label)
+void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, TCGLabel *l)
{
if (cond == TCG_COND_ALWAYS) {
- tcg_gen_br(label);
+ tcg_gen_br(l);
} else if (cond != TCG_COND_NEVER) {
if (TCG_TARGET_REG_BITS == 32) {
tcg_gen_op6ii_i32(INDEX_op_brcond2_i32, TCGV_LOW(arg1),
TCGV_HIGH(arg1), TCGV_LOW(arg2),
- TCGV_HIGH(arg2), cond, label);
+ TCGV_HIGH(arg2), cond, label_arg(l));
} else {
- tcg_gen_op4ii_i64(INDEX_op_brcond_i64, arg1, arg2, cond, label);
+ tcg_gen_op4ii_i64(INDEX_op_brcond_i64, arg1, arg2, cond,
+ label_arg(l));
}
}
}
-void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, int label)
+void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, TCGLabel *l)
{
if (cond == TCG_COND_ALWAYS) {
- tcg_gen_br(label);
+ tcg_gen_br(l);
} else if (cond != TCG_COND_NEVER) {
TCGv_i64 t0 = tcg_const_i64(arg2);
- tcg_gen_brcond_i64(cond, arg1, t0, label);
+ tcg_gen_brcond_i64(cond, arg1, t0, l);
tcg_temp_free_i64(t0);
}
}
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index 96adf9a..d1d763f 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -251,19 +251,16 @@
/* Generic ops. */
-int gen_new_label(void);
-
-static inline void gen_set_label(int n)
+static inline void gen_set_label(TCGLabel *l)
{
- tcg_gen_op1(&tcg_ctx, INDEX_op_set_label, n);
+ tcg_gen_op1(&tcg_ctx, INDEX_op_set_label, label_arg(l));
}
-static inline void tcg_gen_br(int label)
+static inline void tcg_gen_br(TCGLabel *l)
{
- tcg_gen_op1(&tcg_ctx, INDEX_op_br, label);
+ tcg_gen_op1(&tcg_ctx, INDEX_op_br, label_arg(l));
}
-
/* Helper calls. */
/* 32 bit ops */
@@ -293,8 +290,8 @@
void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2);
void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2,
unsigned int ofs, unsigned int len);
-void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, int label);
-void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, int label);
+void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, TCGLabel *);
+void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLabel *);
void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret,
TCGv_i32 arg1, TCGv_i32 arg2);
void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret,
@@ -469,8 +466,8 @@
void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2);
void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2,
unsigned int ofs, unsigned int len);
-void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, int label);
-void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, int label);
+void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, TCGLabel *);
+void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, TCGLabel *);
void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret,
TCGv_i64 arg1, TCGv_i64 arg2);
void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret,
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 3841e99..751545e 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -246,7 +246,7 @@
l->u.value_ptr = ptr;
}
-int gen_new_label(void)
+TCGLabel *gen_new_label(void)
{
TCGContext *s = &tcg_ctx;
int idx;
@@ -258,7 +258,8 @@
l = &s->labels[idx];
l->has_value = 0;
l->u.first_reloc = NULL;
- return idx;
+
+ return l;
}
#include "tcg-target.c"
diff --git a/tcg/tcg.h b/tcg/tcg.h
index f941965..1987d24 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -755,6 +755,36 @@
TCGv_i32 tcg_const_local_i32(int32_t val);
TCGv_i64 tcg_const_local_i64(int64_t val);
+TCGLabel *gen_new_label(void);
+
+/**
+ * label_arg
+ * @l: label
+ *
+ * Encode a label for storage in the TCG opcode stream.
+ */
+
+static inline TCGArg label_arg(TCGLabel *l)
+{
+ ptrdiff_t idx = l - tcg_ctx.labels;
+ tcg_debug_assert(idx >= 0 && idx < tcg_ctx.nb_labels);
+ return idx;
+}
+
+/**
+ * arg_label
+ * @i: value
+ *
+ * The opposite of label_arg. Retrieve a label from the
+ * encoding of the TCG opcode stream.
+ */
+
+static inline TCGLabel *arg_label(TCGArg idx)
+{
+ tcg_debug_assert(idx < tcg_ctx.nb_labels);
+ return &tcg_ctx.labels[idx];
+}
+
/**
* tcg_ptr_byte_diff
* @a, @b: addresses to be differenced
