commit 42532189dfba7a5675225b7b3d6da3d80f8c2447
author ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> Tue Sep 25 16:53:15 2007 +0000
committer ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> Tue Sep 25 16:53:15 2007 +0000
tree 3d1e8f329f076ccb5717e0962370cf9d22fef118
parent b51eaa8218f4bd9cfd9a10b7014676035289ef56

Timer start/stop implementation, by Aurelien Jarno.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3237 c046a42c-6fe2-441c-8c8c-71466251a162

target-mips/op.c

diff --git a/target-mips/op.c b/target-mips/op.c
index b353644..b8c5ce8 100644
--- a/target-mips/op.c
+++ b/target-mips/op.c
@@ -1886,9 +1886,8 @@
 
 void op_mtc0_intctl (void)
 {
-    /* vectored interrupts not implemented, timer on int 7,
-       no performance counters. */
-    env->CP0_IntCtl |= T0 & 0x000002e0;
+    /* vectored interrupts not implemented, no performance counters. */
+    env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000002e0) | (T0 & 0x000002e0);
     RETURN();
 }
 
@@ -1908,12 +1907,20 @@
 void op_mtc0_cause (void)
 {
     uint32_t mask = 0x00C00300;
+    uint32_t old = env->CP0_Cause;
 
     if (env->insn_flags & ISA_MIPS32R2)
         mask |= 1 << CP0Ca_DC;
 
     env->CP0_Cause = (env->CP0_Cause & ~mask) | (T0 & mask);
 
+    if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
+        if (env->CP0_Cause & (1 << CP0Ca_DC))
+            CALL_FROM_TB1(cpu_mips_stop_count, env);
+        else
+            CALL_FROM_TB1(cpu_mips_start_count, env);
+    }
+
     /* Handle the software interrupt as an hardware one, as they
        are very similar */
     if (T0 & CP0Ca_IP_mask) {