commit 411eefd56a3921ddbfdbadca596e1a8593ce834c
author Max Chou <max.chou@sifive.com> Tue Apr 08 18:39:35 2025 +0800
committer Alistair Francis <alistair.francis@wdc.com> Mon May 19 13:39:06 2025 +1000
tree ebcace0d1cae8bce096345a036f17496a2848afe
parent b5480a693e3e657108746721ffe434b3bb6e7a72

target/riscv: rvv: Apply vext_check_input_eew to vector integer extension instructions(OPMVV)

Handle the overlap of source registers with different EEWs.

Co-authored-by: Anton Blanchard <antonb@tenstorrent.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Max Chou <max.chou@sifive.com>
Message-ID: <20250408103938.3623486-8-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Cc: qemu-stable@nongnu.org

target/riscv/insn_trans/trans_rvv.c.inc

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 8416927..954f032 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -3943,7 +3943,9 @@
         require_align(a->rd, s->lmul) &&
         require_align(a->rs2, s->lmul - div) &&
         require_vm(a->vm, a->rd) &&
-        require_noover(a->rd, s->lmul, a->rs2, s->lmul - div);
+        require_noover(a->rd, s->lmul, a->rs2, s->lmul - div) &&
+        vext_check_input_eew(s, -1, 0, a->rs2, s->sew, a->vm);
+
     return ret;
 }