commit 3d7b417e13152587df587fe58789740c3ef7abb9
author aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> Tue Oct 21 11:28:46 2008 +0000
committer aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> Tue Oct 21 11:28:46 2008 +0000
tree 824bf571e3bad076986e5144f6834ffd032d77f1
parent d75a0b97e0e9bfcd73dd2ef081ba06e53932b42d

target-ppc: Convert XER accesses to TCG

Define XER bits as a single register and access them individually to
avoid defining 5 32-bit registers (TCG doesn't permit to map 8-bit
registers).

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5500 c046a42c-6fe2-441c-8c8c-71466251a162

gdbstub.c

diff --git a/gdbstub.c b/gdbstub.c
index ed3f5c6..b1e3500 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -445,7 +445,7 @@
             }
         case 67: GET_REGL(env->lr);
         case 68: GET_REGL(env->ctr);
-        case 69: GET_REG32(ppc_load_xer(env));
+        case 69: GET_REGL(env->xer);
         case 70: GET_REG32(0); /* fpscr */
         }
     }
@@ -485,8 +485,8 @@
             env->ctr = ldtul_p(mem_buf);
             return sizeof(target_ulong);
         case 69:
-            ppc_store_xer(env, ldl_p(mem_buf));
-            return 4;
+            env->xer = ldtul_p(mem_buf);
+            return sizeof(target_ulong);
         case 70:
             /* fpscr */
             return 4;