target/riscv: Declare RISCVCPUClass::misa_mxl_max as RISCVMXL
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250210133134.90879-5-philmd@linaro.org>
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6da3917..d4f0196 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -3056,7 +3056,7 @@
{
RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
- mcc->misa_mxl_max = (uint32_t)(uintptr_t)data;
+ mcc->misa_mxl_max = (RISCVMXL)(uintptr_t)data;
riscv_cpu_validate_misa_mxl(mcc);
}
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 616c3bd..7de19b4 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -539,7 +539,7 @@
DeviceRealize parent_realize;
ResettablePhases parent_phases;
- uint32_t misa_mxl_max; /* max mxl for this cpu */
+ RISCVMXL misa_mxl_max; /* max mxl for this cpu */
};
static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
