include/exec: Change cpu_mmu_index argument to CPUState
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 3facfcb..047cd2c 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -1601,7 +1601,7 @@
void *p;
(void)probe_access_internal(env_cpu(env), addr, 1, MMU_INST_FETCH,
- cpu_mmu_index(env, true), false,
+ cpu_mmu_index(env_cpu(env), true), false,
&p, &full, 0, false);
if (p == NULL) {
return -1;
@@ -2959,26 +2959,30 @@
uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr)
{
- MemOpIdx oi = make_memop_idx(MO_UB, cpu_mmu_index(env, true));
- return do_ld1_mmu(env_cpu(env), addr, oi, 0, MMU_INST_FETCH);
+ CPUState *cs = env_cpu(env);
+ MemOpIdx oi = make_memop_idx(MO_UB, cpu_mmu_index(cs, true));
+ return do_ld1_mmu(cs, addr, oi, 0, MMU_INST_FETCH);
}
uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr addr)
{
- MemOpIdx oi = make_memop_idx(MO_TEUW, cpu_mmu_index(env, true));
- return do_ld2_mmu(env_cpu(env), addr, oi, 0, MMU_INST_FETCH);
+ CPUState *cs = env_cpu(env);
+ MemOpIdx oi = make_memop_idx(MO_TEUW, cpu_mmu_index(cs, true));
+ return do_ld2_mmu(cs, addr, oi, 0, MMU_INST_FETCH);
}
uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr addr)
{
- MemOpIdx oi = make_memop_idx(MO_TEUL, cpu_mmu_index(env, true));
- return do_ld4_mmu(env_cpu(env), addr, oi, 0, MMU_INST_FETCH);
+ CPUState *cs = env_cpu(env);
+ MemOpIdx oi = make_memop_idx(MO_TEUL, cpu_mmu_index(cs, true));
+ return do_ld4_mmu(cs, addr, oi, 0, MMU_INST_FETCH);
}
uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr addr)
{
- MemOpIdx oi = make_memop_idx(MO_TEUQ, cpu_mmu_index(env, true));
- return do_ld8_mmu(env_cpu(env), addr, oi, 0, MMU_INST_FETCH);
+ CPUState *cs = env_cpu(env);
+ MemOpIdx oi = make_memop_idx(MO_TEUQ, cpu_mmu_index(cs, true));
+ return do_ld8_mmu(cs, addr, oi, 0, MMU_INST_FETCH);
}
uint8_t cpu_ldb_code_mmu(CPUArchState *env, abi_ptr addr,
diff --git a/accel/tcg/ldst_common.c.inc b/accel/tcg/ldst_common.c.inc
index 4483351..c82048e 100644
--- a/accel/tcg/ldst_common.c.inc
+++ b/accel/tcg/ldst_common.c.inc
@@ -354,7 +354,8 @@
uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
{
- return cpu_ldub_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra);
+ int mmu_index = cpu_mmu_index(env_cpu(env), false);
+ return cpu_ldub_mmuidx_ra(env, addr, mmu_index, ra);
}
int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
@@ -364,7 +365,8 @@
uint32_t cpu_lduw_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
{
- return cpu_lduw_be_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra);
+ int mmu_index = cpu_mmu_index(env_cpu(env), false);
+ return cpu_lduw_be_mmuidx_ra(env, addr, mmu_index, ra);
}
int cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
@@ -374,17 +376,20 @@
uint32_t cpu_ldl_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
{
- return cpu_ldl_be_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra);
+ int mmu_index = cpu_mmu_index(env_cpu(env), false);
+ return cpu_ldl_be_mmuidx_ra(env, addr, mmu_index, ra);
}
uint64_t cpu_ldq_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
{
- return cpu_ldq_be_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra);
+ int mmu_index = cpu_mmu_index(env_cpu(env), false);
+ return cpu_ldq_be_mmuidx_ra(env, addr, mmu_index, ra);
}
uint32_t cpu_lduw_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
{
- return cpu_lduw_le_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra);
+ int mmu_index = cpu_mmu_index(env_cpu(env), false);
+ return cpu_lduw_le_mmuidx_ra(env, addr, mmu_index, ra);
}
int cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
@@ -394,54 +399,63 @@
uint32_t cpu_ldl_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
{
- return cpu_ldl_le_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra);
+ int mmu_index = cpu_mmu_index(env_cpu(env), false);
+ return cpu_ldl_le_mmuidx_ra(env, addr, mmu_index, ra);
}
uint64_t cpu_ldq_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
{
- return cpu_ldq_le_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra);
+ int mmu_index = cpu_mmu_index(env_cpu(env), false);
+ return cpu_ldq_le_mmuidx_ra(env, addr, mmu_index, ra);
}
void cpu_stb_data_ra(CPUArchState *env, abi_ptr addr,
uint32_t val, uintptr_t ra)
{
- cpu_stb_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra);
+ int mmu_index = cpu_mmu_index(env_cpu(env), false);
+ cpu_stb_mmuidx_ra(env, addr, val, mmu_index, ra);
}
void cpu_stw_be_data_ra(CPUArchState *env, abi_ptr addr,
uint32_t val, uintptr_t ra)
{
- cpu_stw_be_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra);
+ int mmu_index = cpu_mmu_index(env_cpu(env), false);
+ cpu_stw_be_mmuidx_ra(env, addr, val, mmu_index, ra);
}
void cpu_stl_be_data_ra(CPUArchState *env, abi_ptr addr,
uint32_t val, uintptr_t ra)
{
- cpu_stl_be_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra);
+ int mmu_index = cpu_mmu_index(env_cpu(env), false);
+ cpu_stl_be_mmuidx_ra(env, addr, val, mmu_index, ra);
}
void cpu_stq_be_data_ra(CPUArchState *env, abi_ptr addr,
uint64_t val, uintptr_t ra)
{
- cpu_stq_be_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra);
+ int mmu_index = cpu_mmu_index(env_cpu(env), false);
+ cpu_stq_be_mmuidx_ra(env, addr, val, mmu_index, ra);
}
void cpu_stw_le_data_ra(CPUArchState *env, abi_ptr addr,
uint32_t val, uintptr_t ra)
{
- cpu_stw_le_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra);
+ int mmu_index = cpu_mmu_index(env_cpu(env), false);
+ cpu_stw_le_mmuidx_ra(env, addr, val, mmu_index, ra);
}
void cpu_stl_le_data_ra(CPUArchState *env, abi_ptr addr,
uint32_t val, uintptr_t ra)
{
- cpu_stl_le_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra);
+ int mmu_index = cpu_mmu_index(env_cpu(env), false);
+ cpu_stl_le_mmuidx_ra(env, addr, val, mmu_index, ra);
}
void cpu_stq_le_data_ra(CPUArchState *env, abi_ptr addr,
uint64_t val, uintptr_t ra)
{
- cpu_stq_le_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra);
+ int mmu_index = cpu_mmu_index(env_cpu(env), false);
+ cpu_stq_le_mmuidx_ra(env, addr, val, mmu_index, ra);
}
/*--------------------------*/
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index 80c0d06..bc05dce 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -311,7 +311,7 @@
#define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 2))
#define TLB_WATCHPOINT 0
-static inline int cpu_mmu_index(CPUArchState *env, bool ifetch)
+static inline int cpu_mmu_index(CPUState *cs, bool ifetch)
{
return MMU_USER_IDX;
}
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index cdfbe99..9ead1be 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -275,9 +275,8 @@
* The user-only version of this function is inline in cpu-all.h,
* where it always returns MMU_USER_IDX.
*/
-static inline int cpu_mmu_index(CPUArchState *env, bool ifetch)
+static inline int cpu_mmu_index(CPUState *cs, bool ifetch)
{
- CPUState *cs = env_cpu(env);
int ret = cs->cc->mmu_index(cs, ifetch);
tcg_debug_assert(ret >= 0 && ret < NB_MMU_MODES);
return ret;
diff --git a/semihosting/uaccess.c b/semihosting/uaccess.c
index 5d889f9..dc587d7 100644
--- a/semihosting/uaccess.c
+++ b/semihosting/uaccess.c
@@ -26,7 +26,7 @@
ssize_t uaccess_strlen_user(CPUArchState *env, target_ulong addr)
{
- int mmu_idx = cpu_mmu_index(env, false);
+ int mmu_idx = cpu_mmu_index(env_cpu(env), false);
size_t len = 0;
while (1) {
diff --git a/target/cris/translate.c b/target/cris/translate.c
index 7acea29..8f74b6c 100644
--- a/target/cris/translate.c
+++ b/target/cris/translate.c
@@ -2966,7 +2966,7 @@
dc->cpu = env_archcpu(env);
dc->ppc = pc_start;
dc->pc = pc_start;
- dc->mem_index = cpu_mmu_index(env, false);
+ dc->mem_index = cpu_mmu_index(cs, false);
dc->flags_uptodate = 1;
dc->flags_x = tb_flags & X_FLAG;
dc->cc_x_uptodate = 0;
diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c
index 4fcc612..629a9d9 100644
--- a/target/hppa/mem_helper.c
+++ b/target/hppa/mem_helper.c
@@ -646,7 +646,7 @@
void HELPER(diag_btlb)(CPUHPPAState *env)
{
unsigned int phys_page, len, slot;
- int mmu_idx = cpu_mmu_index(env, 0);
+ int mmu_idx = cpu_mmu_index(env_cpu(env), 0);
uintptr_t ra = GETPC();
HPPATLBEntry *btlb;
uint64_t virt_page;
diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c
index ce15469..b1f24a5 100644
--- a/target/hppa/op_helper.c
+++ b/target/hppa/op_helper.c
@@ -59,7 +59,7 @@
static void atomic_store_mask32(CPUHPPAState *env, target_ulong addr,
uint32_t val, uint32_t mask, uintptr_t ra)
{
- int mmu_idx = cpu_mmu_index(env, 0);
+ int mmu_idx = cpu_mmu_index(env_cpu(env), 0);
uint32_t old, new, cmp, *haddr;
void *vaddr;
@@ -86,7 +86,7 @@
int size, uintptr_t ra)
{
#ifdef CONFIG_ATOMIC64
- int mmu_idx = cpu_mmu_index(env, 0);
+ int mmu_idx = cpu_mmu_index(env_cpu(env), 0);
uint64_t old, new, cmp, *haddr;
void *vaddr;
@@ -235,7 +235,7 @@
default:
/* Nothing is stored, but protection is checked and the
cacheline is marked dirty. */
- probe_write(env, addr, 0, cpu_mmu_index(env, 0), ra);
+ probe_write(env, addr, 0, cpu_mmu_index(env_cpu(env), 0), ra);
break;
}
}
@@ -296,7 +296,7 @@
default:
/* Nothing is stored, but protection is checked and the
cacheline is marked dirty. */
- probe_write(env, addr, 0, cpu_mmu_index(env, 0), ra);
+ probe_write(env, addr, 0, cpu_mmu_index(env_cpu(env), 0), ra);
break;
}
}
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 2808903..10cba16 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -6955,7 +6955,7 @@
dc->cc_op_dirty = false;
dc->popl_esp_hack = 0;
/* select memory access functions */
- dc->mem_index = cpu_mmu_index(env, false);
+ dc->mem_index = cpu_mmu_index(cpu, false);
dc->cpuid_features = env->features[FEAT_1_EDX];
dc->cpuid_ext_features = env->features[FEAT_1_ECX];
dc->cpuid_ext2_features = env->features[FEAT_8000_0001_EDX];
diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c
index b065877..45f821d 100644
--- a/target/loongarch/cpu_helper.c
+++ b/target/loongarch/cpu_helper.c
@@ -224,7 +224,7 @@
int prot;
if (get_physical_address(env, &phys_addr, &prot, addr, MMU_DATA_LOAD,
- cpu_mmu_index(env, false)) != 0) {
+ cpu_mmu_index(cs, false)) != 0) {
return -1;
}
return phys_addr;
diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
index 804ab7a..a08c08b 100644
--- a/target/loongarch/tcg/tlb_helper.c
+++ b/target/loongarch/tcg/tlb_helper.c
@@ -90,7 +90,7 @@
uint8_t tlb_ps;
LoongArchTLB *tlb = &env->tlb[index];
- int mmu_idx = cpu_mmu_index(env, false);
+ int mmu_idx = cpu_mmu_index(env_cpu(env), false);
uint8_t tlb_v0 = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, V);
uint8_t tlb_v1 = FIELD_EX64(tlb->tlb_entry1, TLBENTRY, V);
uint64_t tlb_vppn = FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN);
diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c
index 1ce850b..47b4173 100644
--- a/target/m68k/op_helper.c
+++ b/target/m68k/op_helper.c
@@ -811,7 +811,7 @@
uint32_t l1, l2;
uintptr_t ra = GETPC();
#if defined(CONFIG_ATOMIC64)
- int mmu_idx = cpu_mmu_index(env, 0);
+ int mmu_idx = cpu_mmu_index(env_cpu(env), 0);
MemOpIdx oi = make_memop_idx(MO_BEUQ, mmu_idx);
#endif
diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c
index 98bdb82..460eee0 100644
--- a/target/microblaze/helper.c
+++ b/target/microblaze/helper.c
@@ -228,10 +228,9 @@
MemTxAttrs *attrs)
{
MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
- CPUMBState *env = &cpu->env;
target_ulong vaddr, paddr = 0;
MicroBlazeMMULookup lu;
- int mmu_idx = cpu_mmu_index(env, false);
+ int mmu_idx = cpu_mmu_index(cs, false);
unsigned int hit;
/* Caller doesn't initialize */
diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c
index 7565197..2340066 100644
--- a/target/microblaze/mmu.c
+++ b/target/microblaze/mmu.c
@@ -305,7 +305,7 @@
}
hit = mmu_translate(cpu, &lu, v & TLB_EPN_MASK,
- 0, cpu_mmu_index(env, false));
+ 0, cpu_mmu_index(env_cpu(env), false));
if (hit) {
env->mmu.regs[MMU_R_TLBX] = lu.idx;
} else {
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 2e62864..a465c2d 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -1607,7 +1607,7 @@
dc->ext_imm = dc->base.tb->cs_base;
dc->r0 = NULL;
dc->r0_set = false;
- dc->mem_index = cpu_mmu_index(&cpu->env, false);
+ dc->mem_index = cpu_mmu_index(cs, false);
dc->jmp_cond = dc->tb_flags & D_FLAG ? TCG_COND_ALWAYS : TCG_COND_NEVER;
dc->jmp_dest = -1;
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index 3078372..612556b 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -948,7 +948,7 @@
Nios2CPU *cpu = env_archcpu(env);
int page_insns;
- dc->mem_idx = cpu_mmu_index(env, false);
+ dc->mem_idx = cpu_mmu_index(cs, false);
dc->cr_state = cpu->cr_state;
dc->tb_flags = dc->base.tb->flags;
dc->eic_present = cpu->eic_present;
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index d4cbc5e..785bcb6 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -1528,7 +1528,7 @@
CPUOpenRISCState *env = cpu_env(cs);
int bound;
- dc->mem_idx = cpu_mmu_index(env, false);
+ dc->mem_idx = cpu_mmu_index(cs, false);
dc->tb_flags = dc->base.tb->flags;
dc->delayed_branch = (dc->tb_flags & TB_FLAGS_DFLAG) != 0;
dc->cpucfgr = env->cpucfgr;
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 5185615..1e076f6 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -755,7 +755,7 @@
uint32_t flags;
*pc = env->pc;
*cs_base = env->npc;
- flags = cpu_mmu_index(env, false);
+ flags = cpu_mmu_index(env_cpu(env), false);
#ifndef CONFIG_USER_ONLY
if (cpu_supervisor_mode(env)) {
flags |= TB_FLAG_SUPER;
diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c
index 09066d5..52aa6c6 100644
--- a/target/sparc/ldst_helper.c
+++ b/target/sparc/ldst_helper.c
@@ -690,7 +690,7 @@
case ASI_M_IODIAG: /* Turbosparc IOTLB Diagnostic */
break;
case ASI_KERNELTXT: /* Supervisor code access */
- oi = make_memop_idx(memop, cpu_mmu_index(env, true));
+ oi = make_memop_idx(memop, cpu_mmu_index(env_cpu(env), true));
switch (size) {
case 1:
ret = cpu_ldb_code_mmu(env, addr, oi, GETPC());
diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c
index 453498c..5170a66 100644
--- a/target/sparc/mmu_helper.c
+++ b/target/sparc/mmu_helper.c
@@ -901,7 +901,7 @@
SPARCCPU *cpu = SPARC_CPU(cs);
CPUSPARCState *env = &cpu->env;
hwaddr phys_addr;
- int mmu_idx = cpu_mmu_index(env, false);
+ int mmu_idx = cpu_mmu_index(cs, false);
if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 2, mmu_idx) != 0) {
if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 0, mmu_idx) != 0) {
diff --git a/target/tricore/helper.c b/target/tricore/helper.c
index 174f666..649373a 100644
--- a/target/tricore/helper.c
+++ b/target/tricore/helper.c
@@ -48,7 +48,7 @@
TriCoreCPU *cpu = TRICORE_CPU(cs);
hwaddr phys_addr;
int prot;
- int mmu_idx = cpu_mmu_index(&cpu->env, false);
+ int mmu_idx = cpu_mmu_index(cs, false);
if (get_physical_address(&cpu->env, &phys_addr, &prot, addr,
MMU_DATA_LOAD, mmu_idx)) {
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index f1156c3..278c514 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -8355,7 +8355,7 @@
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
CPUTriCoreState *env = cpu_env(cs);
- ctx->mem_idx = cpu_mmu_index(env, false);
+ ctx->mem_idx = cpu_mmu_index(cs, false);
uint32_t tb_flags = (uint32_t)ctx->base.tb->flags;
ctx->priv = FIELD_EX32(tb_flags, TB_FLAGS, PRIV);
diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c
index 2fda4e8..47063b0 100644
--- a/target/xtensa/mmu_helper.c
+++ b/target/xtensa/mmu_helper.c
@@ -66,7 +66,7 @@
* only the side-effects (ie any MMU or other exception)
*/
probe_access(env, vaddr, 1, MMU_INST_FETCH,
- cpu_mmu_index(env, true), GETPC());
+ cpu_mmu_index(env_cpu(env), true), GETPC());
}
void HELPER(wsr_rasid)(CPUXtensaState *env, uint32_t v)
