tree e45b953a40a49d6ddea723481bd7acef9a66d2d6
parent 051b9980b99dbfba22ea5f79bd3708d513ae121d
author Peter Maydell <peter.maydell@linaro.org> 1398954284 +0100
committer Peter Maydell <peter.maydell@linaro.org> 1398954284 +0100

target-arm: Implement XScale cache lockdown operations as NOPs

XScale defines some implementation-specific coprocessor registers
for doing cache lockdown operations. Since QEMU doesn't model a
cache no proper implementation is possible, but NOP out the
registers so that guest code like u-boot that tries to use them
doesn't crash.

Reported-by: <prqek@centrum.cz>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>