qapi/machine-common.json

# -*- Mode: Python -*-
# vim: filetype=python
#
# This work is licensed under the terms of the GNU GPL, version 2 or later.
# See the COPYING file in the top-level directory.

##
# = Common machine types
##

##
# @S390CpuEntitlement:
#
# An enumeration of CPU entitlements that can be assumed by a virtual
# S390 CPU
#
# Since: 8.2
##
{ 'enum': 'S390CpuEntitlement',
  'data': [ 'auto', 'low', 'medium', 'high' ] }

##
# @CpuTopologyLevel:
#
# An enumeration of CPU topology levels.
#
# @thread: thread level, which would also be called SMT level or
#     logical processor level.  The @threads option in
#     SMPConfiguration is used to configure the topology of this
#     level.
#
# @core: core level.  The @cores option in SMPConfiguration is used
#     to configure the topology of this level.
#
# @module: module level.  The @modules option in SMPConfiguration is
#     used to configure the topology of this level.
#
# @cluster: cluster level.  The @clusters option in SMPConfiguration
#     is used to configure the topology of this level.
#
# @die: die level.  The @dies option in SMPConfiguration is used to
#     configure the topology of this level.
#
# @socket: socket level, which would also be called package level.
#     The @sockets option in SMPConfiguration is used to configure
#     the topology of this level.
#
# @book: book level.  The @books option in SMPConfiguration is used
#     to configure the topology of this level.
#
# @drawer: drawer level.  The @drawers option in SMPConfiguration is
#     used to configure the topology of this level.
#
# @default: default level.  Some architectures will have default
#     topology settings (e.g., cache topology), and this special
#     level means following the architecture-specific settings.
#
# Since: 9.2
##
{ 'enum': 'CpuTopologyLevel',
  'data': [ 'thread', 'core', 'module', 'cluster', 'die',
            'socket', 'book', 'drawer', 'default' ] }

##
# @CacheLevelAndType:
#
# Caches a system may have.  The enumeration value here is the
# combination of cache level and cache type.
#
# @l1d: L1 data cache.
#
# @l1i: L1 instruction cache.
#
# @l2: L2 (unified) cache.
#
# @l3: L3 (unified) cache
#
# Since: 9.2
##
{ 'enum': 'CacheLevelAndType',
  'data': [ 'l1d', 'l1i', 'l2', 'l3' ] }

##
# @SmpCacheProperties:
#
# Cache information for SMP system.
#
# @cache: Cache name, which is the combination of cache level
#     and cache type.
#
# @topology: Cache topology level.  It accepts the CPU topology
#     enumeration as the parameter, i.e., CPUs in the same
#     topology container share the same cache.
#
# Since: 9.2
##
{ 'struct': 'SmpCacheProperties',
  'data': {
  'cache': 'CacheLevelAndType',
  'topology': 'CpuTopologyLevel' } }

##
# @SmpCachePropertiesWrapper:
#
# List wrapper of SmpCacheProperties.
#
# @caches: the list of SmpCacheProperties.
#
# Since 9.2
##
{ 'struct': 'SmpCachePropertiesWrapper',
  'data': { 'caches': ['SmpCacheProperties'] } }