commit | 3a4e56015b897a5502ab6a691cd4e20700e779c1 | [log] [tgz] |
---|---|---|
author | Michael Tokarev <mjt@tls.msk.ru> | Tue Nov 14 19:11:33 2023 +0300 |
committer | Michael Tokarev <mjt@tls.msk.ru> | Wed Nov 15 12:06:05 2023 +0300 |
tree | 92657ea61d7ff7c06eb8132b7dd2eb71618ed6c6 | |
parent | 801faee4dd15ee395fe1c2fb35241c3c7a0b9af5 [diff] |
target/riscv/cpu.h: spelling fix: separatly Fixes: 40336d5b1d4c "target/riscv: Add HS-mode virtual interrupt and IRQ filtering support." Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>