tree 9ba62390cd163c7be8fae917cedeabeadf3d0160
parent ff832b77aa8ab454e092fb73b61821e56218e8a5
author Alistair Francis <alistair.francis@wdc.com> 1587664209 -0700
committer Alistair Francis <alistair.francis@wdc.com> 1591200711 -0700

target/riscv: Add the lowRISC Ibex CPU

Ibex is a small and efficient, 32-bit, in-order RISC-V core with
a 2-stage pipeline that implements the RV32IMC instruction set
architecture.

For more details on lowRISC see here:
https://github.com/lowRISC/ibex

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>