Add concat_i32_i64 op.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5280 c046a42c-6fe2-441c-8c8c-71466251a162
diff --git a/target-mips/translate.c b/target-mips/translate.c
index b553b5f..3ac0f60 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -693,13 +693,7 @@
     if (ctx->hflags & MIPS_HFLAG_F64)
         tcg_gen_mov_i64(t, fpu_fpr64[reg]);
     else {
-        TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64);
-
-        tcg_gen_extu_i32_i64(t, fpu_fpr32[reg | 1]);
-        tcg_gen_shli_i64(t, t, 32);
-        tcg_gen_extu_i32_i64(r_tmp2, fpu_fpr32[reg & ~1]);
-        tcg_gen_or_i64(t, t, r_tmp2);
-        tcg_temp_free(r_tmp2);
+        tcg_gen_concat_i32_i64(t, fpu_fpr32[reg & ~1], fpu_fpr32[reg | 1]);
     }
 }
 
@@ -6546,22 +6540,17 @@
     case FOP(38, 16):
         check_cp1_64bitmode(ctx);
         {
-            TCGv fp64_0 = tcg_temp_new(TCG_TYPE_I64);
-            TCGv fp64_1 = tcg_temp_new(TCG_TYPE_I64);
+            TCGv fp64 = tcg_temp_new(TCG_TYPE_I64);
             TCGv fp32_0 = tcg_temp_new(TCG_TYPE_I32);
             TCGv fp32_1 = tcg_temp_new(TCG_TYPE_I32);
 
             gen_load_fpr32(fp32_0, fs);
             gen_load_fpr32(fp32_1, ft);
-            tcg_gen_extu_i32_i64(fp64_0, fp32_0);
-            tcg_gen_extu_i32_i64(fp64_1, fp32_1);
-            tcg_temp_free(fp32_0);
+            tcg_gen_concat_i32_i64(fp64, fp32_0, fp32_1);
             tcg_temp_free(fp32_1);
-            tcg_gen_shli_i64(fp64_1, fp64_1, 32);
-            tcg_gen_or_i64(fp64_0, fp64_0, fp64_1);
-            tcg_temp_free(fp64_1);
-            gen_store_fpr64(ctx, fp64_0, fd);
-            tcg_temp_free(fp64_0);
+            tcg_temp_free(fp32_0);
+            gen_store_fpr64(ctx, fp64, fd);
+            tcg_temp_free(fp64);
         }
         opn = "cvt.ps.s";
         break;