tree eca8fdc9bd67c063dcef30e47385d587e30b3070
parent a3500b22a18ec4195793037c0f45a47bd5a59e51
parent 74b493244d0624afed22606e76fc7fca62777401
author Peter Maydell <peter.maydell@linaro.org> 1727883006 +0100
committer Peter Maydell <peter.maydell@linaro.org> 1727883006 +0100
mergetag object 74b493244d0624afed22606e76fc7fca62777401
 type commit
 tag pull-riscv-to-apply-20241002
 tagger Alistair Francis <alistair.francis@wdc.com> 1727848000 +1000
 
 RISC-V PR for 9.2
 
 * Add a property to set vl to ceil(AVL/2)
 * Enable numamem testing for RISC-V
 * Consider MISA bit choice in implied rule
 * Fix the za64rs priv spec requirements
 * Enable Bit Manip for OpenTitan Ibex CPU
 * Fix the group bit setting of AIA with KVM
 * Stop timer with infinite timecmp
 * Add 'fcsr' register to QEMU log as a part of F extension
 * Fix riscv64 build on musl libc
 * Add preliminary textra trigger CSR functions
 * RISC-V bsd-user support
 * Respect firmware ELF entry point
 * Add Svvptc extension support
 * Fix masking of rv32 physical address
 * Fix linking problem with semihosting disabled
 * Fix IMSIC interrupt state updates
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Merge tag 'pull-riscv-to-apply-20241002' of https://github.com/alistair23/qemu into staging

RISC-V PR for 9.2

* Add a property to set vl to ceil(AVL/2)
* Enable numamem testing for RISC-V
* Consider MISA bit choice in implied rule
* Fix the za64rs priv spec requirements
* Enable Bit Manip for OpenTitan Ibex CPU
* Fix the group bit setting of AIA with KVM
* Stop timer with infinite timecmp
* Add 'fcsr' register to QEMU log as a part of F extension
* Fix riscv64 build on musl libc
* Add preliminary textra trigger CSR functions
* RISC-V bsd-user support
* Respect firmware ELF entry point
* Add Svvptc extension support
* Fix masking of rv32 physical address
* Fix linking problem with semihosting disabled
* Fix IMSIC interrupt state updates

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# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown]
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* tag 'pull-riscv-to-apply-20241002' of https://github.com/alistair23/qemu: (35 commits)
  bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files
  bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV
  bsd-user: Implement 'get_mcontext' for RISC-V
  bsd-user: Implement RISC-V signal trampoline setup functions
  bsd-user: Define RISC-V signal handling structures and constants
  bsd-user: Add generic RISC-V64 target definitions
  bsd-user: Define RISC-V system call structures and constants
  bsd-user: Define RISC-V VM parameters and helper functions
  bsd-user: Add RISC-V thread setup and initialization support
  bsd-user: Implement RISC-V sysarch system call emulation
  bsd-user: Add RISC-V signal trampoline setup function
  bsd-user: Define RISC-V register structures and register copying
  bsd-user: Add RISC-V ELF definitions and hardware capability detection
  bsd-user: Implement RISC-V TLS register setup
  bsd-user: Implement RISC-V CPU register cloning and reset functions
  bsd-user: Add RISC-V CPU execution loop and syscall handling
  bsd-user: Implement RISC-V CPU initialization and main loop
  hw/intc: riscv-imsic: Fix interrupt state updates.
  target/riscv/cpu_helper: Fix linking problem with semihosting disabled
  target/riscv32: Fix masking of physical address
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>