)]}'
{
  "commit": "35ba77d2fcd10efd6db8318bbd4d21fa9402143b",
  "tree": "eca8fdc9bd67c063dcef30e47385d587e30b3070",
  "parents": [
    "a3500b22a18ec4195793037c0f45a47bd5a59e51",
    "74b493244d0624afed22606e76fc7fca62777401"
  ],
  "author": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Wed Oct 02 16:30:06 2024 +0100"
  },
  "committer": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Wed Oct 02 16:30:06 2024 +0100"
  },
  "message": "Merge tag \u0027pull-riscv-to-apply-20241002\u0027 of https://github.com/alistair23/qemu into staging\n\nRISC-V PR for 9.2\n\n* Add a property to set vl to ceil(AVL/2)\n* Enable numamem testing for RISC-V\n* Consider MISA bit choice in implied rule\n* Fix the za64rs priv spec requirements\n* Enable Bit Manip for OpenTitan Ibex CPU\n* Fix the group bit setting of AIA with KVM\n* Stop timer with infinite timecmp\n* Add \u0027fcsr\u0027 register to QEMU log as a part of F extension\n* Fix riscv64 build on musl libc\n* Add preliminary textra trigger CSR functions\n* RISC-V bsd-user support\n* Respect firmware ELF entry point\n* Add Svvptc extension support\n* Fix masking of rv32 physical address\n* Fix linking problem with semihosting disabled\n* Fix IMSIC interrupt state updates\n\n# -----BEGIN PGP SIGNATURE-----\n#\n# iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmb83lYACgkQr3yVEwxT\n# gBNndBAAmh66yWt9TeTHlQ/rgBhx2nUMBbfICBWQyNGvPlslffwrNoLkh8jpkuiP\n# PD0RQArAAGeM09cgCZCu14JzIBmmNiGgUxsUnqOZvUw18uIlLFlpt/tiT7iGw/Xb\n# pfI7waF66/FPXBErY2yiw9/RGQLlkiGNBC9FNYrD/kCahf9MSIobv85tOgSQ2qjH\n# nOJ+UBN0TQ1x0Z5lJMj9Pzl1WDvelRnCkYI5nXg1heKG73Hm7GmHt99QpTV2Okqn\n# T3jFzEfMTQeHO4nC/X2pbaesE62K+mTg/FZpId2iV8lMCSm1zKof+xJ4boKM9RB2\n# 0HjXAT+MveLuLUNtgfbV9C+VgU25M+wnfy5tH0l801Y/Gez8Q1fbK2uykuiyiUSy\n# MNNk/KzmOYuffwItuyeL3mmWHXsN+izUIeMmMxfL9X9nssZXRsrDXc+MByS7w0fk\n# QOeZmXHTxXwxFymr0t0DLK2eKEG6cqQty1KWp6iLx3uwnMTGo+576P41Q+boj64s\n# VllWzmuR0Ta0xuSR4sDvEFCO7OCFEgVdn1j0FvhRFskPEDrbQgXRLq8i3awtU6z1\n# NIh+A30XeK+EZLv0sEje6gav5lZHWMfAeCOKJstVzOl8+NQibuKTUrsqLgTrBK6K\n# plw8qwvZYjSnYErzHfywlq9ArufIvOHYcx9Nb76tLNy9E+y01yo\u003d\n# \u003d15Hm\n# -----END PGP SIGNATURE-----\n# gpg: Signature made Wed 02 Oct 2024 06:47:02 BST\n# gpg:                using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013\n# gpg: Good signature from \"Alistair Francis \u003calistair@alistair23.me\u003e\" [unknown]\n# gpg: WARNING: This key is not certified with a trusted signature!\n# gpg:          There is no indication that the signature belongs to the owner.\n# Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65  9296 AF7C 9513 0C53 8013\n\n* tag \u0027pull-riscv-to-apply-20241002\u0027 of https://github.com/alistair23/qemu: (35 commits)\n  bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files\n  bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV\n  bsd-user: Implement \u0027get_mcontext\u0027 for RISC-V\n  bsd-user: Implement RISC-V signal trampoline setup functions\n  bsd-user: Define RISC-V signal handling structures and constants\n  bsd-user: Add generic RISC-V64 target definitions\n  bsd-user: Define RISC-V system call structures and constants\n  bsd-user: Define RISC-V VM parameters and helper functions\n  bsd-user: Add RISC-V thread setup and initialization support\n  bsd-user: Implement RISC-V sysarch system call emulation\n  bsd-user: Add RISC-V signal trampoline setup function\n  bsd-user: Define RISC-V register structures and register copying\n  bsd-user: Add RISC-V ELF definitions and hardware capability detection\n  bsd-user: Implement RISC-V TLS register setup\n  bsd-user: Implement RISC-V CPU register cloning and reset functions\n  bsd-user: Add RISC-V CPU execution loop and syscall handling\n  bsd-user: Implement RISC-V CPU initialization and main loop\n  hw/intc: riscv-imsic: Fix interrupt state updates.\n  target/riscv/cpu_helper: Fix linking problem with semihosting disabled\n  target/riscv32: Fix masking of physical address\n  ...\n\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\n",
  "tree_diff": []
}