Merge tag 'pull-loongarch-20240821' of https://gitlab.com/gaosong/qemu into staging
Fix for 9.1
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* tag 'pull-loongarch-20240821' of https://gitlab.com/gaosong/qemu:
hw/loongarch: Fix length for lowram in ACPI SRAT
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
diff --git a/bsd-user/mmap.c b/bsd-user/mmap.c
index f3a4f17..775e905 100644
--- a/bsd-user/mmap.c
+++ b/bsd-user/mmap.c
@@ -129,6 +129,40 @@
}
/*
+ * Perform a pread on behalf of target_mmap. We can reach EOF, we can be
+ * interrupted by signals, and in general there's no good error return path.
+ * If @zero, zero the rest of the block at EOF.
+ * Return true on success.
+ */
+static bool mmap_pread(int fd, void *p, size_t len, off_t offset, bool zero)
+{
+ while (1) {
+ ssize_t r = pread(fd, p, len, offset);
+
+ if (likely(r == len)) {
+ /* Complete */
+ return true;
+ }
+ if (r == 0) {
+ /* EOF */
+ if (zero) {
+ memset(p, 0, len);
+ }
+ return true;
+ }
+ if (r > 0) {
+ /* Short read */
+ p += r;
+ len -= r;
+ offset += r;
+ } else if (errno != EINTR) {
+ /* Error */
+ return false;
+ }
+ }
+}
+
+/*
* map an incomplete host page
*
* mmap_frag can be called with a valid fd, if flags doesn't contain one of
@@ -190,7 +224,7 @@
mprotect(host_start, qemu_host_page_size, prot1 | PROT_WRITE);
/* read the corresponding file data */
- if (pread(fd, g2h_untagged(start), end - start, offset) == -1) {
+ if (!mmap_pread(fd, g2h_untagged(start), end - start, offset, true)) {
return -1;
}
@@ -565,7 +599,7 @@
-1, 0);
if (retaddr == -1)
goto fail;
- if (pread(fd, g2h_untagged(start), len, offset) == -1) {
+ if (!mmap_pread(fd, g2h_untagged(start), len, offset, false)) {
goto fail;
}
if (!(prot & PROT_WRITE)) {
diff --git a/linux-user/mmap.c b/linux-user/mmap.c
index 6418e81..e4bf5d5 100644
--- a/linux-user/mmap.c
+++ b/linux-user/mmap.c
@@ -284,6 +284,40 @@
}
/*
+ * Perform a pread on behalf of target_mmap. We can reach EOF, we can be
+ * interrupted by signals, and in general there's no good error return path.
+ * If @zero, zero the rest of the block at EOF.
+ * Return true on success.
+ */
+static bool mmap_pread(int fd, void *p, size_t len, off_t offset, bool zero)
+{
+ while (1) {
+ ssize_t r = pread(fd, p, len, offset);
+
+ if (likely(r == len)) {
+ /* Complete */
+ return true;
+ }
+ if (r == 0) {
+ /* EOF */
+ if (zero) {
+ memset(p, 0, len);
+ }
+ return true;
+ }
+ if (r > 0) {
+ /* Short read */
+ p += r;
+ len -= r;
+ offset += r;
+ } else if (errno != EINTR) {
+ /* Error */
+ return false;
+ }
+ }
+}
+
+/*
* Map an incomplete host page.
*
* Here be dragons. This case will not work if there is an existing
@@ -357,10 +391,9 @@
/* Read or zero the new guest pages. */
if (flags & MAP_ANONYMOUS) {
memset(g2h_untagged(start), 0, last - start + 1);
- } else {
- if (pread(fd, g2h_untagged(start), last - start + 1, offset) == -1) {
- return false;
- }
+ } else if (!mmap_pread(fd, g2h_untagged(start), last - start + 1,
+ offset, true)) {
+ return false;
}
/* Put final protection */
@@ -853,8 +886,7 @@
}
if (misaligned_offset) {
- /* TODO: The read could be short. */
- if (pread(fd, p, host_len, offset + real_start - start) != host_len) {
+ if (!mmap_pread(fd, p, host_len, offset + real_start - start, false)) {
do_munmap(p, host_len);
return -1;
}
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index c6cc035..14edd57 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1339,6 +1339,11 @@
CC_OP_BMILGL,
CC_OP_BMILGQ,
+ CC_OP_BLSIB, /* Z,S via CC_DST, C = SRC!=0; O=0; P,A undefined */
+ CC_OP_BLSIW,
+ CC_OP_BLSIL,
+ CC_OP_BLSIQ,
+
/*
* Note that only CC_OP_POPCNT (i.e. the one with MO_TL size)
* is used or implemented, because the translation needs
diff --git a/target/i386/tcg/cc_helper.c b/target/i386/tcg/cc_helper.c
index 301ed95..dbddaa2 100644
--- a/target/i386/tcg/cc_helper.c
+++ b/target/i386/tcg/cc_helper.c
@@ -186,6 +186,13 @@
case CC_OP_BMILGL:
return compute_all_bmilgl(dst, src1);
+ case CC_OP_BLSIB:
+ return compute_all_blsib(dst, src1);
+ case CC_OP_BLSIW:
+ return compute_all_blsiw(dst, src1);
+ case CC_OP_BLSIL:
+ return compute_all_blsil(dst, src1);
+
case CC_OP_ADCX:
return compute_all_adcx(dst, src1, src2);
case CC_OP_ADOX:
@@ -216,6 +223,8 @@
return compute_all_sarq(dst, src1);
case CC_OP_BMILGQ:
return compute_all_bmilgq(dst, src1);
+ case CC_OP_BLSIQ:
+ return compute_all_blsiq(dst, src1);
#endif
}
}
@@ -308,6 +317,13 @@
case CC_OP_BMILGL:
return compute_c_bmilgl(dst, src1);
+ case CC_OP_BLSIB:
+ return compute_c_blsib(dst, src1);
+ case CC_OP_BLSIW:
+ return compute_c_blsiw(dst, src1);
+ case CC_OP_BLSIL:
+ return compute_c_blsil(dst, src1);
+
#ifdef TARGET_X86_64
case CC_OP_ADDQ:
return compute_c_addq(dst, src1);
@@ -321,6 +337,8 @@
return compute_c_shlq(dst, src1);
case CC_OP_BMILGQ:
return compute_c_bmilgq(dst, src1);
+ case CC_OP_BLSIQ:
+ return compute_c_blsiq(dst, src1);
#endif
}
}
diff --git a/target/i386/tcg/cc_helper_template.h.inc b/target/i386/tcg/cc_helper_template.h.inc
index bb611fe..c5425e5 100644
--- a/target/i386/tcg/cc_helper_template.h.inc
+++ b/target/i386/tcg/cc_helper_template.h.inc
@@ -235,6 +235,24 @@
return src1 == 0;
}
+static int glue(compute_all_blsi, SUFFIX)(DATA_TYPE dst, DATA_TYPE src1)
+{
+ int cf, pf, af, zf, sf, of;
+
+ cf = (src1 != 0);
+ pf = 0; /* undefined */
+ af = 0; /* undefined */
+ zf = (dst == 0) * CC_Z;
+ sf = lshift(dst, 8 - DATA_BITS) & CC_S;
+ of = 0;
+ return cf | pf | af | zf | sf | of;
+}
+
+static int glue(compute_c_blsi, SUFFIX)(DATA_TYPE dst, DATA_TYPE src1)
+{
+ return src1 != 0;
+}
+
#undef DATA_BITS
#undef SIGN_MASK
#undef DATA_TYPE
diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc
index 22a0689..9b50419 100644
--- a/target/i386/tcg/emit.c.inc
+++ b/target/i386/tcg/emit.c.inc
@@ -1304,7 +1304,7 @@
/* input in T1, which is ready for prepare_update2_cc */
tcg_gen_neg_tl(s->T0, s->T1);
tcg_gen_and_tl(s->T0, s->T0, s->T1);
- prepare_update2_cc(decode, s, CC_OP_BMILGB + ot);
+ prepare_update2_cc(decode, s, CC_OP_BLSIB + ot);
}
static void gen_BLSMSK(DisasContext *s, X86DecodedInsn *decode)
diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c
index bab552c..3b8fd82 100644
--- a/target/i386/tcg/seg_helper.c
+++ b/target/i386/tcg/seg_helper.c
@@ -378,7 +378,7 @@
/* X86Access avoids memory exceptions during the task switch */
mmu_index = cpu_mmu_index_kernel(env);
- access_prepare_mmu(&old, env, env->tr.base, old_tss_limit_max,
+ access_prepare_mmu(&old, env, env->tr.base, old_tss_limit_max + 1,
MMU_DATA_STORE, mmu_index, retaddr);
if (source == SWITCH_TSS_CALL) {
@@ -386,7 +386,8 @@
probe_access(env, tss_base, 2, MMU_DATA_STORE,
mmu_index, retaddr);
}
- access_prepare_mmu(&new, env, tss_base, tss_limit,
+ /* While true tss_limit may be larger, we don't access the iopb here. */
+ access_prepare_mmu(&new, env, tss_base, tss_limit_max + 1,
MMU_DATA_LOAD, mmu_index, retaddr);
/* save the current state in the old TSS */
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index b72864b..98f5fe6 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -304,6 +304,7 @@
[CC_OP_SHLB ... CC_OP_SHLQ] = USES_CC_DST | USES_CC_SRC,
[CC_OP_SARB ... CC_OP_SARQ] = USES_CC_DST | USES_CC_SRC,
[CC_OP_BMILGB ... CC_OP_BMILGQ] = USES_CC_DST | USES_CC_SRC,
+ [CC_OP_BLSIB ... CC_OP_BLSIQ] = USES_CC_DST | USES_CC_SRC,
[CC_OP_ADCX] = USES_CC_DST | USES_CC_SRC,
[CC_OP_ADOX] = USES_CC_SRC | USES_CC_SRC2,
[CC_OP_ADCOX] = USES_CC_DST | USES_CC_SRC | USES_CC_SRC2,
@@ -865,6 +866,18 @@
}
}
+static CCPrepare gen_prepare_val_nz(TCGv src, MemOp size, bool eqz)
+{
+ if (size == MO_TL) {
+ return (CCPrepare) { .cond = eqz ? TCG_COND_EQ : TCG_COND_NE,
+ .reg = src };
+ } else {
+ return (CCPrepare) { .cond = eqz ? TCG_COND_TSTEQ : TCG_COND_TSTNE,
+ .imm = MAKE_64BIT_MASK(0, 8 << size),
+ .reg = src };
+ }
+}
+
/* compute eflags.C, trying to store it in reg if not NULL */
static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg)
{
@@ -908,8 +921,11 @@
case CC_OP_BMILGB ... CC_OP_BMILGQ:
size = s->cc_op - CC_OP_BMILGB;
- gen_ext_tl(cpu_cc_src, cpu_cc_src, size, false);
- return (CCPrepare) { .cond = TCG_COND_EQ, .reg = cpu_cc_src };
+ return gen_prepare_val_nz(cpu_cc_src, size, true);
+
+ case CC_OP_BLSIB ... CC_OP_BLSIQ:
+ size = s->cc_op - CC_OP_BLSIB;
+ return gen_prepare_val_nz(cpu_cc_src, size, false);
case CC_OP_ADCX:
case CC_OP_ADCOX:
@@ -1006,12 +1022,7 @@
default:
{
MemOp size = (s->cc_op - CC_OP_ADDB) & 3;
- if (size == MO_TL) {
- return (CCPrepare) { .cond = TCG_COND_EQ, .reg = cpu_cc_dst };
- } else {
- return (CCPrepare) { .cond = TCG_COND_TSTEQ, .reg = cpu_cc_dst,
- .imm = (1ull << (8 << size)) - 1 };
- }
+ return gen_prepare_val_nz(cpu_cc_dst, size, true);
}
}
}
diff --git a/tests/tcg/x86_64/Makefile.target b/tests/tcg/x86_64/Makefile.target
index eda9bd7..783ab5b 100644
--- a/tests/tcg/x86_64/Makefile.target
+++ b/tests/tcg/x86_64/Makefile.target
@@ -16,6 +16,7 @@
X86_64_TESTS += cmpxchg
X86_64_TESTS += adox
X86_64_TESTS += test-1648
+X86_64_TESTS += test-2175
TESTS=$(MULTIARCH_TESTS) $(X86_64_TESTS) test-x86_64
else
TESTS=$(MULTIARCH_TESTS)
diff --git a/tests/tcg/x86_64/test-2175.c b/tests/tcg/x86_64/test-2175.c
new file mode 100644
index 0000000..aafd037
--- /dev/null
+++ b/tests/tcg/x86_64/test-2175.c
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* See https://gitlab.com/qemu-project/qemu/-/issues/2185 */
+
+#include <assert.h>
+
+int test_setc(unsigned int x, unsigned int y)
+{
+ asm("blsi %1, %0; setc %b0" : "+r"(x) : "r"(y));
+ return (unsigned char)x;
+}
+
+int test_pushf(unsigned int x, unsigned int y)
+{
+ asm("blsi %1, %0; pushf; pop %q0" : "+r"(x) : "r"(y));
+ return x & 1;
+}
+
+int main()
+{
+ assert(test_setc(1, 0xedbf530a));
+ assert(test_pushf(1, 0xedbf530a));
+ return 0;
+}
+
