commit 3335a04806d337c69f44a707cdc27515d6c91d84
author Richard Henderson <richard.henderson@linaro.org> Sat Nov 04 12:21:37 2023 -0700
committer Richard Henderson <richard.henderson@linaro.org> Wed Jun 05 09:05:10 2024 -0700
tree f9fbfc1d70e2d389023f715b7b33f2a56f0f89f7
parent 4fd71d19acd6e05b74927a0b5c4a5b0650e3d6f5

target/sparc: Add feature bits for VIS 3

The manual separates VIS 3 and VIS 3B, even though they are both
present in all extant cpus.  For clarity, let the translator
match the manual but otherwise leave them on the same feature bit.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/sparc/cpu-feature.h.inc

diff --git a/target/sparc/cpu-feature.h.inc b/target/sparc/cpu-feature.h.inc
index a30b925..3913fb4 100644
--- a/target/sparc/cpu-feature.h.inc
+++ b/target/sparc/cpu-feature.h.inc
@@ -13,3 +13,4 @@
 FEATURE(POWERDOWN)
 FEATURE(CASA)
 FEATURE(FMAF)
+FEATURE(VIS3)

target/sparc/translate.c

diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 5efd09f..59b922c 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -2188,6 +2188,8 @@
 # define avail_HYPV(C)    ((C)->def->features & CPU_FEATURE_HYPV)
 # define avail_VIS1(C)    ((C)->def->features & CPU_FEATURE_VIS1)
 # define avail_VIS2(C)    ((C)->def->features & CPU_FEATURE_VIS2)
+# define avail_VIS3(C)    ((C)->def->features & CPU_FEATURE_VIS3)
+# define avail_VIS3B(C)   avail_VIS3(C)
 #else
 # define avail_32(C)      true
 # define avail_ASR17(C)   ((C)->def->features & CPU_FEATURE_ASR17)
@@ -2201,6 +2203,8 @@
 # define avail_HYPV(C)    false
 # define avail_VIS1(C)    false
 # define avail_VIS2(C)    false
+# define avail_VIS3(C)    false
+# define avail_VIS3B(C)   false
 #endif
 
 /* Default case for non jump instructions. */