)]}'
{
  "commit": "31afe04586efeccb80cc36ffafcd0e32a3245ffb",
  "tree": "94b4399f6016f60c293f988526ab8f265b676f33",
  "parents": [
    "8cefcc3b7127f1c497aa832378fe69453fb9db2c"
  ],
  "author": {
    "name": "Tommy Wu",
    "email": "tommy.wu@sifive.com",
    "time": "Thu May 25 10:37:51 2023 +0100"
  },
  "committer": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Tue May 30 15:50:16 2023 +0100"
  },
  "message": "hw/dma/xilinx_axidma: Check DMASR.HALTED to prevent infinite loop.\n\nWhen we receive a packet from the xilinx_axienet and then try to s2mem\nthrough the xilinx_axidma, if the descriptor ring buffer is full in the\nxilinx axidma driver, we’ll assert the DMASR.HALTED in the\nfunction : stream_process_s2mem and return 0. In the end, we’ll be stuck in\nan infinite loop in axienet_eth_rx_notify.\n\nThis patch checks the DMASR.HALTED state when we try to push data\nfrom xilinx axi-enet to xilinx axi-dma. When the DMASR.HALTED is asserted,\nwe will not keep pushing the data and then prevent the infinte loop.\n\nSigned-off-by: Tommy Wu \u003ctommy.wu@sifive.com\u003e\nReviewed-by: Edgar E. Iglesias \u003cedgar@zeroasic.com\u003e\nReviewed-by: Frank Chang \u003cfrank.chang@sifive.com\u003e\nMessage-id: 20230519062137.1251741-1-tommy.wu@sifive.com\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "6030c764352a053de680c4ed60a4d96f8c92faa8",
      "old_mode": 33188,
      "old_path": "hw/dma/xilinx_axidma.c",
      "new_id": "12c90267df63907faf5b7e58ff88c23e0e14219f",
      "new_mode": 33188,
      "new_path": "hw/dma/xilinx_axidma.c"
    }
  ]
}