tree 63ba2517967608d35ba2c7c0b624e4d50fda62a3
parent f78ea7ddb0e18766ece9fdfe02061744a7afc41b
parent f88131d931219bf76bb1bbf3bd8d6ca941a91ae3
author Stefan Hajnoczi <stefanha@redhat.com> 1699976905 -0500
committer Stefan Hajnoczi <stefanha@redhat.com> 1699976906 -0500
mergetag object f88131d931219bf76bb1bbf3bd8d6ca941a91ae3
 type commit
 tag pull-pa-20231113
 tagger Richard Henderson <richard.henderson@linaro.org> 1699896230 -0800
 
 target/hppa: Mask reserved PSW bits in expand_sm_imm
 target/hppa: Fix calculation of CR_IIASQ back register
 target/hppa: Fix possible overflow in TLB size calculation
 target/hppa: Fix probe instruction
 target/hppa: Split MMU_PHYS_IDX to MMU_ABS_IDX, MMU_ABS_W_IDX
 target/hppa: Reduce TARGET_PHYS_ADDR_SPACE_BITS to 40
 hw/pci-host/astro: Translate 32-bit pci onto 40-bit runway bus
 hw/hppa: Update SeaBIOS-hppa to version 12
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Merge tag 'pull-pa-20231113' of https://gitlab.com/rth7680/qemu into staging

target/hppa: Mask reserved PSW bits in expand_sm_imm
target/hppa: Fix calculation of CR_IIASQ back register
target/hppa: Fix possible overflow in TLB size calculation
target/hppa: Fix probe instruction
target/hppa: Split MMU_PHYS_IDX to MMU_ABS_IDX, MMU_ABS_W_IDX
target/hppa: Reduce TARGET_PHYS_ADDR_SPACE_BITS to 40
hw/pci-host/astro: Translate 32-bit pci onto 40-bit runway bus
hw/hppa: Update SeaBIOS-hppa to version 12

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# gpg: Signature made Mon 13 Nov 2023 12:30:06 EST
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* tag 'pull-pa-20231113' of https://gitlab.com/rth7680/qemu:
  hw/hppa: Require at least SeaBIOS-hppa version 12
  target/hppa: Update to SeaBIOS-hppa from version 10 to 12
  hw/hppa: Move software power button address to page zero
  hw/pci-host/astro: Fix boot for C3700 machine
  target/hppa: Reduce TARGET_PHYS_ADDR_SPACE_BITS to 40
  target/hppa: Replace MMU_PHYS_IDX with MMU_ABS_IDX, MMU_ABS_W_IDX
  target/hppa: Introduce MMU_IDX_MMU_DISABLED
  target/hppa: Fix possible overflow in TLB size calculation
  target/hppa: Fix calculation of CR_IIASQ back register
  target/hppa: Use PRIV_P_TO_MMU_IDX in helper_probe
  target/hppa: Use only low 2 immediate bits for PROBEI
  target/hppa: Mask reserved PSW bits in expand_sm_imm

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>