)]}'
{
  "commit": "3072961b6edc99abfbd87caac3de29bb58a52ccf",
  "tree": "bf8e8ec9883ce97137c7a38b450aa11afeddc671",
  "parents": [
    "f88934b61ee0dc1d583f0a576ce87ed2ff9c116b",
    "5c2891601ccdaa41427187ef95bc25c828b355e4"
  ],
  "author": {
    "name": "Stefan Hajnoczi",
    "email": "stefanha@redhat.com",
    "time": "Wed May 28 15:17:25 2025 -0400"
  },
  "committer": {
    "name": "Stefan Hajnoczi",
    "email": "stefanha@redhat.com",
    "time": "Wed May 28 15:17:25 2025 -0400"
  },
  "message": "Merge tag \u0027pull-tcg-20250528\u0027 of https://gitlab.com/rth7680/qemu into staging\n\naccel/tcg: Fix atomic_mmu_lookup vs TLB_FORCE_SLOW\nlinux-user: implement pgid field of /proc/self/stat\ntarget/sh4: Use MO_ALIGN for system UNALIGN()\ntarget/microblaze: Use TARGET_LONG_BITS \u003d\u003d 32 for system mode\naccel/tcg: Add TCGCPUOps.pointer_wrap\ntarget/*: Populate TCGCPUOps.pointer_wrap\n\n# -----BEGIN PGP SIGNATURE-----\n#\n# iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmg2xZAdHHJpY2hhcmQu\n# aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/VmAgAu5PHIARUuNqneUPQ\n# 2JxqpZHGVbaXE0ACi9cslpfThFM/I4OXmK21ZWb1dHB3qasNiKU8cdImXSUVH3dj\n# DLsr/tliReerZGUoHEtFsYd+VOtqb3wcrvXxnzG/xB761uZjFCnqwy4MrXMfSXVh\n# 6w+eysWOblYHQb9rAZho4nyw6BgjYAX2vfMFxLJBcDP/fjILFB7xoXHEyqKWMmE1\n# 0enA0KUotyLOCRXVEXSsfPDYD8szXfMkII3YcGnscthm5j58oc3skVdKFGVjNkNb\n# /aFpyvoU7Vp3JpxkYEIWLQrRM75VSb1KzJwMipHgYy3GoV++BrY10T0jyEPrx0iq\n# RFzK4A\u003d\u003d\n# \u003dXQzq\n# -----END PGP SIGNATURE-----\n# gpg: Signature made Wed 28 May 2025 04:13:04 EDT\n# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F\n# gpg:                issuer \"richard.henderson@linaro.org\"\n# gpg: Good signature from \"Richard Henderson \u003crichard.henderson@linaro.org\u003e\" [full]\n# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F\n\n* tag \u0027pull-tcg-20250528\u0027 of https://gitlab.com/rth7680/qemu: (28 commits)\n  accel/tcg: Assert TCGCPUOps.pointer_wrap is set\n  target/sparc: Fill in TCGCPUOps.pointer_wrap\n  target/s390x: Fill in TCGCPUOps.pointer_wrap\n  target/riscv: Fill in TCGCPUOps.pointer_wrap\n  target/ppc: Fill in TCGCPUOps.pointer_wrap\n  target/mips: Fill in TCGCPUOps.pointer_wrap\n  target/loongarch: Fill in TCGCPUOps.pointer_wrap\n  target/i386: Fill in TCGCPUOps.pointer_wrap\n  target/arm: Fill in TCGCPUOps.pointer_wrap\n  target: Use cpu_pointer_wrap_uint32 for 32-bit targets\n  target: Use cpu_pointer_wrap_notreached for strict align targets\n  accel/tcg: Add TCGCPUOps.pointer_wrap\n  target/sh4: Use MO_ALIGN for system UNALIGN()\n  tcg: Drop TCGContext.page_{mask,bits}\n  tcg: Drop TCGContext.tlb_dyn_max_bits\n  target/microblaze: Simplify compute_ldst_addr_type{a,b}\n  target/microblaze: Drop DisasContext.r0\n  target/microblaze: Use TARGET_LONG_BITS \u003d\u003d 32 for system mode\n  target/microblaze: Fix printf format in mmu_translate\n  target/microblaze: Use TCGv_i64 for compute_ldst_addr_ea\n  ...\n\nSigned-off-by: Stefan Hajnoczi \u003cstefanha@redhat.com\u003e\n",
  "tree_diff": []
}