target/ppc: Fix THREAD_SIBLING_FOREACH for multi-socket
The THREAD_SIBLING_FOREACH macro wasn't excluding threads from other
chips. Add chip_index field to the thread state and add a check for the
new field in the macro.
Fixes: b769d4c8f4c6 ("target/ppc: Add initial flags and helpers for SMT support")
Signed-off-by: Glenn Miles <milesg@linux.ibm.com>
[npiggin: set chip_index for spapr too]
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index cbfac49..e6b0229 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -322,6 +322,8 @@
pir_spr->default_value = pir;
tir_spr->default_value = tir;
+ env->chip_index = pc->chip->chip_id;
+
if (pc->big_core) {
/* 2 "small cores" get the same core index for SMT operations */
env->core_index = core_hwid >> 1;
diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
index ada439e..135f86a 100644
--- a/hw/ppc/spapr_cpu_core.c
+++ b/hw/ppc/spapr_cpu_core.c
@@ -313,6 +313,7 @@
return NULL;
}
+ env->chip_index = sc->node_id;
env->core_index = cc->core_id;
cpu->node_id = sc->node_id;
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 0b4f101..2ffac2e 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1253,6 +1253,7 @@
/* For SMT processors */
bool has_smt_siblings;
int core_index;
+ int chip_index;
#if !defined(CONFIG_USER_ONLY)
/* MMU context, only relevant for full system emulation */
@@ -1412,8 +1413,10 @@
#define THREAD_SIBLING_FOREACH(cs, cs_sibling) \
CPU_FOREACH(cs_sibling) \
- if (POWERPC_CPU(cs)->env.core_index == \
- POWERPC_CPU(cs_sibling)->env.core_index)
+ if ((POWERPC_CPU(cs)->env.chip_index == \
+ POWERPC_CPU(cs_sibling)->env.chip_index) && \
+ (POWERPC_CPU(cs)->env.core_index == \
+ POWERPC_CPU(cs_sibling)->env.core_index))
#define SET_FIT_PERIOD(a_, b_, c_, d_) \
do { \