| commit | 2e9ff01a912997c4af066aab5e43a52db6c68aaf | [log] [tgz] |
|---|---|---|
| author | Bibo Mao <maobibo@loongson.cn> | Thu Oct 09 10:59:31 2025 +0800 |
| committer | Bibo Mao <maobibo@loongson.cn> | Wed Oct 15 10:57:49 2025 +0800 |
| tree | 32cdec7c2d9d9e01ca896ccf15f6dbed7f5c82ed | |
| parent | 3bf5c57a11827d9fa706524d57ee3e5af68a429e [diff] |
target/loongarch: Add missing TLB flush with different asid If asid is changed in function helper_csrwr_asid(), qemu TLB is flushed, however loongArch TLB is still valid. So loongArch TLB need be invalidated in function invalidate_tlb() with different asid and bit effective need be cleared. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>