Special-case iWMMXt register transfer insns, which are in ARM LDC2/STC2 class.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3107 c046a42c-6fe2-441c-8c8c-71466251a162
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 8132d0c..f1b170d 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -838,9 +838,11 @@
case 15: /* Implementation specific. */
if (arm_feature(env, ARM_FEATURE_XSCALE)) {
if (op2 == 0 && crm == 1) {
- /* Changes cp0 to cp13 behavior, so needs a TB flush. */
- tb_flush(env);
- env->cp15.c15_cpar = (val & 0x3fff) | 2;
+ if (env->cp15.c15_cpar != (val & 0x3fff)) {
+ /* Changes cp0 to cp13 behavior, so needs a TB flush. */
+ tb_flush(env);
+ env->cp15.c15_cpar = val & 0x3fff;
+ }
break;
}
goto bad_reg;
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 3ce93f8..799aef2 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -2230,6 +2230,13 @@
gen_op_movl_T0_im(val);
gen_bx(s);
return;
+ } else if ((insn & 0x0e000f00) == 0x0c000100) {
+ if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
+ /* iWMMXt register transfer. */
+ if (env->cp15.c15_cpar & (1 << 1))
+ if (!disas_iwmmxt_insn(env, s, insn))
+ return;
+ }
} else if ((insn & 0x0fe00000) == 0x0c400000) {
/* Coprocessor double register transfer. */
} else if ((insn & 0x0f000010) == 0x0e000010) {
