)]}'
{
  "commit": "2d64e6a009e1efbf6d9ae63a3dc5d35f356641e7",
  "tree": "e078d24a65f9ec1f20a000e9691d9688a029c2e8",
  "parents": [
    "541da2604fe157d9db5995808097230a9f966b4a"
  ],
  "author": {
    "name": "Steven Lee",
    "email": "steven_lee@aspeedtech.com",
    "time": "Fri May 02 18:34:42 2025 +0800"
  },
  "committer": {
    "name": "Cédric Le Goater",
    "email": "clg@redhat.com",
    "time": "Mon May 05 09:38:55 2025 +0200"
  },
  "message": "hw/arm/aspeed_ast27x0-tsp: Introduce AST27x0 A1 TSP SoC\n\nAST2700 TSP(Tertiary Service Processor) is a Cortex-M4 coprocessor\nThe patch adds support for TSP with following update:\n\n- Introduce Aspeed27x0TSPSoCState structure in aspeed_soc.h\n- Implement initialization and realization functions\n- Add support for UART, INTC, and SCU devices\n- Map unimplemented devices for IPC and SCUIO\n- Defined memory map and IRQ maps for AST27x0 A1 TSP SoC\n\nThe IRQ mapping is similar to AST2700 CA35 SoC, featuring a two-level\ninterrupt controller.\n\nDifference from AST2700:\n\n    - AST2700\n      - Support GICINT128 to GICINT136 in INTC\n      - The INTCIO GIC_192_201 has 10 output pins, mapped as follows:\n          Bit 0 -\u003e GIC 192\n          Bit 1 -\u003e GIC 193\n          Bit 2 -\u003e GIC 194\n          Bit 3 -\u003e GIC 195\n          Bit 4 -\u003e GIC 196\n\n    - AST2700-tsp\n      - Support TSPINT128 to TSPINT136 in INTC\n      - The INTCIO TSPINT_160_169 has 10 output pins, mapped as follows:\n          Bit 0 -\u003e TSPINT 160\n          Bit 1 -\u003e TSPINT 161\n          Bit 2 -\u003e TSPINT 162\n          Bit 3 -\u003e TSPINT 163\n          Bit 4 -\u003e TSPINT 164\n\nSigned-off-by: Steven Lee \u003csteven_lee@aspeedtech.com\u003e\nChange-Id: I69eec2b68b26ef04187b2922c5f2e584b9076c66\nReviewed-by: Cédric Le Goater \u003cclg@redhat.com\u003e\nLink: https://lore.kernel.org/qemu-devel/20250502103449.3091642-7-steven_lee@aspeedtech.com\n[ clg: removed local \u0027Error* err\u0027 in aspeed_soc_ast27x0tsp_realize() ]\nSigned-off-by: Cédric Le Goater \u003cclg@redhat.com\u003e\n",
  "tree_diff": [
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "4e0efaef07c0441a2676a692336f568da5d8af08",
      "new_mode": 33188,
      "new_path": "hw/arm/aspeed_ast27x0-tsp.c"
    },
    {
      "type": "modify",
      "old_id": "39b74a89ed8e2d538ed22b5b8aca618d7dd3356a",
      "old_mode": 33188,
      "old_path": "hw/arm/meson.build",
      "new_id": "98c563150640291815be0c498948f2e8887899cd",
      "new_mode": 33188,
      "new_path": "hw/arm/meson.build"
    },
    {
      "type": "modify",
      "old_id": "32be90bc35368451546fd8429e61dc18fb93685c",
      "old_mode": 33188,
      "old_path": "include/hw/arm/aspeed_soc.h",
      "new_id": "217ef0eafd6c73d2ce8030e56ca032b58a1264b7",
      "new_mode": 33188,
      "new_path": "include/hw/arm/aspeed_soc.h"
    }
  ]
}