tree 5d3336552c32107e2eb7d79653b2a1cdf081471c
parent 6a91e62694624035064c58bad5b3e75924892355
parent 385e575cd5ab2436c123e4b7f8c9b383a64c0dbe
author Peter Maydell <peter.maydell@linaro.org> 1711105190 +0000
committer Peter Maydell <peter.maydell@linaro.org> 1711105190 +0000
mergetag object 385e575cd5ab2436c123e4b7f8c9b383a64c0dbe
 type commit
 tag pull-riscv-to-apply-20240322
 tagger Alistair Francis <alistair.francis@wdc.com> 1711097407 +1000
 
 RISC-V PR for 9.0
 
 * Do not enable all named features by default
 * A range of Vector fixes
 * Update APLIC IDC after claiming iforce register
 * Remove the dependency of Zvfbfmin to Zfbfmin
 * Fix mode in riscv_tlb_fill
 * Fix timebase-frequency when using KVM acceleration
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Merge tag 'pull-riscv-to-apply-20240322' of https://github.com/alistair23/qemu into staging

RISC-V PR for 9.0

* Do not enable all named features by default
* A range of Vector fixes
* Update APLIC IDC after claiming iforce register
* Remove the dependency of Zvfbfmin to Zfbfmin
* Fix mode in riscv_tlb_fill
* Fix timebase-frequency when using KVM acceleration

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# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown]
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* tag 'pull-riscv-to-apply-20240322' of https://github.com/alistair23/qemu:
  target/riscv/kvm: fix timebase-frequency when using KVM acceleration
  target/riscv: Fix mode in riscv_tlb_fill
  target/riscv: rvv: Remove the dependency of Zvfbfmin to Zfbfmin
  hw/intc: Update APLIC IDC after claiming iforce register
  target/riscv/vector_helper.c: optimize loops in ldst helpers
  target/riscv: enable 'vstart_eq_zero' in the end of insns
  trans_rvv.c.inc: remove redundant mark_vs_dirty() calls
  target/riscv: remove 'over' brconds from vector trans
  target/riscv/vector_helpers: do early exit when vstart >= vl
  target/riscv: always clear vstart for ldst_whole insns
  target/riscv: always clear vstart in whole vec move insns
  target/riscv/vector_helper.c: fix 'vmvr_v' memcpy endianess
  trans_rvv.c.inc: set vstart = 0 in int scalar move insns
  target/riscv/vector_helper.c: set vstart = 0 in GEN_VEXT_VSLIDEUP_VX()
  target/riscv: do not enable all named features by default

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>