)]}'
{
  "commit": "2bfcd27e00a49da2efa5d703121b94cd9cd4948b",
  "tree": "a67e9a49a3364bcea764ae56b1af2a7e9bfc1989",
  "parents": [
    "b496a392fec656d8e7af81c496efa3d45fd59023"
  ],
  "author": {
    "name": "Luc Michel",
    "email": "luc.michel@amd.com",
    "time": "Wed Jul 16 11:53:43 2025 +0200"
  },
  "committer": {
    "name": "Philippe Mathieu-Daudé",
    "email": "philmd@linaro.org",
    "time": "Tue Jul 29 13:56:39 2025 +0200"
  },
  "message": "hw/net/cadence_gem: fix register mask initialization\n\nThe gem_init_register_masks function was called at init time but it\nrelies on the num-priority-queues property. Call it at realize time\ninstead.\n\nCc: qemu-stable@nongnu.org\nFixes: 4c70e32f05f (\"net: cadence_gem: Define access permission for interrupt registers\")\nSigned-off-by: Luc Michel \u003cluc.michel@amd.com\u003e\nReviewed-by: Francisco Iglesias \u003cfrancisco.iglesias@amd.com\u003e\nReviewed-by: Sai Pavan Boddu \u003csai.pavan.boddu@amd.com\u003e\nMessage-ID: \u003c20250716095432.81923-2-luc.michel@amd.com\u003e\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "50025d5a6f2b35882a5948e82872863bc966e3d5",
      "old_mode": 33188,
      "old_path": "hw/net/cadence_gem.c",
      "new_id": "44446666deb26652cb79c9a24bc39329b04feb69",
      "new_mode": 33188,
      "new_path": "hw/net/cadence_gem.c"
    }
  ]
}