commit 29d26d20e5b4a9f28cdd9d072b407223e7b0e610
author aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> Fri Sep 05 19:07:53 2008 +0000
committer aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> Fri Sep 05 19:07:53 2008 +0000
tree f6282aba8ca4adde082eea23ec2811d9f3975aaf
parent 980f8a0b394b8542e49a8df0db420e9862b8f3d1

fix alpha cmovxx instruction

The CMOV instruction is defined by the alpha manual as:

CMOVxx Ra.rq,Rb.rq,Rc.wq !Operate format
CMOVxx Ra.rq,#b.ib,Rc.wq !Operate format

Operation:
IF TEST(Rav, Condition_based_on_Opcode) THEN
Rc ← Rbv

The current qemu behavior inverses Ra and Rb.  This is fixed by this
patch.

Signed-off-by: Tristan Gingold <gingold@adacore.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5171 c046a42c-6fe2-441c-8c8c-71466251a162

target-alpha/translate.c

diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 8376c04..847646f 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -390,15 +390,15 @@
                                     int islit, int8_t lit)
 {
     if (ra != 31)
-        tcg_gen_mov_i64(cpu_T[1], cpu_ir[ra]);
-    else
-        tcg_gen_movi_i64(cpu_T[1], 0);
-    if (islit)
-        tcg_gen_movi_i64(cpu_T[0], lit);
-    else if (rb != 31)
-        tcg_gen_mov_i64(cpu_T[0], cpu_ir[rb]);
+        tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]);
     else
         tcg_gen_movi_i64(cpu_T[0], 0);
+    if (islit)
+        tcg_gen_movi_i64(cpu_T[1], lit);
+    else if (rb != 31)
+        tcg_gen_mov_i64(cpu_T[1], cpu_ir[rb]);
+    else
+        tcg_gen_movi_i64(cpu_T[1], 0);
     (*gen_test_op)();
     gen_op_cmov_ir(rc);
 }