29abd3d112c380b8019a77ebad65f61addfb812d - qemu

commit	29abd3d112c380b8019a77ebad65f61addfb812d	[log] [tgz]
author	Huang Borong <3543977024@qq.com>	Tue Jun 17 15:42:22 2025 +0800
committer	Alistair Francis <alistair.francis@wdc.com>	Fri Jul 04 21:09:49 2025 +1000
tree	d4e216946c7724a28213722e3a5810d9ced76f92
parent	60aab7ad11e6cd8a82420ed6a18416853c0fb762 [diff]

hw/riscv: Initial support for BOSC's Xiangshan Kunminghu FPGA prototype

This implementation provides emulation for the Xiangshan Kunminghu
FPGA prototype platform, including support for UART, CLINT, IMSIC,
and APLIC devices. More details can be found at
https://github.com/OpenXiangShan/XiangShan

Signed-off-by: qinshaoqing <qinshaoqing@bosc.ac.cn>
Signed-off-by: Yang Wang <wangyang@bosc.ac.cn>
Signed-off-by: Yu Hu <819258943@qq.com>
Signed-off-by: Ran Wang <wangran@bosc.ac.cn>
Signed-off-by: Borong Huang <3543977024@qq.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20250617074222.17618-1-wangran@bosc.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

MAINTAINERS[diff]
configs/devices/riscv64-softmmu/default.mak[diff]
docs/system/riscv/xiangshan-kunminghu.rst[Added - diff]
docs/system/target-riscv.rst[diff]
hw/riscv/Kconfig[diff]
hw/riscv/meson.build[diff]
hw/riscv/xiangshan_kmh.c[Added - diff]
include/hw/riscv/xiangshan_kmh.h[Added - diff]

8 files changed

tree: d4e216946c7724a28213722e3a5810d9ced76f92