tree 1ea2c598a7964b41e8b84500bc5ca2dc251ea8f8
parent 3f044554b94fc0756d5b3cdbf84501e0eea0e629
parent 2f5a2315b84a9b1f089ecfc3f31b29813609a7b7
author Richard Henderson <richard.henderson@linaro.org> 1719498976 -0700
committer Richard Henderson <richard.henderson@linaro.org> 1719498976 -0700
mergetag object 2f5a2315b84a9b1f089ecfc3f31b29813609a7b7
 type commit
 tag pull-riscv-to-apply-20240627-1
 tagger Alistair Francis <alistair.francis@wdc.com> 1719482396 +1000
 
 RISC-V PR for 9.1
 
 * Extend virtual irq csrs masks to be 64 bit wide
 * Move Guest irqs out of the core local irqs range
 * zvbb implies zvkb
 * virt: add address-cells in create_fdt_one_aplic()
 * virt: add aplic nodename helper
 * virt: rename aplic nodename to 'interrupt-controller'
 * virt: aplic DT: add 'qemu, aplic' to 'compatible'
 * virt: aplic DT: rename prop to 'riscv, delegation'
 * virt: change imsic nodename to 'interrupt-controller'
 * virt: imsics DT: add 'qemu, imsics' to 'compatible'
 * virt: imsics DT: add '#msi-cells'
 * QEMU support for KVM Guest Debug on RISC-V
 * Support RISC-V privilege 1.13 spec
 * Add support for RISC-V ACPI tests
 * Modularize common match conditions for trigger
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Merge tag 'pull-riscv-to-apply-20240627-1' of https://github.com/alistair23/qemu into staging

RISC-V PR for 9.1

* Extend virtual irq csrs masks to be 64 bit wide
* Move Guest irqs out of the core local irqs range
* zvbb implies zvkb
* virt: add address-cells in create_fdt_one_aplic()
* virt: add aplic nodename helper
* virt: rename aplic nodename to 'interrupt-controller'
* virt: aplic DT: add 'qemu, aplic' to 'compatible'
* virt: aplic DT: rename prop to 'riscv, delegation'
* virt: change imsic nodename to 'interrupt-controller'
* virt: imsics DT: add 'qemu, imsics' to 'compatible'
* virt: imsics DT: add '#msi-cells'
* QEMU support for KVM Guest Debug on RISC-V
* Support RISC-V privilege 1.13 spec
* Add support for RISC-V ACPI tests
* Modularize common match conditions for trigger

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# gpg: Signature made Thu 27 Jun 2024 03:00:01 AM PDT
# gpg:                using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65  9296 AF7C 9513 0C53 8013

* tag 'pull-riscv-to-apply-20240627-1' of https://github.com/alistair23/qemu: (32 commits)
  target/riscv: Apply modularized matching conditions for icount trigger
  target/riscv: Apply modularized matching conditions for watchpoint
  target/riscv: Add functions for common matching conditions of trigger
  target/riscv: Remove extension auto-update check statements
  target/riscv: Add Zc extension implied rule
  target/riscv: Add multi extension implied rules
  target/riscv: Add MISA extension implied rules
  target/riscv: Introduce extension implied rule helpers
  target/riscv: Introduce extension implied rules definition
  target/riscv: fix instructions count handling in icount mode
  target/riscv: Fix froundnx.h nanbox check
  hw/riscv/virt.c: Make block devices default to virtio
  target/riscv: Support the version for ss1p13
  target/riscv: Reserve exception codes for sw-check and hw-err
  target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32
  target/riscv: Add 'P1P13' bit in SMSTATEEN0
  target/riscv: Define macros and variables for ss1p13
  target/riscv: Reuse the conversion function of priv_spec
  target/riscv/kvm: define TARGET_KVM_HAVE_GUEST_DEBUG
  target/riscv/kvm: handle the exit with debug reason
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>