)]}'
{
  "commit": "282ff9baebba548f8b6bfb63ffd53f40c8a0ce14",
  "tree": "6481c10065162ebe242358c070fae7806cd2cb7f",
  "parents": [
    "975a1bd4399b0a00f89996e838f418c256fa0b56"
  ],
  "author": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Mon Aug 17 13:38:37 2026 +0100"
  },
  "committer": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Fri Aug 21 09:50:40 2026 +0100"
  },
  "message": "target/arm: Implement CPACR.D32DIS\n\nOn some v7A CPUs, CPACR.D32DIS is a bit allowing the guest to make\nVFP instructions that touch registers D16..D31 UNDEF.  Whether the\nCPU implements this or not is IMPDEF, and the only two CPUs we\nimplement which have this are the Cortex-A7 and Cortex-A9.  In v8A\nthe bit is no longer defined at all.\n\nSince the only kind of trapping that needs to be done is a simple\nUNDEF, this is straightforward enough to implement.\n\nResolves: https://gitlab.com/qemu-project/qemu/-/work_items/1499\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nMessage-id: 20260817123838.1578060-8-peter.maydell@linaro.org\n",
  "tree_diff": [
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      "new_path": "target/arm/tcg/cpu32.c"
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}