commit 274f33765af36b5c7447adec18b61125f05b7b83
author Richard Henderson <richard.henderson@linaro.org> Fri Jun 02 14:14:04 2023 -0700
committer Richard Henderson <richard.henderson@linaro.org> Sun Jul 09 13:47:17 2023 +0100
tree 7571c5e81061a5626b8d1f126f5fc53a8cfb4617
parent 607a5f9d624fdd63d0b7f0e640f7a8d21213b8df

target/riscv: Use aesenc_SB_SR_MC_AK

This implements the AES64ESM instruction.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/riscv/crypto_helper.c

diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c
index 505166c..c036fe8 100644
--- a/target/riscv/crypto_helper.c
+++ b/target/riscv/crypto_helper.c
@@ -198,7 +198,12 @@
 
 target_ulong HELPER(aes64esm)(target_ulong rs1, target_ulong rs2)
 {
-    return aes64_operation(rs1, rs2, true, true);
+    AESState t;
+
+    t.d[HOST_BIG_ENDIAN] = rs1;
+    t.d[!HOST_BIG_ENDIAN] = rs2;
+    aesenc_SB_SR_MC_AK(&t, &t, &aes_zero, false);
+    return t.d[HOST_BIG_ENDIAN];
 }
 
 target_ulong HELPER(aes64es)(target_ulong rs1, target_ulong rs2)