| commit | 193fb5c9bd1fbf8a0b78c75f2056b0d7d9fc0ffe | [log] [tgz] |
|---|---|---|
| author | Frank Chang <frank.chang@sifive.com> | Tue Jan 18 09:45:10 2022 +0800 |
| committer | Alistair Francis <alistair.francis@wdc.com> | Fri Jan 21 15:52:56 2022 +1000 |
| tree | bac6adb9cb66e10a670e311b386ca9bdb280fd0b | |
| parent | 40d78c85f6f321c00588230a400477250a85c2e7 [diff] |
target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns Vector single-width floating-point reduction operations for EEW=32 are supported for Zve64f extension. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220118014522.13613-8-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>