Implement SSE4.1, SSE4.2 (x86).
This adds support for CPUID_EXT_SSE41, CPUID_EXT_SSE42, CPUID_EXT_POPCNT
extensions. Most instructions haven't been tested yet.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5411 c046a42c-6fe2-441c-8c8c-71466251a162
diff --git a/tests/test-i386-ssse3.c b/tests/test-i386-ssse3.c
index 0a43d27..0a42bd0 100644
--- a/tests/test-i386-ssse3.c
+++ b/tests/test-i386-ssse3.c
@@ -1,6 +1,7 @@
/* See if various MMX/SSE SSSE3 instructions give expected results */
#include <stdio.h>
#include <string.h>
+#include <stdint.h>
int main(int argc, char *argv[]) {
char hello[16];
@@ -9,9 +10,11 @@
uint64_t a = 0x0000000000090007;
uint64_t b = 0x0000000000000000;
+ uint32_t c;
+ uint16_t d;
- const char c[16] = "LLOaaaaaaaaaaaaa";
- const char d[16] = "aaaaaaaaaaaaaaHE";
+ const char e[16] = "LLOaaaaaaaaaaaaa";
+ const char f[16] = "aaaaaaaaaaaaaaHE";
/* pshufb mm1/xmm1, mm2/xmm2 */
asm volatile ("movq (%0), %%mm0" : : "r" (ehlo) : "mm0", "mm1");
@@ -33,10 +36,22 @@
printf("%i - %i = %i\n", 9, 7, -(int16_t) a);
/* palignr mm1/xmm1, m64/m128, imm8 */
- asm volatile ("movdqa (%0), %%xmm0" : : "r" (c) : "xmm0");
- asm volatile ("palignr $14, (%0), %%xmm0" : : "r" (d));
+ asm volatile ("movdqa (%0), %%xmm0" : : "r" (e) : "xmm0");
+ asm volatile ("palignr $14, (%0), %%xmm0" : : "r" (f));
asm volatile ("movdqa %%xmm0, (%0)" : : "r" (hello));
printf("%5.5s\n", hello);
+#if 1 /* SSE4 */
+ /* popcnt r64, r/m64 */
+ asm volatile ("movq $0x8421000010009c63, %%rax" : : : "rax");
+ asm volatile ("popcnt %%ax, %%dx" : : : "dx");
+ asm volatile ("popcnt %%eax, %%ecx" : : : "ecx");
+ asm volatile ("popcnt %rax, %rax");
+ asm volatile ("movq %%rax, %0" : "=m" (a));
+ asm volatile ("movl %%ecx, %0" : "=m" (c));
+ asm volatile ("movw %%dx, %0" : "=m" (d));
+ printf("%i = %i\n%i = %i = %i\n", 13, (int) a, 9, c, d + 1);
+#endif
+
return 0;
}
