commit 212c88c0c78b1b2027b91d0669b92c49d921e91c
author Richard Henderson <richard.henderson@linaro.org> Wed Jul 07 18:50:46 2021 -0700
committer Richard Henderson <richard.henderson@linaro.org> Tue Jul 13 08:13:19 2021 -0700
tree 8e264bac0a9618e1a51b5505805dd50ac289e5bf
parent 3e646c3a3cfb1ce9522c230c2cbbafaf42f0a9c5

target/alpha: Use tcg_constant_i64 for zero and lit

These constant temps do not need to be freed, and
therefore need less bookkeeping from tcg producers.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/alpha/translate.c

diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index 64c4865..58c0e08 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -66,8 +66,6 @@
     /* Temporaries for $31 and $f31 as source and destination.  */
     TCGv zero;
     TCGv sink;
-    /* Temporary for immediate constants.  */
-    TCGv lit;
 };
 
 /* Target-specific return values from translate_one, indicating the
@@ -157,7 +155,7 @@
 static TCGv load_zero(DisasContext *ctx)
 {
     if (!ctx->zero) {
-        ctx->zero = tcg_const_i64(0);
+        ctx->zero = tcg_constant_i64(0);
     }
     return ctx->zero;
 }
@@ -177,14 +175,6 @@
         tcg_temp_free(ctx->sink);
         ctx->sink = NULL;
     }
-    if (ctx->zero) {
-        tcg_temp_free(ctx->zero);
-        ctx->zero = NULL;
-    }
-    if (ctx->lit) {
-        tcg_temp_free(ctx->lit);
-        ctx->lit = NULL;
-    }
 }
 
 static TCGv load_gpr(DisasContext *ctx, unsigned reg)
@@ -200,8 +190,7 @@
                          uint8_t lit, bool islit)
 {
     if (islit) {
-        ctx->lit = tcg_const_i64(lit);
-        return ctx->lit;
+        return tcg_constant_i64(lit);
     } else if (likely(reg < 31)) {
         return ctx->ir[reg];
     } else {
@@ -2992,7 +2981,6 @@
 
     ctx->zero = NULL;
     ctx->sink = NULL;
-    ctx->lit = NULL;
 
     /* Bound the number of insns to execute to those left on the page.  */
     bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;