Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging
Pull request
Bug fixes for 7.0.
# gpg: Signature made Thu 17 Mar 2022 16:42:22 GMT
# gpg: using RSA key 8695A8BFD3F97CDAAC35775A9CA4ABB381AB73C8
# gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" [full]
# gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" [full]
# Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8
* tag 'block-pull-request' of https://gitlab.com/stefanha/qemu:
aio-posix: fix spurious ->poll_ready() callbacks in main loop
aio-posix: fix build failure io_uring 2.2
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
diff --git a/audio/mixeng.c b/audio/mixeng.c
index f27deb1..100a306 100644
--- a/audio/mixeng.c
+++ b/audio/mixeng.c
@@ -342,13 +342,13 @@
void audio_sample_to_uint64(const void *samples, int pos,
uint64_t *left, uint64_t *right)
{
- const struct st_sample *sample = samples;
- sample += pos;
#ifdef FLOAT_MIXENG
error_report(
"Coreaudio and floating point samples are not supported by replay yet");
abort();
#else
+ const struct st_sample *sample = samples;
+ sample += pos;
*left = sample->l;
*right = sample->r;
#endif
@@ -357,13 +357,13 @@
void audio_sample_from_uint64(void *samples, int pos,
uint64_t left, uint64_t right)
{
- struct st_sample *sample = samples;
- sample += pos;
#ifdef FLOAT_MIXENG
error_report(
"Coreaudio and floating point samples are not supported by replay yet");
abort();
#else
+ struct st_sample *sample = samples;
+ sample += pos;
sample->l = left;
sample->r = right;
#endif
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 46a4250..d2e5ecd 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -1852,7 +1852,12 @@
vms->gic_version = VIRT_GIC_VERSION_2;
break;
case VIRT_GIC_VERSION_MAX:
- vms->gic_version = VIRT_GIC_VERSION_3;
+ if (module_object_class_by_name("arm-gicv3")) {
+ /* CONFIG_ARM_GICV3_TCG was set */
+ vms->gic_version = VIRT_GIC_VERSION_3;
+ } else {
+ vms->gic_version = VIRT_GIC_VERSION_2;
+ }
break;
case VIRT_GIC_VERSION_HOST:
error_report("gic-version=host requires KVM");
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index 6d0e411..5bfe285 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -52,6 +52,13 @@
#define QSPI_DMA_ADDR 0xff0f0800
#define NUM_QSPI_IRQ_LINES 2
+#define CRF_ADDR 0xfd1a0000
+#define CRF_IRQ 120
+
+/* Serializer/Deserializer. */
+#define SERDES_ADDR 0xfd400000
+#define SERDES_SIZE 0x20000
+
#define DP_ADDR 0xfd4a0000
#define DP_IRQ 113
@@ -59,7 +66,7 @@
#define DPDMA_IRQ 116
#define APU_ADDR 0xfd5c0000
-#define APU_SIZE 0x100
+#define APU_IRQ 153
#define IPI_ADDR 0xFF300000
#define IPI_IRQ 64
@@ -276,6 +283,39 @@
sysbus_connect_irq(sbd, 0, gic[EFUSE_IRQ]);
}
+static void xlnx_zynqmp_create_apu_ctrl(XlnxZynqMPState *s, qemu_irq *gic)
+{
+ SysBusDevice *sbd;
+ int i;
+
+ object_initialize_child(OBJECT(s), "apu-ctrl", &s->apu_ctrl,
+ TYPE_XLNX_ZYNQMP_APU_CTRL);
+ sbd = SYS_BUS_DEVICE(&s->apu_ctrl);
+
+ for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
+ g_autofree gchar *name = g_strdup_printf("cpu%d", i);
+
+ object_property_set_link(OBJECT(&s->apu_ctrl), name,
+ OBJECT(&s->apu_cpu[i]), &error_abort);
+ }
+
+ sysbus_realize(sbd, &error_fatal);
+ sysbus_mmio_map(sbd, 0, APU_ADDR);
+ sysbus_connect_irq(sbd, 0, gic[APU_IRQ]);
+}
+
+static void xlnx_zynqmp_create_crf(XlnxZynqMPState *s, qemu_irq *gic)
+{
+ SysBusDevice *sbd;
+
+ object_initialize_child(OBJECT(s), "crf", &s->crf, TYPE_XLNX_ZYNQMP_CRF);
+ sbd = SYS_BUS_DEVICE(&s->crf);
+
+ sysbus_realize(sbd, &error_fatal);
+ sysbus_mmio_map(sbd, 0, CRF_ADDR);
+ sysbus_connect_irq(sbd, 0, gic[CRF_IRQ]);
+}
+
static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s)
{
static const struct UnimpInfo {
@@ -283,7 +323,7 @@
hwaddr base;
hwaddr size;
} unimp_areas[ARRAY_SIZE(s->mr_unimp)] = {
- { .name = "apu", APU_ADDR, APU_SIZE },
+ { .name = "serdes", SERDES_ADDR, SERDES_SIZE },
};
unsigned int nr;
@@ -679,6 +719,8 @@
xlnx_zynqmp_create_bbram(s, gic_spi);
xlnx_zynqmp_create_efuse(s, gic_spi);
+ xlnx_zynqmp_create_apu_ctrl(s, gic_spi);
+ xlnx_zynqmp_create_crf(s, gic_spi);
xlnx_zynqmp_create_unimp_mmio(s);
for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
diff --git a/hw/display/ati.c b/hw/display/ati.c
index 31f2275..6e38e00 100644
--- a/hw/display/ati.c
+++ b/hw/display/ati.c
@@ -955,7 +955,9 @@
}
/* init vga bits */
- vga_common_init(vga, OBJECT(s));
+ if (!vga_common_init(vga, OBJECT(s), errp)) {
+ return;
+ }
vga_init(vga, OBJECT(s), pci_address_space(dev),
pci_address_space_io(dev), true);
vga->con = graphic_console_init(DEVICE(s), 0, s->vga.hw_ops, &s->vga);
diff --git a/hw/display/cirrus_vga.c b/hw/display/cirrus_vga.c
index fdca6ca..3bb6a58 100644
--- a/hw/display/cirrus_vga.c
+++ b/hw/display/cirrus_vga.c
@@ -2940,27 +2940,30 @@
static void pci_cirrus_vga_realize(PCIDevice *dev, Error **errp)
{
- PCICirrusVGAState *d = PCI_CIRRUS_VGA(dev);
- CirrusVGAState *s = &d->cirrus_vga;
- PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
- int16_t device_id = pc->device_id;
+ PCICirrusVGAState *d = PCI_CIRRUS_VGA(dev);
+ CirrusVGAState *s = &d->cirrus_vga;
+ PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
+ int16_t device_id = pc->device_id;
- /* follow real hardware, cirrus card emulated has 4 MB video memory.
- Also accept 8 MB/16 MB for backward compatibility. */
- if (s->vga.vram_size_mb != 4 && s->vga.vram_size_mb != 8 &&
- s->vga.vram_size_mb != 16) {
- error_setg(errp, "Invalid cirrus_vga ram size '%u'",
- s->vga.vram_size_mb);
- return;
- }
- /* setup VGA */
- vga_common_init(&s->vga, OBJECT(dev));
- cirrus_init_common(s, OBJECT(dev), device_id, 1, pci_address_space(dev),
- pci_address_space_io(dev));
- s->vga.con = graphic_console_init(DEVICE(dev), 0, s->vga.hw_ops, &s->vga);
+ /*
+ * Follow real hardware, cirrus card emulated has 4 MB video memory.
+ * Also accept 8 MB/16 MB for backward compatibility.
+ */
+ if (s->vga.vram_size_mb != 4 && s->vga.vram_size_mb != 8 &&
+ s->vga.vram_size_mb != 16) {
+ error_setg(errp, "Invalid cirrus_vga ram size '%u'",
+ s->vga.vram_size_mb);
+ return;
+ }
+ /* setup VGA */
+ if (!vga_common_init(&s->vga, OBJECT(dev), errp)) {
+ return;
+ }
+ cirrus_init_common(s, OBJECT(dev), device_id, 1, pci_address_space(dev),
+ pci_address_space_io(dev));
+ s->vga.con = graphic_console_init(DEVICE(dev), 0, s->vga.hw_ops, &s->vga);
- /* setup PCI */
-
+ /* setup PCI */
memory_region_init(&s->pci_bar, OBJECT(dev), "cirrus-pci-bar0", 0x2000000);
/* XXX: add byte swapping apertures */
@@ -2968,14 +2971,14 @@
memory_region_add_subregion(&s->pci_bar, 0x1000000,
&s->cirrus_linear_bitblt_io);
- /* setup memory space */
- /* memory #0 LFB */
- /* memory #1 memory-mapped I/O */
- /* XXX: s->vga.vram_size must be a power of two */
- pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->pci_bar);
- if (device_id == CIRRUS_ID_CLGD5446) {
- pci_register_bar(&d->dev, 1, 0, &s->cirrus_mmio_io);
- }
+ /* setup memory space */
+ /* memory #0 LFB */
+ /* memory #1 memory-mapped I/O */
+ /* XXX: s->vga.vram_size must be a power of two */
+ pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->pci_bar);
+ if (device_id == CIRRUS_ID_CLGD5446) {
+ pci_register_bar(&d->dev, 1, 0, &s->cirrus_mmio_io);
+ }
}
static Property pci_vga_cirrus_properties[] = {
diff --git a/hw/display/cirrus_vga_isa.c b/hw/display/cirrus_vga_isa.c
index 4f6fb1a..96144bd 100644
--- a/hw/display/cirrus_vga_isa.c
+++ b/hw/display/cirrus_vga_isa.c
@@ -56,7 +56,9 @@
return;
}
s->global_vmstate = true;
- vga_common_init(s, OBJECT(dev));
+ if (!vga_common_init(s, OBJECT(dev), errp)) {
+ return;
+ }
cirrus_init_common(&d->cirrus_vga, OBJECT(dev), CIRRUS_ID_CLGD5430, 0,
isa_address_space(isadev),
isa_address_space_io(isadev));
diff --git a/hw/display/qxl.c b/hw/display/qxl.c
index 1f9ad31..adbdbca 100644
--- a/hw/display/qxl.c
+++ b/hw/display/qxl.c
@@ -2215,7 +2215,11 @@
qxl_init_ramsize(qxl);
vga->vbe_size = qxl->vgamem_size;
vga->vram_size_mb = qxl->vga.vram_size / MiB;
- vga_common_init(vga, OBJECT(dev));
+ vga_common_init(vga, OBJECT(dev), &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
vga_init(vga, OBJECT(dev),
pci_address_space(dev), pci_address_space_io(dev), false);
portio_list_init(&qxl->vga_port_list, OBJECT(dev), qxl_vga_portio_list,
diff --git a/hw/display/vga-isa.c b/hw/display/vga-isa.c
index 90851e7..46abbc5 100644
--- a/hw/display/vga-isa.c
+++ b/hw/display/vga-isa.c
@@ -62,7 +62,10 @@
const MemoryRegionPortio *vga_ports, *vbe_ports;
s->global_vmstate = true;
- vga_common_init(s, OBJECT(dev));
+ if (!vga_common_init(s, OBJECT(dev), errp)) {
+ return;
+ }
+
s->legacy_address_space = isa_address_space(isadev);
vga_io_memory = vga_init_io(s, OBJECT(dev), &vga_ports, &vbe_ports);
isa_register_portio_list(isadev, &d->portio_vga,
diff --git a/hw/display/vga-mmio.c b/hw/display/vga-mmio.c
index 4969368..75dfced 100644
--- a/hw/display/vga-mmio.c
+++ b/hw/display/vga-mmio.c
@@ -102,7 +102,10 @@
s->vga.bank_offset = 0;
s->vga.global_vmstate = true;
- vga_common_init(&s->vga, OBJECT(dev));
+ if (!vga_common_init(&s->vga, OBJECT(dev), errp)) {
+ return;
+ }
+
sysbus_init_mmio(sbd, &s->vga.vram);
s->vga.con = graphic_console_init(dev, 0, s->vga.hw_ops, &s->vga);
}
diff --git a/hw/display/vga-pci.c b/hw/display/vga-pci.c
index 62fb5c3..3e5bc25 100644
--- a/hw/display/vga-pci.c
+++ b/hw/display/vga-pci.c
@@ -239,7 +239,9 @@
bool edid = false;
/* vga + console init */
- vga_common_init(s, OBJECT(dev));
+ if (!vga_common_init(s, OBJECT(dev), errp)) {
+ return;
+ }
vga_init(s, OBJECT(dev), pci_address_space(dev), pci_address_space_io(dev),
true);
@@ -275,7 +277,9 @@
bool edid = false;
/* vga + console init */
- vga_common_init(s, OBJECT(dev));
+ if (!vga_common_init(s, OBJECT(dev), errp)) {
+ return;
+ }
s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s);
/* mmio bar */
diff --git a/hw/display/vga.c b/hw/display/vga.c
index 9d1f66a..a7a291f 100644
--- a/hw/display/vga.c
+++ b/hw/display/vga.c
@@ -2168,9 +2168,10 @@
return val;
}
-void vga_common_init(VGACommonState *s, Object *obj)
+bool vga_common_init(VGACommonState *s, Object *obj, Error **errp)
{
int i, j, v, b;
+ Error *local_err = NULL;
for(i = 0;i < 256; i++) {
v = 0;
@@ -2205,8 +2206,18 @@
s->vbe_size_mask = s->vbe_size - 1;
s->is_vbe_vmstate = 1;
+
+ if (s->global_vmstate && qemu_ram_block_by_name("vga.vram")) {
+ error_setg(errp, "Only one global VGA device can be used at a time");
+ return false;
+ }
+
memory_region_init_ram_nomigrate(&s->vram, obj, "vga.vram", s->vram_size,
- &error_fatal);
+ &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return false;
+ }
vmstate_register_ram(&s->vram, s->global_vmstate ? NULL : DEVICE(obj));
xen_register_framebuffer(&s->vram);
s->vram_ptr = memory_region_get_ram_ptr(&s->vram);
@@ -2237,6 +2248,8 @@
s->default_endian_fb = false;
#endif
vga_dirty_log_start(s);
+
+ return true;
}
static const MemoryRegionPortio vga_portio_list[] = {
diff --git a/hw/display/vga_int.h b/hw/display/vga_int.h
index 847e784..305e700 100644
--- a/hw/display/vga_int.h
+++ b/hw/display/vga_int.h
@@ -156,7 +156,7 @@
return (v << 2) | (b << 1) | b;
}
-void vga_common_init(VGACommonState *s, Object *obj);
+bool vga_common_init(VGACommonState *s, Object *obj, Error **errp);
void vga_init(VGACommonState *s, Object *obj, MemoryRegion *address_space,
MemoryRegion *address_space_io, bool init_vga_ports);
MemoryRegion *vga_init_io(VGACommonState *s, Object *obj,
diff --git a/hw/display/virtio-vga.c b/hw/display/virtio-vga.c
index 5a2f7a4..7b55c8d 100644
--- a/hw/display/virtio-vga.c
+++ b/hw/display/virtio-vga.c
@@ -108,7 +108,9 @@
/* init vga compat bits */
vga->vram_size_mb = 8;
- vga_common_init(vga, OBJECT(vpci_dev));
+ if (!vga_common_init(vga, OBJECT(vpci_dev), errp)) {
+ return;
+ }
vga_init(vga, OBJECT(vpci_dev), pci_address_space(&vpci_dev->pci_dev),
pci_address_space_io(&vpci_dev->pci_dev), true);
pci_register_bar(&vpci_dev->pci_dev, 0,
diff --git a/hw/display/vmware_vga.c b/hw/display/vmware_vga.c
index 0cc43a1..98c8347 100644
--- a/hw/display/vmware_vga.c
+++ b/hw/display/vmware_vga.c
@@ -1254,7 +1254,7 @@
&error_fatal);
s->fifo_ptr = memory_region_get_ram_ptr(&s->fifo_ram);
- vga_common_init(&s->vga, OBJECT(dev));
+ vga_common_init(&s->vga, OBJECT(dev), &error_fatal);
vga_init(&s->vga, OBJECT(dev), address_space, io, true);
vmstate_register(NULL, 0, &vmstate_vga_common, &s->vga);
s->new_depth = 32;
diff --git a/hw/dma/xlnx_csu_dma.c b/hw/dma/xlnx_csu_dma.c
index 84f782f..60ada32 100644
--- a/hw/dma/xlnx_csu_dma.c
+++ b/hw/dma/xlnx_csu_dma.c
@@ -744,6 +744,7 @@
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(XlnxCSUDMA),
.class_init = xlnx_csu_dma_class_init,
+ .class_size = sizeof(XlnxCSUDMAClass),
.instance_init = xlnx_csu_dma_init,
.interfaces = (InterfaceInfo[]) {
{ TYPE_STREAM_SINK },
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 4ad4d72..dcf6ece 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -583,7 +583,7 @@
Aml *bnum = aml_arg(4);
Aml *func = aml_arg(2);
Aml *rev = aml_arg(1);
- Aml *sun = aml_arg(5);
+ Aml *sunum = aml_arg(5);
method = aml_method("PDSM", 6, AML_SERIALIZED);
@@ -594,7 +594,7 @@
UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D");
ifctx = aml_if(aml_equal(aml_arg(0), UUID));
{
- aml_append(ifctx, aml_store(aml_call2("AIDX", bnum, sun), acpi_index));
+ aml_append(ifctx, aml_store(aml_call2("AIDX", bnum, sunum), acpi_index));
ifctx1 = aml_if(aml_equal(func, zero));
{
uint8_t byte_list[1];
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
index ec8d4ce..a7cf301 100644
--- a/hw/intc/Kconfig
+++ b/hw/intc/Kconfig
@@ -25,7 +25,7 @@
select MSI_NONBROKEN
select I8259
-config ARM_GIC_TCG
+config ARM_GICV3_TCG
bool
default y
depends on ARM_GIC && TCG
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index 81ccdb0d..d6d012f 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -6,7 +6,7 @@
'arm_gicv3_common.c',
'arm_gicv3_its_common.c',
))
-softmmu_ss.add(when: 'CONFIG_ARM_GIC_TCG', if_true: files(
+softmmu_ss.add(when: 'CONFIG_ARM_GICV3_TCG', if_true: files(
'arm_gicv3.c',
'arm_gicv3_dist.c',
'arm_gicv3_its.c',
@@ -28,7 +28,7 @@
specific_ss.add(when: 'CONFIG_ALLWINNER_A10_PIC', if_true: files('allwinner-a10-pic.c'))
specific_ss.add(when: 'CONFIG_APIC', if_true: files('apic.c', 'apic_common.c'))
specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif_common.c'))
-specific_ss.add(when: 'CONFIG_ARM_GIC_TCG', if_true: files('arm_gicv3_cpuif.c'))
+specific_ss.add(when: 'CONFIG_ARM_GICV3_TCG', if_true: files('arm_gicv3_cpuif.c'))
specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files('arm_gic_kvm.c'))
specific_ss.add(when: ['CONFIG_ARM_GIC_KVM', 'TARGET_AARCH64'], if_true: files('arm_gicv3_kvm.c', 'arm_gicv3_its_kvm.c'))
specific_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_nvic.c'))
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index 6455853..6fb6961 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -84,6 +84,8 @@
))
softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c'))
+specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-crf.c'))
+specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-apu-ctrl.c'))
softmmu_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files(
'xlnx-versal-xramc.c',
'xlnx-versal-pmc-iou-slcr.c',
diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c
index 0b61070..bc2b879 100644
--- a/hw/misc/npcm7xx_clk.c
+++ b/hw/misc/npcm7xx_clk.c
@@ -612,8 +612,8 @@
NPCM7xxClockSELState *sel = NPCM7XX_CLOCK_SEL(obj);
for (i = 0; i < NPCM7XX_CLK_SEL_MAX_INPUT; ++i) {
- sel->clock_in[i] = qdev_init_clock_in(DEVICE(sel),
- g_strdup_printf("clock-in[%d]", i),
+ g_autofree char *s = g_strdup_printf("clock-in[%d]", i);
+ sel->clock_in[i] = qdev_init_clock_in(DEVICE(sel), s,
npcm7xx_clk_update_sel_cb, sel, ClockUpdate);
}
sel->clock_out = qdev_init_clock_out(DEVICE(sel), "clock-out");
diff --git a/hw/misc/xlnx-zynqmp-apu-ctrl.c b/hw/misc/xlnx-zynqmp-apu-ctrl.c
new file mode 100644
index 0000000..20de23c
--- /dev/null
+++ b/hw/misc/xlnx-zynqmp-apu-ctrl.c
@@ -0,0 +1,253 @@
+/*
+ * QEMU model of the ZynqMP APU Control.
+ *
+ * Copyright (c) 2013-2022 Xilinx Inc
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> and
+ * Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu/log.h"
+#include "migration/vmstate.h"
+#include "hw/qdev-properties.h"
+#include "hw/sysbus.h"
+#include "hw/irq.h"
+#include "hw/register.h"
+
+#include "qemu/bitops.h"
+#include "qapi/qmp/qerror.h"
+
+#include "hw/misc/xlnx-zynqmp-apu-ctrl.h"
+
+#ifndef XILINX_ZYNQMP_APU_ERR_DEBUG
+#define XILINX_ZYNQMP_APU_ERR_DEBUG 0
+#endif
+
+static void update_wfi_out(void *opaque)
+{
+ XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(opaque);
+ unsigned int i, wfi_pending;
+
+ wfi_pending = s->cpu_pwrdwn_req & s->cpu_in_wfi;
+ for (i = 0; i < APU_MAX_CPU; i++) {
+ qemu_set_irq(s->wfi_out[i], !!(wfi_pending & (1 << i)));
+ }
+}
+
+static void zynqmp_apu_rvbar_post_write(RegisterInfo *reg, uint64_t val)
+{
+ XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(reg->opaque);
+ int i;
+
+ for (i = 0; i < APU_MAX_CPU; ++i) {
+ uint64_t rvbar = s->regs[R_RVBARADDR0L + 2 * i] +
+ ((uint64_t)s->regs[R_RVBARADDR0H + 2 * i] << 32);
+ if (s->cpus[i]) {
+ object_property_set_int(OBJECT(s->cpus[i]), "rvbar", rvbar,
+ &error_abort);
+ }
+ }
+}
+
+static void zynqmp_apu_pwrctl_post_write(RegisterInfo *reg, uint64_t val)
+{
+ XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(reg->opaque);
+ unsigned int i, new;
+
+ for (i = 0; i < APU_MAX_CPU; i++) {
+ new = val & (1 << i);
+ /* Check if CPU's CPUPWRDNREQ has changed. If yes, update GPIOs. */
+ if (new != (s->cpu_pwrdwn_req & (1 << i))) {
+ qemu_set_irq(s->cpu_power_status[i], !!new);
+ }
+ s->cpu_pwrdwn_req &= ~(1 << i);
+ s->cpu_pwrdwn_req |= new;
+ }
+ update_wfi_out(s);
+}
+
+static void imr_update_irq(XlnxZynqMPAPUCtrl *s)
+{
+ bool pending = s->regs[R_ISR] & ~s->regs[R_IMR];
+ qemu_set_irq(s->irq_imr, pending);
+}
+
+static void isr_postw(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(reg->opaque);
+ imr_update_irq(s);
+}
+
+static uint64_t ien_prew(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(reg->opaque);
+ uint32_t val = val64;
+
+ s->regs[R_IMR] &= ~val;
+ imr_update_irq(s);
+ return 0;
+}
+
+static uint64_t ids_prew(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(reg->opaque);
+ uint32_t val = val64;
+
+ s->regs[R_IMR] |= val;
+ imr_update_irq(s);
+ return 0;
+}
+
+static const RegisterAccessInfo zynqmp_apu_regs_info[] = {
+#define RVBAR_REGDEF(n) \
+ { .name = "RVBAR CPU " #n " Low", .addr = A_RVBARADDR ## n ## L, \
+ .reset = 0xffff0000ul, \
+ .post_write = zynqmp_apu_rvbar_post_write, \
+ },{ .name = "RVBAR CPU " #n " High", .addr = A_RVBARADDR ## n ## H, \
+ .post_write = zynqmp_apu_rvbar_post_write, \
+ }
+ { .name = "ERR_CTRL", .addr = A_APU_ERR_CTRL,
+ },{ .name = "ISR", .addr = A_ISR,
+ .w1c = 0x1,
+ .post_write = isr_postw,
+ },{ .name = "IMR", .addr = A_IMR,
+ .reset = 0x1,
+ .ro = 0x1,
+ },{ .name = "IEN", .addr = A_IEN,
+ .pre_write = ien_prew,
+ },{ .name = "IDS", .addr = A_IDS,
+ .pre_write = ids_prew,
+ },{ .name = "CONFIG_0", .addr = A_CONFIG_0,
+ .reset = 0xf0f,
+ },{ .name = "CONFIG_1", .addr = A_CONFIG_1,
+ },
+ RVBAR_REGDEF(0),
+ RVBAR_REGDEF(1),
+ RVBAR_REGDEF(2),
+ RVBAR_REGDEF(3),
+ { .name = "ACE_CTRL", .addr = A_ACE_CTRL,
+ .reset = 0xf000f,
+ },{ .name = "SNOOP_CTRL", .addr = A_SNOOP_CTRL,
+ },{ .name = "PWRCTL", .addr = A_PWRCTL,
+ .post_write = zynqmp_apu_pwrctl_post_write,
+ },{ .name = "PWRSTAT", .addr = A_PWRSTAT,
+ .ro = 0x3000f,
+ }
+};
+
+static void zynqmp_apu_reset_enter(Object *obj, ResetType type)
+{
+ XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(obj);
+ int i;
+
+ for (i = 0; i < APU_R_MAX; ++i) {
+ register_reset(&s->regs_info[i]);
+ }
+
+ s->cpu_pwrdwn_req = 0;
+ s->cpu_in_wfi = 0;
+}
+
+static void zynqmp_apu_reset_hold(Object *obj)
+{
+ XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(obj);
+
+ update_wfi_out(s);
+ imr_update_irq(s);
+}
+
+static const MemoryRegionOps zynqmp_apu_ops = {
+ .read = register_read_memory,
+ .write = register_write_memory,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ }
+};
+
+static void zynqmp_apu_handle_wfi(void *opaque, int irq, int level)
+{
+ XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(opaque);
+
+ s->cpu_in_wfi = deposit32(s->cpu_in_wfi, irq, 1, level);
+ update_wfi_out(s);
+}
+
+static void zynqmp_apu_init(Object *obj)
+{
+ XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(obj);
+ int i;
+
+ s->reg_array =
+ register_init_block32(DEVICE(obj), zynqmp_apu_regs_info,
+ ARRAY_SIZE(zynqmp_apu_regs_info),
+ s->regs_info, s->regs,
+ &zynqmp_apu_ops,
+ XILINX_ZYNQMP_APU_ERR_DEBUG,
+ APU_R_MAX * 4);
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->reg_array->mem);
+ sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq_imr);
+
+ for (i = 0; i < APU_MAX_CPU; ++i) {
+ g_autofree gchar *prop_name = g_strdup_printf("cpu%d", i);
+ object_property_add_link(obj, prop_name, TYPE_ARM_CPU,
+ (Object **)&s->cpus[i],
+ qdev_prop_allow_set_link_before_realize,
+ OBJ_PROP_LINK_STRONG);
+ }
+
+ /* wfi_out is used to connect to PMU GPIs. */
+ qdev_init_gpio_out_named(DEVICE(obj), s->wfi_out, "wfi_out", 4);
+ /* CPU_POWER_STATUS is used to connect to INTC redirect. */
+ qdev_init_gpio_out_named(DEVICE(obj), s->cpu_power_status,
+ "CPU_POWER_STATUS", 4);
+ /* wfi_in is used as input from CPUs as wfi request. */
+ qdev_init_gpio_in_named(DEVICE(obj), zynqmp_apu_handle_wfi, "wfi_in", 4);
+}
+
+static void zynqmp_apu_finalize(Object *obj)
+{
+ XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(obj);
+ register_finalize_block(s->reg_array);
+}
+
+static const VMStateDescription vmstate_zynqmp_apu = {
+ .name = TYPE_XLNX_ZYNQMP_APU_CTRL,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPAPUCtrl, APU_R_MAX),
+ VMSTATE_END_OF_LIST(),
+ }
+};
+
+static void zynqmp_apu_class_init(ObjectClass *klass, void *data)
+{
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->vmsd = &vmstate_zynqmp_apu;
+
+ rc->phases.enter = zynqmp_apu_reset_enter;
+ rc->phases.hold = zynqmp_apu_reset_hold;
+}
+
+static const TypeInfo zynqmp_apu_info = {
+ .name = TYPE_XLNX_ZYNQMP_APU_CTRL,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(XlnxZynqMPAPUCtrl),
+ .class_init = zynqmp_apu_class_init,
+ .instance_init = zynqmp_apu_init,
+ .instance_finalize = zynqmp_apu_finalize,
+};
+
+static void zynqmp_apu_register_types(void)
+{
+ type_register_static(&zynqmp_apu_info);
+}
+
+type_init(zynqmp_apu_register_types)
diff --git a/hw/misc/xlnx-zynqmp-crf.c b/hw/misc/xlnx-zynqmp-crf.c
new file mode 100644
index 0000000..57bc8cf
--- /dev/null
+++ b/hw/misc/xlnx-zynqmp-crf.c
@@ -0,0 +1,266 @@
+/*
+ * QEMU model of the CRF - Clock Reset FPD.
+ *
+ * Copyright (c) 2022 Xilinx Inc.
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+ */
+
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+#include "hw/register.h"
+#include "qemu/bitops.h"
+#include "qemu/log.h"
+#include "migration/vmstate.h"
+#include "hw/irq.h"
+#include "hw/misc/xlnx-zynqmp-crf.h"
+#include "target/arm/arm-powerctl.h"
+
+#ifndef XLNX_ZYNQMP_CRF_ERR_DEBUG
+#define XLNX_ZYNQMP_CRF_ERR_DEBUG 0
+#endif
+
+#define CRF_MAX_CPU 4
+
+static void ir_update_irq(XlnxZynqMPCRF *s)
+{
+ bool pending = s->regs[R_IR_STATUS] & ~s->regs[R_IR_MASK];
+ qemu_set_irq(s->irq_ir, pending);
+}
+
+static void ir_status_postw(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(reg->opaque);
+ ir_update_irq(s);
+}
+
+static uint64_t ir_enable_prew(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(reg->opaque);
+ uint32_t val = val64;
+
+ s->regs[R_IR_MASK] &= ~val;
+ ir_update_irq(s);
+ return 0;
+}
+
+static uint64_t ir_disable_prew(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(reg->opaque);
+ uint32_t val = val64;
+
+ s->regs[R_IR_MASK] |= val;
+ ir_update_irq(s);
+ return 0;
+}
+
+static uint64_t rst_fpd_apu_prew(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(reg->opaque);
+ uint32_t val = val64;
+ uint32_t val_old = s->regs[R_RST_FPD_APU];
+ unsigned int i;
+
+ for (i = 0; i < CRF_MAX_CPU; i++) {
+ uint32_t mask = (1 << (R_RST_FPD_APU_ACPU0_RESET_SHIFT + i));
+
+ if ((val ^ val_old) & mask) {
+ if (val & mask) {
+ arm_set_cpu_off(i);
+ } else {
+ arm_set_cpu_on_and_reset(i);
+ }
+ }
+ }
+ return val64;
+}
+
+static const RegisterAccessInfo crf_regs_info[] = {
+ { .name = "ERR_CTRL", .addr = A_ERR_CTRL,
+ },{ .name = "IR_STATUS", .addr = A_IR_STATUS,
+ .w1c = 0x1,
+ .post_write = ir_status_postw,
+ },{ .name = "IR_MASK", .addr = A_IR_MASK,
+ .reset = 0x1,
+ .ro = 0x1,
+ },{ .name = "IR_ENABLE", .addr = A_IR_ENABLE,
+ .pre_write = ir_enable_prew,
+ },{ .name = "IR_DISABLE", .addr = A_IR_DISABLE,
+ .pre_write = ir_disable_prew,
+ },{ .name = "CRF_WPROT", .addr = A_CRF_WPROT,
+ },{ .name = "APLL_CTRL", .addr = A_APLL_CTRL,
+ .reset = 0x12c09,
+ .rsvd = 0xf88c80f6,
+ },{ .name = "APLL_CFG", .addr = A_APLL_CFG,
+ .rsvd = 0x1801210,
+ },{ .name = "APLL_FRAC_CFG", .addr = A_APLL_FRAC_CFG,
+ .rsvd = 0x7e330000,
+ },{ .name = "DPLL_CTRL", .addr = A_DPLL_CTRL,
+ .reset = 0x2c09,
+ .rsvd = 0xf88c80f6,
+ },{ .name = "DPLL_CFG", .addr = A_DPLL_CFG,
+ .rsvd = 0x1801210,
+ },{ .name = "DPLL_FRAC_CFG", .addr = A_DPLL_FRAC_CFG,
+ .rsvd = 0x7e330000,
+ },{ .name = "VPLL_CTRL", .addr = A_VPLL_CTRL,
+ .reset = 0x12809,
+ .rsvd = 0xf88c80f6,
+ },{ .name = "VPLL_CFG", .addr = A_VPLL_CFG,
+ .rsvd = 0x1801210,
+ },{ .name = "VPLL_FRAC_CFG", .addr = A_VPLL_FRAC_CFG,
+ .rsvd = 0x7e330000,
+ },{ .name = "PLL_STATUS", .addr = A_PLL_STATUS,
+ .reset = 0x3f,
+ .rsvd = 0xc0,
+ .ro = 0x3f,
+ },{ .name = "APLL_TO_LPD_CTRL", .addr = A_APLL_TO_LPD_CTRL,
+ .reset = 0x400,
+ .rsvd = 0xc0ff,
+ },{ .name = "DPLL_TO_LPD_CTRL", .addr = A_DPLL_TO_LPD_CTRL,
+ .reset = 0x400,
+ .rsvd = 0xc0ff,
+ },{ .name = "VPLL_TO_LPD_CTRL", .addr = A_VPLL_TO_LPD_CTRL,
+ .reset = 0x400,
+ .rsvd = 0xc0ff,
+ },{ .name = "ACPU_CTRL", .addr = A_ACPU_CTRL,
+ .reset = 0x3000400,
+ .rsvd = 0xfcffc0f8,
+ },{ .name = "DBG_TRACE_CTRL", .addr = A_DBG_TRACE_CTRL,
+ .reset = 0x2500,
+ .rsvd = 0xfeffc0f8,
+ },{ .name = "DBG_FPD_CTRL", .addr = A_DBG_FPD_CTRL,
+ .reset = 0x1002500,
+ .rsvd = 0xfeffc0f8,
+ },{ .name = "DP_VIDEO_REF_CTRL", .addr = A_DP_VIDEO_REF_CTRL,
+ .reset = 0x1002300,
+ .rsvd = 0xfec0c0f8,
+ },{ .name = "DP_AUDIO_REF_CTRL", .addr = A_DP_AUDIO_REF_CTRL,
+ .reset = 0x1032300,
+ .rsvd = 0xfec0c0f8,
+ },{ .name = "DP_STC_REF_CTRL", .addr = A_DP_STC_REF_CTRL,
+ .reset = 0x1203200,
+ .rsvd = 0xfec0c0f8,
+ },{ .name = "DDR_CTRL", .addr = A_DDR_CTRL,
+ .reset = 0x1000500,
+ .rsvd = 0xfeffc0f8,
+ },{ .name = "GPU_REF_CTRL", .addr = A_GPU_REF_CTRL,
+ .reset = 0x1500,
+ .rsvd = 0xf8ffc0f8,
+ },{ .name = "SATA_REF_CTRL", .addr = A_SATA_REF_CTRL,
+ .reset = 0x1001600,
+ .rsvd = 0xfeffc0f8,
+ },{ .name = "PCIE_REF_CTRL", .addr = A_PCIE_REF_CTRL,
+ .reset = 0x1500,
+ .rsvd = 0xfeffc0f8,
+ },{ .name = "GDMA_REF_CTRL", .addr = A_GDMA_REF_CTRL,
+ .reset = 0x1000500,
+ .rsvd = 0xfeffc0f8,
+ },{ .name = "DPDMA_REF_CTRL", .addr = A_DPDMA_REF_CTRL,
+ .reset = 0x1000500,
+ .rsvd = 0xfeffc0f8,
+ },{ .name = "TOPSW_MAIN_CTRL", .addr = A_TOPSW_MAIN_CTRL,
+ .reset = 0x1000400,
+ .rsvd = 0xfeffc0f8,
+ },{ .name = "TOPSW_LSBUS_CTRL", .addr = A_TOPSW_LSBUS_CTRL,
+ .reset = 0x1000800,
+ .rsvd = 0xfeffc0f8,
+ },{ .name = "DBG_TSTMP_CTRL", .addr = A_DBG_TSTMP_CTRL,
+ .reset = 0xa00,
+ .rsvd = 0xffffc0f8,
+ },
+ { .name = "RST_FPD_TOP", .addr = A_RST_FPD_TOP,
+ .reset = 0xf9ffe,
+ .rsvd = 0xf06001,
+ },{ .name = "RST_FPD_APU", .addr = A_RST_FPD_APU,
+ .reset = 0x3d0f,
+ .rsvd = 0xc2f0,
+ .pre_write = rst_fpd_apu_prew,
+ },{ .name = "RST_DDR_SS", .addr = A_RST_DDR_SS,
+ .reset = 0xf,
+ .rsvd = 0xf3,
+ }
+};
+
+static void crf_reset_enter(Object *obj, ResetType type)
+{
+ XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(obj);
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
+ register_reset(&s->regs_info[i]);
+ }
+}
+
+static void crf_reset_hold(Object *obj)
+{
+ XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(obj);
+ ir_update_irq(s);
+}
+
+static const MemoryRegionOps crf_ops = {
+ .read = register_read_memory,
+ .write = register_write_memory,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+};
+
+static void crf_init(Object *obj)
+{
+ XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(obj);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+
+ s->reg_array =
+ register_init_block32(DEVICE(obj), crf_regs_info,
+ ARRAY_SIZE(crf_regs_info),
+ s->regs_info, s->regs,
+ &crf_ops,
+ XLNX_ZYNQMP_CRF_ERR_DEBUG,
+ CRF_R_MAX * 4);
+ sysbus_init_mmio(sbd, &s->reg_array->mem);
+ sysbus_init_irq(sbd, &s->irq_ir);
+}
+
+static void crf_finalize(Object *obj)
+{
+ XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(obj);
+ register_finalize_block(s->reg_array);
+}
+
+static const VMStateDescription vmstate_crf = {
+ .name = TYPE_XLNX_ZYNQMP_CRF,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPCRF, CRF_R_MAX),
+ VMSTATE_END_OF_LIST(),
+ }
+};
+
+static void crf_class_init(ObjectClass *klass, void *data)
+{
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->vmsd = &vmstate_crf;
+ rc->phases.enter = crf_reset_enter;
+ rc->phases.hold = crf_reset_hold;
+}
+
+static const TypeInfo crf_info = {
+ .name = TYPE_XLNX_ZYNQMP_CRF,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(XlnxZynqMPCRF),
+ .class_init = crf_class_init,
+ .instance_init = crf_init,
+ .instance_finalize = crf_finalize,
+};
+
+static void crf_register_types(void)
+{
+ type_register_static(&crf_info);
+}
+
+type_init(crf_register_types)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index 5cb1232..dae9119 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -1697,7 +1697,7 @@
{ 0x0902, "Mouse", "mouse"},
{ 0x0A00, "Dock station", "dock", 0x00ff},
{ 0x0B00, "i386 cpu", "cpu", 0x00ff},
- { 0x0c00, "Fireware contorller", "fireware"},
+ { 0x0c00, "Firewire controller", "firewire"},
{ 0x0c01, "Access bus controller", "access-bus"},
{ 0x0c02, "SSA controller", "ssa"},
{ 0x0c03, "USB controller", "usb"},
diff --git a/hw/virtio/virtio-balloon.c b/hw/virtio/virtio-balloon.c
index e6c1b0a..163d244 100644
--- a/hw/virtio/virtio-balloon.c
+++ b/hw/virtio/virtio-balloon.c
@@ -242,7 +242,7 @@
void *opaque, Error **errp)
{
Error *err = NULL;
- VirtIOBalloon *s = opaque;
+ VirtIOBalloon *s = VIRTIO_BALLOON(obj);
int i;
if (!visit_start_struct(v, name, NULL, 0, &err)) {
@@ -277,7 +277,7 @@
const char *name, void *opaque,
Error **errp)
{
- VirtIOBalloon *s = opaque;
+ VirtIOBalloon *s = VIRTIO_BALLOON(obj);
visit_type_int(v, name, &s->stats_poll_interval, errp);
}
@@ -285,7 +285,7 @@
const char *name, void *opaque,
Error **errp)
{
- VirtIOBalloon *s = opaque;
+ VirtIOBalloon *s = VIRTIO_BALLOON(obj);
int64_t value;
if (!visit_type_int(v, name, &value, errp)) {
@@ -1015,12 +1015,12 @@
s->free_page_hint_notify.notify = virtio_balloon_free_page_hint_notify;
object_property_add(obj, "guest-stats", "guest statistics",
- balloon_stats_get_all, NULL, NULL, s);
+ balloon_stats_get_all, NULL, NULL, NULL);
object_property_add(obj, "guest-stats-polling-interval", "int",
balloon_stats_get_poll_interval,
balloon_stats_set_poll_interval,
- NULL, s);
+ NULL, NULL);
}
static const VMStateDescription vmstate_virtio_balloon = {
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
index 9424f81..9d9a9d0 100644
--- a/include/hw/arm/xlnx-zynqmp.h
+++ b/include/hw/arm/xlnx-zynqmp.h
@@ -39,6 +39,8 @@
#include "hw/nvram/xlnx-bbram.h"
#include "hw/nvram/xlnx-zynqmp-efuse.h"
#include "hw/or-irq.h"
+#include "hw/misc/xlnx-zynqmp-apu-ctrl.h"
+#include "hw/misc/xlnx-zynqmp-crf.h"
#define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
@@ -124,6 +126,8 @@
XlnxZDMA adma[XLNX_ZYNQMP_NUM_ADMA_CH];
XlnxCSUDMA qspi_dma;
qemu_or_irq qspi_irq_orgate;
+ XlnxZynqMPAPUCtrl apu_ctrl;
+ XlnxZynqMPCRF crf;
char *boot_cpu;
ARMCPU *boot_cpu_ptr;
diff --git a/include/hw/misc/xlnx-zynqmp-apu-ctrl.h b/include/hw/misc/xlnx-zynqmp-apu-ctrl.h
new file mode 100644
index 0000000..b8ca943
--- /dev/null
+++ b/include/hw/misc/xlnx-zynqmp-apu-ctrl.h
@@ -0,0 +1,93 @@
+/*
+ * QEMU model of ZynqMP APU Control.
+ *
+ * Copyright (c) 2013-2022 Xilinx Inc
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> and
+ * Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+ *
+ */
+#ifndef HW_MISC_XLNX_ZYNQMP_APU_CTRL_H
+#define HW_MISC_XLNX_ZYNQMP_APU_CTRL_H
+
+#include "hw/sysbus.h"
+#include "hw/register.h"
+#include "target/arm/cpu.h"
+
+#define TYPE_XLNX_ZYNQMP_APU_CTRL "xlnx.apu-ctrl"
+OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPAPUCtrl, XLNX_ZYNQMP_APU_CTRL)
+
+REG32(APU_ERR_CTRL, 0x0)
+ FIELD(APU_ERR_CTRL, PSLVERR, 0, 1)
+REG32(ISR, 0x10)
+ FIELD(ISR, INV_APB, 0, 1)
+REG32(IMR, 0x14)
+ FIELD(IMR, INV_APB, 0, 1)
+REG32(IEN, 0x18)
+ FIELD(IEN, INV_APB, 0, 1)
+REG32(IDS, 0x1c)
+ FIELD(IDS, INV_APB, 0, 1)
+REG32(CONFIG_0, 0x20)
+ FIELD(CONFIG_0, CFGTE, 24, 4)
+ FIELD(CONFIG_0, CFGEND, 16, 4)
+ FIELD(CONFIG_0, VINITHI, 8, 4)
+ FIELD(CONFIG_0, AA64NAA32, 0, 4)
+REG32(CONFIG_1, 0x24)
+ FIELD(CONFIG_1, L2RSTDISABLE, 29, 1)
+ FIELD(CONFIG_1, L1RSTDISABLE, 28, 1)
+ FIELD(CONFIG_1, CP15DISABLE, 0, 4)
+REG32(RVBARADDR0L, 0x40)
+ FIELD(RVBARADDR0L, ADDR, 2, 30)
+REG32(RVBARADDR0H, 0x44)
+ FIELD(RVBARADDR0H, ADDR, 0, 8)
+REG32(RVBARADDR1L, 0x48)
+ FIELD(RVBARADDR1L, ADDR, 2, 30)
+REG32(RVBARADDR1H, 0x4c)
+ FIELD(RVBARADDR1H, ADDR, 0, 8)
+REG32(RVBARADDR2L, 0x50)
+ FIELD(RVBARADDR2L, ADDR, 2, 30)
+REG32(RVBARADDR2H, 0x54)
+ FIELD(RVBARADDR2H, ADDR, 0, 8)
+REG32(RVBARADDR3L, 0x58)
+ FIELD(RVBARADDR3L, ADDR, 2, 30)
+REG32(RVBARADDR3H, 0x5c)
+ FIELD(RVBARADDR3H, ADDR, 0, 8)
+REG32(ACE_CTRL, 0x60)
+ FIELD(ACE_CTRL, AWQOS, 16, 4)
+ FIELD(ACE_CTRL, ARQOS, 0, 4)
+REG32(SNOOP_CTRL, 0x80)
+ FIELD(SNOOP_CTRL, ACE_INACT, 4, 1)
+ FIELD(SNOOP_CTRL, ACP_INACT, 0, 1)
+REG32(PWRCTL, 0x90)
+ FIELD(PWRCTL, CLREXMONREQ, 17, 1)
+ FIELD(PWRCTL, L2FLUSHREQ, 16, 1)
+ FIELD(PWRCTL, CPUPWRDWNREQ, 0, 4)
+REG32(PWRSTAT, 0x94)
+ FIELD(PWRSTAT, CLREXMONACK, 17, 1)
+ FIELD(PWRSTAT, L2FLUSHDONE, 16, 1)
+ FIELD(PWRSTAT, DBGNOPWRDWN, 0, 4)
+
+#define APU_R_MAX ((R_PWRSTAT) + 1)
+
+#define APU_MAX_CPU 4
+
+struct XlnxZynqMPAPUCtrl {
+ SysBusDevice busdev;
+
+ ARMCPU *cpus[APU_MAX_CPU];
+ /* WFIs towards PMU. */
+ qemu_irq wfi_out[4];
+ /* CPU Power status towards INTC Redirect. */
+ qemu_irq cpu_power_status[4];
+ qemu_irq irq_imr;
+
+ uint8_t cpu_pwrdwn_req;
+ uint8_t cpu_in_wfi;
+
+ RegisterInfoArray *reg_array;
+ uint32_t regs[APU_R_MAX];
+ RegisterInfo regs_info[APU_R_MAX];
+};
+
+#endif
diff --git a/include/hw/misc/xlnx-zynqmp-crf.h b/include/hw/misc/xlnx-zynqmp-crf.h
new file mode 100644
index 0000000..02ef0bd
--- /dev/null
+++ b/include/hw/misc/xlnx-zynqmp-crf.h
@@ -0,0 +1,211 @@
+/*
+ * QEMU model of the CRF - Clock Reset FPD.
+ *
+ * Copyright (c) 2022 Xilinx Inc.
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+ */
+#ifndef HW_MISC_XLNX_ZYNQMP_CRF_H
+#define HW_MISC_XLNX_ZYNQMP_CRF_H
+
+#include "hw/sysbus.h"
+#include "hw/register.h"
+
+#define TYPE_XLNX_ZYNQMP_CRF "xlnx.zynqmp_crf"
+OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPCRF, XLNX_ZYNQMP_CRF)
+
+REG32(ERR_CTRL, 0x0)
+ FIELD(ERR_CTRL, SLVERR_ENABLE, 0, 1)
+REG32(IR_STATUS, 0x4)
+ FIELD(IR_STATUS, ADDR_DECODE_ERR, 0, 1)
+REG32(IR_MASK, 0x8)
+ FIELD(IR_MASK, ADDR_DECODE_ERR, 0, 1)
+REG32(IR_ENABLE, 0xc)
+ FIELD(IR_ENABLE, ADDR_DECODE_ERR, 0, 1)
+REG32(IR_DISABLE, 0x10)
+ FIELD(IR_DISABLE, ADDR_DECODE_ERR, 0, 1)
+REG32(CRF_WPROT, 0x1c)
+ FIELD(CRF_WPROT, ACTIVE, 0, 1)
+REG32(APLL_CTRL, 0x20)
+ FIELD(APLL_CTRL, POST_SRC, 24, 3)
+ FIELD(APLL_CTRL, PRE_SRC, 20, 3)
+ FIELD(APLL_CTRL, CLKOUTDIV, 17, 1)
+ FIELD(APLL_CTRL, DIV2, 16, 1)
+ FIELD(APLL_CTRL, FBDIV, 8, 7)
+ FIELD(APLL_CTRL, BYPASS, 3, 1)
+ FIELD(APLL_CTRL, RESET, 0, 1)
+REG32(APLL_CFG, 0x24)
+ FIELD(APLL_CFG, LOCK_DLY, 25, 7)
+ FIELD(APLL_CFG, LOCK_CNT, 13, 10)
+ FIELD(APLL_CFG, LFHF, 10, 2)
+ FIELD(APLL_CFG, CP, 5, 4)
+ FIELD(APLL_CFG, RES, 0, 4)
+REG32(APLL_FRAC_CFG, 0x28)
+ FIELD(APLL_FRAC_CFG, ENABLED, 31, 1)
+ FIELD(APLL_FRAC_CFG, SEED, 22, 3)
+ FIELD(APLL_FRAC_CFG, ALGRTHM, 19, 1)
+ FIELD(APLL_FRAC_CFG, ORDER, 18, 1)
+ FIELD(APLL_FRAC_CFG, DATA, 0, 16)
+REG32(DPLL_CTRL, 0x2c)
+ FIELD(DPLL_CTRL, POST_SRC, 24, 3)
+ FIELD(DPLL_CTRL, PRE_SRC, 20, 3)
+ FIELD(DPLL_CTRL, CLKOUTDIV, 17, 1)
+ FIELD(DPLL_CTRL, DIV2, 16, 1)
+ FIELD(DPLL_CTRL, FBDIV, 8, 7)
+ FIELD(DPLL_CTRL, BYPASS, 3, 1)
+ FIELD(DPLL_CTRL, RESET, 0, 1)
+REG32(DPLL_CFG, 0x30)
+ FIELD(DPLL_CFG, LOCK_DLY, 25, 7)
+ FIELD(DPLL_CFG, LOCK_CNT, 13, 10)
+ FIELD(DPLL_CFG, LFHF, 10, 2)
+ FIELD(DPLL_CFG, CP, 5, 4)
+ FIELD(DPLL_CFG, RES, 0, 4)
+REG32(DPLL_FRAC_CFG, 0x34)
+ FIELD(DPLL_FRAC_CFG, ENABLED, 31, 1)
+ FIELD(DPLL_FRAC_CFG, SEED, 22, 3)
+ FIELD(DPLL_FRAC_CFG, ALGRTHM, 19, 1)
+ FIELD(DPLL_FRAC_CFG, ORDER, 18, 1)
+ FIELD(DPLL_FRAC_CFG, DATA, 0, 16)
+REG32(VPLL_CTRL, 0x38)
+ FIELD(VPLL_CTRL, POST_SRC, 24, 3)
+ FIELD(VPLL_CTRL, PRE_SRC, 20, 3)
+ FIELD(VPLL_CTRL, CLKOUTDIV, 17, 1)
+ FIELD(VPLL_CTRL, DIV2, 16, 1)
+ FIELD(VPLL_CTRL, FBDIV, 8, 7)
+ FIELD(VPLL_CTRL, BYPASS, 3, 1)
+ FIELD(VPLL_CTRL, RESET, 0, 1)
+REG32(VPLL_CFG, 0x3c)
+ FIELD(VPLL_CFG, LOCK_DLY, 25, 7)
+ FIELD(VPLL_CFG, LOCK_CNT, 13, 10)
+ FIELD(VPLL_CFG, LFHF, 10, 2)
+ FIELD(VPLL_CFG, CP, 5, 4)
+ FIELD(VPLL_CFG, RES, 0, 4)
+REG32(VPLL_FRAC_CFG, 0x40)
+ FIELD(VPLL_FRAC_CFG, ENABLED, 31, 1)
+ FIELD(VPLL_FRAC_CFG, SEED, 22, 3)
+ FIELD(VPLL_FRAC_CFG, ALGRTHM, 19, 1)
+ FIELD(VPLL_FRAC_CFG, ORDER, 18, 1)
+ FIELD(VPLL_FRAC_CFG, DATA, 0, 16)
+REG32(PLL_STATUS, 0x44)
+ FIELD(PLL_STATUS, VPLL_STABLE, 5, 1)
+ FIELD(PLL_STATUS, DPLL_STABLE, 4, 1)
+ FIELD(PLL_STATUS, APLL_STABLE, 3, 1)
+ FIELD(PLL_STATUS, VPLL_LOCK, 2, 1)
+ FIELD(PLL_STATUS, DPLL_LOCK, 1, 1)
+ FIELD(PLL_STATUS, APLL_LOCK, 0, 1)
+REG32(APLL_TO_LPD_CTRL, 0x48)
+ FIELD(APLL_TO_LPD_CTRL, DIVISOR0, 8, 6)
+REG32(DPLL_TO_LPD_CTRL, 0x4c)
+ FIELD(DPLL_TO_LPD_CTRL, DIVISOR0, 8, 6)
+REG32(VPLL_TO_LPD_CTRL, 0x50)
+ FIELD(VPLL_TO_LPD_CTRL, DIVISOR0, 8, 6)
+REG32(ACPU_CTRL, 0x60)
+ FIELD(ACPU_CTRL, CLKACT_HALF, 25, 1)
+ FIELD(ACPU_CTRL, CLKACT_FULL, 24, 1)
+ FIELD(ACPU_CTRL, DIVISOR0, 8, 6)
+ FIELD(ACPU_CTRL, SRCSEL, 0, 3)
+REG32(DBG_TRACE_CTRL, 0x64)
+ FIELD(DBG_TRACE_CTRL, CLKACT, 24, 1)
+ FIELD(DBG_TRACE_CTRL, DIVISOR0, 8, 6)
+ FIELD(DBG_TRACE_CTRL, SRCSEL, 0, 3)
+REG32(DBG_FPD_CTRL, 0x68)
+ FIELD(DBG_FPD_CTRL, CLKACT, 24, 1)
+ FIELD(DBG_FPD_CTRL, DIVISOR0, 8, 6)
+ FIELD(DBG_FPD_CTRL, SRCSEL, 0, 3)
+REG32(DP_VIDEO_REF_CTRL, 0x70)
+ FIELD(DP_VIDEO_REF_CTRL, CLKACT, 24, 1)
+ FIELD(DP_VIDEO_REF_CTRL, DIVISOR1, 16, 6)
+ FIELD(DP_VIDEO_REF_CTRL, DIVISOR0, 8, 6)
+ FIELD(DP_VIDEO_REF_CTRL, SRCSEL, 0, 3)
+REG32(DP_AUDIO_REF_CTRL, 0x74)
+ FIELD(DP_AUDIO_REF_CTRL, CLKACT, 24, 1)
+ FIELD(DP_AUDIO_REF_CTRL, DIVISOR1, 16, 6)
+ FIELD(DP_AUDIO_REF_CTRL, DIVISOR0, 8, 6)
+ FIELD(DP_AUDIO_REF_CTRL, SRCSEL, 0, 3)
+REG32(DP_STC_REF_CTRL, 0x7c)
+ FIELD(DP_STC_REF_CTRL, CLKACT, 24, 1)
+ FIELD(DP_STC_REF_CTRL, DIVISOR1, 16, 6)
+ FIELD(DP_STC_REF_CTRL, DIVISOR0, 8, 6)
+ FIELD(DP_STC_REF_CTRL, SRCSEL, 0, 3)
+REG32(DDR_CTRL, 0x80)
+ FIELD(DDR_CTRL, CLKACT, 24, 1)
+ FIELD(DDR_CTRL, DIVISOR0, 8, 6)
+ FIELD(DDR_CTRL, SRCSEL, 0, 3)
+REG32(GPU_REF_CTRL, 0x84)
+ FIELD(GPU_REF_CTRL, PP1_CLKACT, 26, 1)
+ FIELD(GPU_REF_CTRL, PP0_CLKACT, 25, 1)
+ FIELD(GPU_REF_CTRL, CLKACT, 24, 1)
+ FIELD(GPU_REF_CTRL, DIVISOR0, 8, 6)
+ FIELD(GPU_REF_CTRL, SRCSEL, 0, 3)
+REG32(SATA_REF_CTRL, 0xa0)
+ FIELD(SATA_REF_CTRL, CLKACT, 24, 1)
+ FIELD(SATA_REF_CTRL, DIVISOR0, 8, 6)
+ FIELD(SATA_REF_CTRL, SRCSEL, 0, 3)
+REG32(PCIE_REF_CTRL, 0xb4)
+ FIELD(PCIE_REF_CTRL, CLKACT, 24, 1)
+ FIELD(PCIE_REF_CTRL, DIVISOR0, 8, 6)
+ FIELD(PCIE_REF_CTRL, SRCSEL, 0, 3)
+REG32(GDMA_REF_CTRL, 0xb8)
+ FIELD(GDMA_REF_CTRL, CLKACT, 24, 1)
+ FIELD(GDMA_REF_CTRL, DIVISOR0, 8, 6)
+ FIELD(GDMA_REF_CTRL, SRCSEL, 0, 3)
+REG32(DPDMA_REF_CTRL, 0xbc)
+ FIELD(DPDMA_REF_CTRL, CLKACT, 24, 1)
+ FIELD(DPDMA_REF_CTRL, DIVISOR0, 8, 6)
+ FIELD(DPDMA_REF_CTRL, SRCSEL, 0, 3)
+REG32(TOPSW_MAIN_CTRL, 0xc0)
+ FIELD(TOPSW_MAIN_CTRL, CLKACT, 24, 1)
+ FIELD(TOPSW_MAIN_CTRL, DIVISOR0, 8, 6)
+ FIELD(TOPSW_MAIN_CTRL, SRCSEL, 0, 3)
+REG32(TOPSW_LSBUS_CTRL, 0xc4)
+ FIELD(TOPSW_LSBUS_CTRL, CLKACT, 24, 1)
+ FIELD(TOPSW_LSBUS_CTRL, DIVISOR0, 8, 6)
+ FIELD(TOPSW_LSBUS_CTRL, SRCSEL, 0, 3)
+REG32(DBG_TSTMP_CTRL, 0xf8)
+ FIELD(DBG_TSTMP_CTRL, DIVISOR0, 8, 6)
+ FIELD(DBG_TSTMP_CTRL, SRCSEL, 0, 3)
+REG32(RST_FPD_TOP, 0x100)
+ FIELD(RST_FPD_TOP, PCIE_CFG_RESET, 19, 1)
+ FIELD(RST_FPD_TOP, PCIE_BRIDGE_RESET, 18, 1)
+ FIELD(RST_FPD_TOP, PCIE_CTRL_RESET, 17, 1)
+ FIELD(RST_FPD_TOP, DP_RESET, 16, 1)
+ FIELD(RST_FPD_TOP, SWDT_RESET, 15, 1)
+ FIELD(RST_FPD_TOP, AFI_FM5_RESET, 12, 1)
+ FIELD(RST_FPD_TOP, AFI_FM4_RESET, 11, 1)
+ FIELD(RST_FPD_TOP, AFI_FM3_RESET, 10, 1)
+ FIELD(RST_FPD_TOP, AFI_FM2_RESET, 9, 1)
+ FIELD(RST_FPD_TOP, AFI_FM1_RESET, 8, 1)
+ FIELD(RST_FPD_TOP, AFI_FM0_RESET, 7, 1)
+ FIELD(RST_FPD_TOP, GDMA_RESET, 6, 1)
+ FIELD(RST_FPD_TOP, GPU_PP1_RESET, 5, 1)
+ FIELD(RST_FPD_TOP, GPU_PP0_RESET, 4, 1)
+ FIELD(RST_FPD_TOP, GPU_RESET, 3, 1)
+ FIELD(RST_FPD_TOP, GT_RESET, 2, 1)
+ FIELD(RST_FPD_TOP, SATA_RESET, 1, 1)
+REG32(RST_FPD_APU, 0x104)
+ FIELD(RST_FPD_APU, ACPU3_PWRON_RESET, 13, 1)
+ FIELD(RST_FPD_APU, ACPU2_PWRON_RESET, 12, 1)
+ FIELD(RST_FPD_APU, ACPU1_PWRON_RESET, 11, 1)
+ FIELD(RST_FPD_APU, ACPU0_PWRON_RESET, 10, 1)
+ FIELD(RST_FPD_APU, APU_L2_RESET, 8, 1)
+ FIELD(RST_FPD_APU, ACPU3_RESET, 3, 1)
+ FIELD(RST_FPD_APU, ACPU2_RESET, 2, 1)
+ FIELD(RST_FPD_APU, ACPU1_RESET, 1, 1)
+ FIELD(RST_FPD_APU, ACPU0_RESET, 0, 1)
+REG32(RST_DDR_SS, 0x108)
+ FIELD(RST_DDR_SS, DDR_RESET, 3, 1)
+ FIELD(RST_DDR_SS, APM_RESET, 2, 1)
+
+#define CRF_R_MAX (R_RST_DDR_SS + 1)
+
+struct XlnxZynqMPCRF {
+ SysBusDevice parent_obj;
+ MemoryRegion iomem;
+ qemu_irq irq_ir;
+
+ RegisterInfoArray *reg_array;
+ uint32_t regs[CRF_R_MAX];
+ RegisterInfo regs_info[CRF_R_MAX];
+};
+
+#endif
diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h
index 322103a..f2274b2 100644
--- a/include/qemu/osdep.h
+++ b/include/qemu/osdep.h
@@ -400,6 +400,14 @@
#define SIGIO SIGPOLL
#endif
+#ifdef HAVE_MADVISE_WITHOUT_PROTOTYPE
+/*
+ * See MySQL bug #7156 (http://bugs.mysql.com/bug.php?id=7156) for discussion
+ * about Solaris missing the madvise() prototype.
+ */
+extern int madvise(char *, size_t, int);
+#endif
+
#if defined(CONFIG_LINUX)
#ifndef BUS_MCEERR_AR
#define BUS_MCEERR_AR 4
diff --git a/linux-user/include/host/ppc/host-signal.h b/linux-user/include/host/ppc/host-signal.h
deleted file mode 100644
index b80384d..0000000
--- a/linux-user/include/host/ppc/host-signal.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * host-signal.h: signal info dependent on the host architecture
- *
- * Copyright (c) 2003-2005 Fabrice Bellard
- * Copyright (c) 2021 Linaro Limited
- *
- * This work is licensed under the terms of the GNU LGPL, version 2.1 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef PPC_HOST_SIGNAL_H
-#define PPC_HOST_SIGNAL_H
-
-/* The third argument to a SA_SIGINFO handler is ucontext_t. */
-typedef ucontext_t host_sigcontext;
-
-static inline uintptr_t host_signal_pc(host_sigcontext *uc)
-{
- return uc->uc_mcontext.regs->nip;
-}
-
-static inline void host_signal_set_pc(host_sigcontext *uc, uintptr_t pc)
-{
- uc->uc_mcontext.regs->nip = pc;
-}
-
-static inline void *host_signal_mask(host_sigcontext *uc)
-{
- return &uc->uc_sigmask;
-}
-
-static inline bool host_signal_write(siginfo_t *info, host_sigcontext *uc)
-{
- return uc->uc_mcontext.regs->trap != 0x400
- && (uc->uc_mcontext.regs->dsisr & 0x02000000);
-}
-
-#endif
diff --git a/linux-user/include/host/ppc64/host-signal.h b/linux-user/include/host/ppc64/host-signal.h
index a353c22..c4ea866 100644
--- a/linux-user/include/host/ppc64/host-signal.h
+++ b/linux-user/include/host/ppc64/host-signal.h
@@ -1 +1,41 @@
-#include "../ppc/host-signal.h"
+/*
+ * host-signal.h: signal info dependent on the host architecture
+ *
+ * Copyright (c) 2003-2005 Fabrice Bellard
+ * Copyright (c) 2021 Linaro Limited
+ *
+ * This work is licensed under the terms of the GNU LGPL, version 2.1 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef PPC_HOST_SIGNAL_H
+#define PPC_HOST_SIGNAL_H
+
+/* Needed for PT_* constants */
+#include <asm/ptrace.h>
+
+/* The third argument to a SA_SIGINFO handler is ucontext_t. */
+typedef ucontext_t host_sigcontext;
+
+static inline uintptr_t host_signal_pc(host_sigcontext *uc)
+{
+ return uc->uc_mcontext.gp_regs[PT_NIP];
+}
+
+static inline void host_signal_set_pc(host_sigcontext *uc, uintptr_t pc)
+{
+ uc->uc_mcontext.gp_regs[PT_NIP] = pc;
+}
+
+static inline void *host_signal_mask(host_sigcontext *uc)
+{
+ return &uc->uc_sigmask;
+}
+
+static inline bool host_signal_write(siginfo_t *info, host_sigcontext *uc)
+{
+ return uc->uc_mcontext.gp_regs[PT_TRAP] != 0x400
+ && (uc->uc_mcontext.gp_regs[PT_DSISR] & 0x02000000);
+}
+
+#endif
diff --git a/meson.build b/meson.build
index bae62ef..282e7c4 100644
--- a/meson.build
+++ b/meson.build
@@ -1715,11 +1715,30 @@
#error Not supported
#endif
}'''))
-config_host_data.set('CONFIG_MADVISE', cc.links(gnu_source_prefix + '''
+
+has_madvise = cc.links(gnu_source_prefix + '''
#include <sys/types.h>
#include <sys/mman.h>
#include <stddef.h>
- int main(void) { return madvise(NULL, 0, MADV_DONTNEED); }'''))
+ int main(void) { return madvise(NULL, 0, MADV_DONTNEED); }''')
+missing_madvise_proto = false
+if has_madvise
+ # Some platforms (illumos and Solaris before Solaris 11) provide madvise()
+ # but forget to prototype it. In this case, has_madvise will be true (the
+ # test program links despite a compile warning). To detect the
+ # missing-prototype case, we try again with a definitely-bogus prototype.
+ # This will only compile if the system headers don't provide the prototype;
+ # otherwise the conflicting prototypes will cause a compiler error.
+ missing_madvise_proto = cc.links(gnu_source_prefix + '''
+ #include <sys/types.h>
+ #include <sys/mman.h>
+ #include <stddef.h>
+ extern int madvise(int);
+ int main(void) { return madvise(0); }''')
+endif
+config_host_data.set('CONFIG_MADVISE', has_madvise)
+config_host_data.set('HAVE_MADVISE_WITHOUT_PROTOTYPE', missing_madvise_proto)
+
config_host_data.set('CONFIG_MEMFD', cc.links(gnu_source_prefix + '''
#include <sys/mman.h>
int main(void) { return memfd_create("foo", MFD_ALLOW_SEALING); }'''))
diff --git a/qemu.nsi b/qemu.nsi
index c3df8c9..564d617 100644
--- a/qemu.nsi
+++ b/qemu.nsi
@@ -35,6 +35,9 @@
!define OUTFILE "qemu-setup.exe"
!endif
+; Build a unicode installer
+Unicode true
+
; Use maximum compression.
SetCompressor /SOLID lzma
@@ -225,10 +228,7 @@
; Descriptions (mouse-over).
!insertmacro MUI_FUNCTION_DESCRIPTION_BEGIN
!insertmacro MUI_DESCRIPTION_TEXT ${SectionSystem} "System emulation."
- !insertmacro MUI_DESCRIPTION_TEXT ${Section_alpha} "Alpha system emulation."
- !insertmacro MUI_DESCRIPTION_TEXT ${Section_alphaw} "Alpha system emulation (GUI)."
- !insertmacro MUI_DESCRIPTION_TEXT ${Section_i386} "PC i386 system emulation."
- !insertmacro MUI_DESCRIPTION_TEXT ${Section_i386w} "PC i386 system emulation (GUI)."
+!include "${BINDIR}\system-mui-text.nsh"
!insertmacro MUI_DESCRIPTION_TEXT ${SectionTools} "Tools."
!ifdef DLLDIR
!insertmacro MUI_DESCRIPTION_TEXT ${SectionDll} "Runtime Libraries (DLL)."
diff --git a/scripts/nsis.py b/scripts/nsis.py
index 5135a05..462d6ca 100644
--- a/scripts/nsis.py
+++ b/scripts/nsis.py
@@ -33,10 +33,12 @@ def main():
subprocess.run(["make", "install", "DESTDIR=" + destdir + os.path.sep])
with open(
os.path.join(destdir + args.prefix, "system-emulations.nsh"), "w"
- ) as nsh:
- for exe in glob.glob(
+ ) as nsh, open(
+ os.path.join(destdir + args.prefix, "system-mui-text.nsh"), "w"
+ ) as muinsh:
+ for exe in sorted(glob.glob(
os.path.join(destdir + args.prefix, "qemu-system-*.exe")
- ):
+ )):
exe = os.path.basename(exe)
arch = exe[12:-4]
nsh.write(
@@ -49,6 +51,15 @@ def main():
arch, exe
)
)
+ if arch.endswith('w'):
+ desc = arch[:-1] + " emulation (GUI)."
+ else:
+ desc = arch + " emulation."
+
+ muinsh.write(
+ """
+ !insertmacro MUI_DESCRIPTION_TEXT ${{Section_{0}}} "{1}"
+ """.format(arch, desc))
for exe in glob.glob(os.path.join(destdir + args.prefix, "*.exe")):
signcode(exe)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 185d4e7..5d4ca7a 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -21,6 +21,7 @@
#include "qemu/osdep.h"
#include "qemu/qemu-print.h"
#include "qemu/timer.h"
+#include "qemu/log.h"
#include "qemu-common.h"
#include "target/arm/idau.h"
#include "qemu/module.h"
@@ -235,7 +236,10 @@
} else {
env->pstate = PSTATE_MODE_EL1h;
}
- env->pc = cpu->rvbar;
+
+ /* Sample rvbar at reset. */
+ env->cp15.rvbar = cpu->rvbar_prop;
+ env->pc = env->cp15.rvbar;
#endif
} else {
#if defined(CONFIG_USER_ONLY)
@@ -366,6 +370,10 @@
initial_pc = ldl_phys(s->as, vecbase + 4);
}
+ qemu_log_mask(CPU_LOG_INT,
+ "Loaded reset SP 0x%x PC 0x%x from vector table\n",
+ initial_msp, initial_pc);
+
env->regs[13] = initial_msp & 0xFFFFFFFC;
env->regs[15] = initial_pc & ~1;
env->thumb = initial_pc & 1;
@@ -1130,9 +1138,6 @@
static Property arm_cpu_reset_hivecs_property =
DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
-static Property arm_cpu_rvbar_property =
- DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
-
#ifndef CONFIG_USER_ONLY
static Property arm_cpu_has_el2_property =
DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true);
@@ -1235,7 +1240,9 @@
}
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
- qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property);
+ object_property_add_uint64_ptr(obj, "rvbar",
+ &cpu->rvbar_prop,
+ OBJ_PROP_FLAG_READWRITE);
}
#ifndef CONFIG_USER_ONLY
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 157f214..23879de 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -447,6 +447,7 @@
uint64_t vbar_el[4];
};
uint32_t mvbar; /* (monitor) vector base address register */
+ uint64_t rvbar; /* rvbar sampled from rvbar property at reset */
struct { /* FCSE PID. */
uint32_t fcseidr_ns;
uint32_t fcseidr_s;
@@ -985,7 +986,7 @@
/* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
uint32_t dcz_blocksize;
- uint64_t rvbar;
+ uint64_t rvbar_prop; /* Property/input signals. */
/* Configurable aspects of GIC cpu interface (which is part of the CPU) */
int gic_num_lrs; /* number of list registers */
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 088956e..812ca59 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7967,7 +7967,8 @@
ARMCPRegInfo rvbar = {
.name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
- .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar
+ .access = PL1_R,
+ .fieldoffset = offsetof(CPUARMState, cp15.rvbar),
};
define_one_arm_cp_reg(cpu, &rvbar);
}
@@ -8011,7 +8012,8 @@
ARMCPRegInfo rvbar = {
.name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1,
- .type = ARM_CP_CONST, .access = PL2_R, .resetvalue = cpu->rvbar
+ .access = PL2_R,
+ .fieldoffset = offsetof(CPUARMState, cp15.rvbar),
};
define_one_arm_cp_reg(cpu, &rvbar);
}
@@ -8048,7 +8050,9 @@
ARMCPRegInfo el3_regs[] = {
{ .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1,
- .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar },
+ .access = PL3_R,
+ .fieldoffset = offsetof(CPUARMState, cp15.rvbar),
+ },
{ .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0,
.access = PL3_RW,
@@ -11706,11 +11710,17 @@
indexmask = indexmask_grainsize;
continue;
}
- /* Block entry at level 1 or 2, or page entry at level 3.
+ /*
+ * Block entry at level 1 or 2, or page entry at level 3.
* These are basically the same thing, although the number
- * of bits we pull in from the vaddr varies.
+ * of bits we pull in from the vaddr varies. Note that although
+ * descaddrmask masks enough of the low bits of the descriptor
+ * to give a correct page or table address, the address field
+ * in a block descriptor is smaller; so we need to explicitly
+ * clear the lower bits here before ORing in the low vaddr bits.
*/
page_size = (1ULL << ((stride * (4 - level)) + 3));
+ descaddr &= ~(page_size - 1);
descaddr |= (address & (page_size - 1));
/* Extract attributes from the descriptor */
attrs = extract64(descriptor, 2, 10)
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index 648a3b3..b7a0fe0 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -679,6 +679,10 @@
ARMMMUIdx mmu_idx;
bool exc_secure;
+ qemu_log_mask(CPU_LOG_INT,
+ "...loading from element %d of %s vector table at 0x%x\n",
+ exc, targets_secure ? "secure" : "non-secure", addr);
+
mmu_idx = arm_v7m_mmu_idx_for_secstate_and_priv(env, targets_secure, true);
/*
@@ -719,6 +723,7 @@
goto load_fail;
}
*pvec = vector_entry;
+ qemu_log_mask(CPU_LOG_INT, "...loaded new PC 0x%x\n", *pvec);
return true;
load_fail:
@@ -2267,7 +2272,13 @@
* Note that for M profile we don't have a guest facing FSR, but
* the env->exception.fsr will be populated by the code that
* raises the fault, in the A profile short-descriptor format.
+ *
+ * Log the exception.vaddress now regardless of subtype, because
+ * logging below only logs it when it goes into a guest visible
+ * register.
*/
+ qemu_log_mask(CPU_LOG_INT, "...at fault address 0x%x\n",
+ (uint32_t)env->exception.vaddress);
switch (env->exception.fsr & 0xf) {
case M_FAKE_FSR_NSC_EXEC:
/*
diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c
index cd6df18..739aa52 100644
--- a/target/arm/pauth_helper.c
+++ b/target/arm/pauth_helper.c
@@ -390,7 +390,7 @@
static void pauth_check_trap(CPUARMState *env, int el, uintptr_t ra)
{
- if (el < 2 && arm_feature(env, ARM_FEATURE_EL2)) {
+ if (el < 2 && arm_is_el2_enabled(env)) {
uint64_t hcr = arm_hcr_el2_eff(env);
bool trap = !(hcr & HCR_API);
if (el == 0) {
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index c60b9f0..0388cce 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -1575,10 +1575,9 @@
### SVE2 Memory Gather Load Group
-# SVE2 64-bit gather non-temporal load
-# (scalar plus unpacked 32-bit unscaled offsets)
+# SVE2 64-bit gather non-temporal load (scalar plus 64-bit unscaled offsets)
LDNT1_zprz 1100010 msz:2 00 rm:5 1 u:1 0 pg:3 rn:5 rd:5 \
- &rprr_gather_load xs=0 esz=3 scale=0 ff=0
+ &rprr_gather_load xs=2 esz=3 scale=0 ff=0
# SVE2 32-bit gather non-temporal load (scalar plus 32-bit unscaled offsets)
LDNT1_zprz 1000010 msz:2 00 rm:5 10 u:1 pg:3 rn:5 rd:5 \
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 33ca1bc..2c23459 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -6487,10 +6487,33 @@
static bool trans_LDNT1_zprz(DisasContext *s, arg_LD1_zprz *a)
{
+ gen_helper_gvec_mem_scatter *fn = NULL;
+ bool be = s->be_data == MO_BE;
+ bool mte = s->mte_active[0];
+
+ if (a->esz < a->msz + !a->u) {
+ return false;
+ }
if (!dc_isar_feature(aa64_sve2, s)) {
return false;
}
- return trans_LD1_zprz(s, a);
+ if (!sve_access_check(s)) {
+ return true;
+ }
+
+ switch (a->esz) {
+ case MO_32:
+ fn = gather_load_fn32[mte][be][0][0][a->u][a->msz];
+ break;
+ case MO_64:
+ fn = gather_load_fn64[mte][be][0][2][a->u][a->msz];
+ break;
+ }
+ assert(fn != NULL);
+
+ do_mem_zpz(s, a->rd, a->pg, a->rn, 0,
+ cpu_reg(s, a->rm), a->msz, false, fn);
+ return true;
}
/* Indexed by [mte][be][xs][msz]. */
@@ -6647,10 +6670,34 @@
static bool trans_STNT1_zprz(DisasContext *s, arg_ST1_zprz *a)
{
+ gen_helper_gvec_mem_scatter *fn;
+ bool be = s->be_data == MO_BE;
+ bool mte = s->mte_active[0];
+
+ if (a->esz < a->msz) {
+ return false;
+ }
if (!dc_isar_feature(aa64_sve2, s)) {
return false;
}
- return trans_ST1_zprz(s, a);
+ if (!sve_access_check(s)) {
+ return true;
+ }
+
+ switch (a->esz) {
+ case MO_32:
+ fn = scatter_store_fn32[mte][be][0][a->msz];
+ break;
+ case MO_64:
+ fn = scatter_store_fn64[mte][be][2][a->msz];
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ do_mem_zpz(s, a->rd, a->pg, a->rn, 0,
+ cpu_reg(s, a->rm), a->msz, true, fn);
+ return true;
}
/*
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index bd12db9..7e8be99 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -2691,11 +2691,35 @@
do_float_check_status(env, GETPC()); \
}
-VSX_CVT_FP_TO_FP(xscvdpsp, 1, float64, float32, VsrD(0), VsrW(0), 1)
VSX_CVT_FP_TO_FP(xscvspdp, 1, float32, float64, VsrW(0), VsrD(0), 1)
-VSX_CVT_FP_TO_FP(xvcvdpsp, 2, float64, float32, VsrD(i), VsrW(2 * i), 0)
VSX_CVT_FP_TO_FP(xvcvspdp, 2, float32, float64, VsrW(2 * i), VsrD(i), 0)
+#define VSX_CVT_FP_TO_FP2(op, nels, stp, ttp, sfprf) \
+void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
+{ \
+ ppc_vsr_t t = { }; \
+ int i; \
+ \
+ for (i = 0; i < nels; i++) { \
+ t.VsrW(2 * i) = stp##_to_##ttp(xb->VsrD(i), &env->fp_status); \
+ if (unlikely(stp##_is_signaling_nan(xb->VsrD(i), \
+ &env->fp_status))) { \
+ float_invalid_op_vxsnan(env, GETPC()); \
+ t.VsrW(2 * i) = ttp##_snan_to_qnan(t.VsrW(2 * i)); \
+ } \
+ if (sfprf) { \
+ helper_compute_fprf_##ttp(env, t.VsrW(2 * i)); \
+ } \
+ t.VsrW(2 * i + 1) = t.VsrW(2 * i); \
+ } \
+ \
+ *xt = t; \
+ do_float_check_status(env, GETPC()); \
+}
+
+VSX_CVT_FP_TO_FP2(xvcvdpsp, 2, float64, float32, 0)
+VSX_CVT_FP_TO_FP2(xscvdpsp, 1, float64, float32, 1)
+
/*
* VSX_CVT_FP_TO_FP_VECTOR - VSX floating point/floating point conversion
* op - instruction mnemonic
@@ -2891,16 +2915,10 @@
VSX_CVT_FP_TO_INT(xscvdpsxds, 1, float64, int64, VsrD(0), VsrD(0), \
0x8000000000000000ULL)
-VSX_CVT_FP_TO_INT(xscvdpsxws, 1, float64, int32, VsrD(0), VsrW(1), \
- 0x80000000U)
VSX_CVT_FP_TO_INT(xscvdpuxds, 1, float64, uint64, VsrD(0), VsrD(0), 0ULL)
-VSX_CVT_FP_TO_INT(xscvdpuxws, 1, float64, uint32, VsrD(0), VsrW(1), 0U)
VSX_CVT_FP_TO_INT(xvcvdpsxds, 2, float64, int64, VsrD(i), VsrD(i), \
0x8000000000000000ULL)
-VSX_CVT_FP_TO_INT(xvcvdpsxws, 2, float64, int32, VsrD(i), VsrW(2 * i), \
- 0x80000000U)
VSX_CVT_FP_TO_INT(xvcvdpuxds, 2, float64, uint64, VsrD(i), VsrD(i), 0ULL)
-VSX_CVT_FP_TO_INT(xvcvdpuxws, 2, float64, uint32, VsrD(i), VsrW(2 * i), 0U)
VSX_CVT_FP_TO_INT(xvcvspsxds, 2, float32, int64, VsrW(2 * i), VsrD(i), \
0x8000000000000000ULL)
VSX_CVT_FP_TO_INT(xvcvspsxws, 4, float32, int32, VsrW(i), VsrW(i), 0x80000000U)
@@ -2908,6 +2926,45 @@
VSX_CVT_FP_TO_INT(xvcvspuxws, 4, float32, uint32, VsrW(i), VsrW(i), 0U)
/*
+ * Likewise, except that the result is duplicated into both subwords.
+ * Power ISA v3.1 has Programming Notes for these insns:
+ * Previous versions of the architecture allowed the contents of
+ * word 0 of the result register to be undefined. However, all
+ * processors that support this instruction write the result into
+ * words 0 and 1 (and words 2 and 3) of the result register, as
+ * is required by this version of the architecture.
+ */
+#define VSX_CVT_FP_TO_INT2(op, nels, stp, ttp, rnan) \
+void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
+{ \
+ int all_flags = env->fp_status.float_exception_flags, flags; \
+ ppc_vsr_t t = { }; \
+ int i; \
+ \
+ for (i = 0; i < nels; i++) { \
+ env->fp_status.float_exception_flags = 0; \
+ t.VsrW(2 * i) = stp##_to_##ttp##_round_to_zero(xb->VsrD(i), \
+ &env->fp_status); \
+ flags = env->fp_status.float_exception_flags; \
+ if (unlikely(flags & float_flag_invalid)) { \
+ t.VsrW(2 * i) = float_invalid_cvt(env, flags, t.VsrW(2 * i), \
+ rnan, 0, GETPC()); \
+ } \
+ t.VsrW(2 * i + 1) = t.VsrW(2 * i); \
+ all_flags |= flags; \
+ } \
+ \
+ *xt = t; \
+ env->fp_status.float_exception_flags = all_flags; \
+ do_float_check_status(env, GETPC()); \
+}
+
+VSX_CVT_FP_TO_INT2(xscvdpsxws, 1, float64, int32, 0x80000000U)
+VSX_CVT_FP_TO_INT2(xscvdpuxws, 1, float64, uint32, 0U)
+VSX_CVT_FP_TO_INT2(xvcvdpsxws, 2, float64, int32, 0x80000000U)
+VSX_CVT_FP_TO_INT2(xvcvdpuxws, 2, float64, uint32, 0U)
+
+/*
* VSX_CVT_FP_TO_INT_VECTOR - VSX floating point to integer conversion
* op - instruction mnemonic
* stp - source type (float32 or float64)
@@ -2980,11 +3037,27 @@
VSX_CVT_INT_TO_FP(xvcvuxddp, 2, uint64, float64, VsrD(i), VsrD(i), 0, 0)
VSX_CVT_INT_TO_FP(xvcvsxwdp, 2, int32, float64, VsrW(2 * i), VsrD(i), 0, 0)
VSX_CVT_INT_TO_FP(xvcvuxwdp, 2, uint64, float64, VsrW(2 * i), VsrD(i), 0, 0)
-VSX_CVT_INT_TO_FP(xvcvsxdsp, 2, int64, float32, VsrD(i), VsrW(2 * i), 0, 0)
-VSX_CVT_INT_TO_FP(xvcvuxdsp, 2, uint64, float32, VsrD(i), VsrW(2 * i), 0, 0)
VSX_CVT_INT_TO_FP(xvcvsxwsp, 4, int32, float32, VsrW(i), VsrW(i), 0, 0)
VSX_CVT_INT_TO_FP(xvcvuxwsp, 4, uint32, float32, VsrW(i), VsrW(i), 0, 0)
+#define VSX_CVT_INT_TO_FP2(op, stp, ttp) \
+void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
+{ \
+ ppc_vsr_t t = { }; \
+ int i; \
+ \
+ for (i = 0; i < 2; i++) { \
+ t.VsrW(2 * i) = stp##_to_##ttp(xb->VsrD(i), &env->fp_status); \
+ t.VsrW(2 * i + 1) = t.VsrW(2 * i); \
+ } \
+ \
+ *xt = t; \
+ do_float_check_status(env, GETPC()); \
+}
+
+VSX_CVT_INT_TO_FP2(xvcvsxdsp, int64, float32)
+VSX_CVT_INT_TO_FP2(xvcvuxdsp, uint64, float32)
+
/*
* VSX_CVT_INT_TO_FP_VECTOR - VSX integer to floating point conversion
* op - instruction mnemonic
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
index ac07acd..f7121cb 100644
--- a/tests/tcg/aarch64/Makefile.target
+++ b/tests/tcg/aarch64/Makefile.target
@@ -86,7 +86,11 @@
EXTRA_RUNS += run-gdbstub-sysregs run-gdbstub-sve-ioctls
endif
+endif
+ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_SVE2),)
+AARCH64_TESTS += test-826
+test-826: CFLAGS+=-march=armv8.1-a+sve2
endif
TESTS += $(AARCH64_TESTS)
diff --git a/tests/tcg/aarch64/test-826.c b/tests/tcg/aarch64/test-826.c
new file mode 100644
index 0000000..f59740a
--- /dev/null
+++ b/tests/tcg/aarch64/test-826.c
@@ -0,0 +1,50 @@
+#include <sys/mman.h>
+#include <unistd.h>
+#include <signal.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <assert.h>
+
+static void *expected;
+
+void sigsegv(int sig, siginfo_t *info, void *vuc)
+{
+ ucontext_t *uc = vuc;
+
+ assert(info->si_addr == expected);
+ uc->uc_mcontext.pc += 4;
+}
+
+int main()
+{
+ struct sigaction sa = {
+ .sa_sigaction = sigsegv,
+ .sa_flags = SA_SIGINFO
+ };
+
+ void *page;
+ long ofs;
+
+ if (sigaction(SIGSEGV, &sa, NULL) < 0) {
+ perror("sigaction");
+ return EXIT_FAILURE;
+ }
+
+ page = mmap(0, getpagesize(), PROT_NONE, MAP_PRIVATE | MAP_ANON, -1, 0);
+ if (page == MAP_FAILED) {
+ perror("mmap");
+ return EXIT_FAILURE;
+ }
+
+ ofs = 0x124;
+ expected = page + ofs;
+
+ asm("ptrue p0.d, vl1\n\t"
+ "dup z0.d, %0\n\t"
+ "ldnt1h {z1.d}, p0/z, [z0.d, %1]\n\t"
+ "dup z1.d, %1\n\t"
+ "ldnt1h {z0.d}, p0/z, [z1.d, %0]"
+ : : "r"(page), "r"(ofs) : "v0", "v1");
+
+ return EXIT_SUCCESS;
+}
diff --git a/tests/tcg/configure.sh b/tests/tcg/configure.sh
index ed4b5cc..84f928f 100755
--- a/tests/tcg/configure.sh
+++ b/tests/tcg/configure.sh
@@ -300,6 +300,10 @@
echo "CROSS_CC_HAS_SVE=y" >> $config_target_mak
fi
if do_compiler "$target_compiler" $target_compiler_cflags \
+ -march=armv8.1-a+sve2 -o $TMPE $TMPC; then
+ echo "CROSS_CC_HAS_SVE2=y" >> $config_target_mak
+ fi
+ if do_compiler "$target_compiler" $target_compiler_cflags \
-march=armv8.3-a -o $TMPE $TMPC; then
echo "CROSS_CC_HAS_ARMV8_3=y" >> $config_target_mak
fi
diff --git a/ui/gtk.c b/ui/gtk.c
index 1b24a67..c57c367 100644
--- a/ui/gtk.c
+++ b/ui/gtk.c
@@ -972,6 +972,10 @@
return TRUE;
}
+ if (button->type == GDK_2BUTTON_PRESS || button->type == GDK_3BUTTON_PRESS) {
+ return TRUE;
+ }
+
qemu_input_queue_btn(vc->gfx.dcl.con, btn,
button->type == GDK_BUTTON_PRESS);
qemu_input_event_sync();
diff --git a/ui/vnc.c b/ui/vnc.c
index 3ccd33d..310a873 100644
--- a/ui/vnc.c
+++ b/ui/vnc.c
@@ -3098,6 +3098,9 @@
VncState *vs;
int has_dirty = 0;
pixman_image_t *tmpbuf = NULL;
+ unsigned long offset;
+ int x;
+ uint8_t *guest_ptr, *server_ptr;
struct timeval tv = { 0, 0 };
@@ -3106,6 +3109,13 @@
has_dirty = vnc_update_stats(vd, &tv);
}
+ offset = find_next_bit((unsigned long *) &vd->guest.dirty,
+ height * VNC_DIRTY_BPL(&vd->guest), 0);
+ if (offset == height * VNC_DIRTY_BPL(&vd->guest)) {
+ /* no dirty bits in guest surface */
+ return has_dirty;
+ }
+
/*
* Walk through the guest dirty map.
* Check and copy modified bits from guest to server surface.
@@ -3130,15 +3140,6 @@
line_bytes = MIN(server_stride, guest_ll);
for (;;) {
- int x;
- uint8_t *guest_ptr, *server_ptr;
- unsigned long offset = find_next_bit((unsigned long *) &vd->guest.dirty,
- height * VNC_DIRTY_BPL(&vd->guest),
- y * VNC_DIRTY_BPL(&vd->guest));
- if (offset == height * VNC_DIRTY_BPL(&vd->guest)) {
- /* no more dirty bits */
- break;
- }
y = offset / VNC_DIRTY_BPL(&vd->guest);
x = offset % VNC_DIRTY_BPL(&vd->guest);
@@ -3177,6 +3178,13 @@
}
y++;
+ offset = find_next_bit((unsigned long *) &vd->guest.dirty,
+ height * VNC_DIRTY_BPL(&vd->guest),
+ y * VNC_DIRTY_BPL(&vd->guest));
+ if (offset == height * VNC_DIRTY_BPL(&vd->guest)) {
+ /* no more dirty bits */
+ break;
+ }
}
qemu_pixman_image_unref(tmpbuf);
return has_dirty;
diff --git a/util/osdep.c b/util/osdep.c
index 7c4deda..394804d 100644
--- a/util/osdep.c
+++ b/util/osdep.c
@@ -23,16 +23,6 @@
*/
#include "qemu/osdep.h"
#include "qapi/error.h"
-
-/* Needed early for CONFIG_BSD etc. */
-
-#ifdef CONFIG_SOLARIS
-#include <sys/statvfs.h>
-/* See MySQL bug #7156 (http://bugs.mysql.com/bug.php?id=7156) for
- discussion about Solaris header problems */
-extern int madvise(char *, size_t, int);
-#endif
-
#include "qemu-common.h"
#include "qemu/cutils.h"
#include "qemu/sockets.h"
