target/ppc: Add PPR32 SPR
PPR32 provides access to the upper half of PPR.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 2532408..141cbef 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2120,6 +2120,7 @@
#define SPR_POWER_MMCRS (0x37E)
#define SPR_WORT (0x37F)
#define SPR_PPR (0x380)
+#define SPR_PPR32 (0x382)
#define SPR_750_GQR0 (0x390)
#define SPR_440_DNV0 (0x390)
#define SPR_750_GQR1 (0x391)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 927721d..6baf755 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -5606,6 +5606,14 @@
0x00000000);
}
+static void register_power7_common_sprs(CPUPPCState *env)
+{
+ spr_register(env, SPR_PPR32, "PPR32",
+ &spr_read_ppr32, &spr_write_ppr32,
+ &spr_read_ppr32, &spr_write_ppr32,
+ 0x00000000);
+}
+
static void register_power8_tce_address_control_sprs(CPUPPCState *env)
{
spr_register_kvm(env, SPR_TAR, "TAR",
@@ -6101,6 +6109,7 @@
register_power6_common_sprs(env);
register_HEIR32_spr(env);
register_power6_dbg_sprs(env);
+ register_power7_common_sprs(env);
register_power7_book4_sprs(env);
/* env variables */
@@ -6247,6 +6256,7 @@
register_power6_common_sprs(env);
register_HEIR32_spr(env);
register_power6_dbg_sprs(env);
+ register_power7_common_sprs(env);
register_power8_tce_address_control_sprs(env);
register_power8_ids_sprs(env);
register_power8_ebb_sprs(env);
@@ -6414,6 +6424,7 @@
register_power6_common_sprs(env);
register_HEIR32_spr(env);
register_power6_dbg_sprs(env);
+ register_power7_common_sprs(env);
register_power8_tce_address_control_sprs(env);
register_power8_ids_sprs(env);
register_power8_ebb_sprs(env);
@@ -6608,6 +6619,7 @@
register_power6_common_sprs(env);
register_HEIR64_spr(env);
register_power6_dbg_sprs(env);
+ register_power7_common_sprs(env);
register_power8_tce_address_control_sprs(env);
register_power8_ids_sprs(env);
register_power8_ebb_sprs(env);
diff --git a/target/ppc/spr_common.h b/target/ppc/spr_common.h
index eb2561f..9e40b3b 100644
--- a/target/ppc/spr_common.h
+++ b/target/ppc/spr_common.h
@@ -203,6 +203,8 @@
void spr_write_tfmr(DisasContext *ctx, int sprn, int gprn);
void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn);
void spr_read_dexcr_ureg(DisasContext *ctx, int gprn, int sprn);
+void spr_read_ppr32(DisasContext *ctx, int sprn, int gprn);
+void spr_write_ppr32(DisasContext *ctx, int sprn, int gprn);
#endif
void register_low_BATs(CPUPPCState *env);
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index cf42dfc..fb05047 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -1352,6 +1352,30 @@
gen_load_spr(t0, sprn + 16);
tcg_gen_ext32u_tl(cpu_gpr[gprn], t0);
}
+
+/* The PPR32 SPR accesses the upper 32-bits of PPR */
+void spr_read_ppr32(DisasContext *ctx, int gprn, int sprn)
+{
+ gen_load_spr(cpu_gpr[gprn], SPR_PPR);
+ tcg_gen_shri_tl(cpu_gpr[gprn], cpu_gpr[gprn], 32);
+ spr_load_dump_spr(SPR_PPR);
+}
+
+void spr_write_ppr32(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv t0 = tcg_temp_new();
+
+ /*
+ * Don't clobber the low 32-bits of the PPR. These are all reserved bits
+ * but TCG does implement them, so it would be surprising to zero them
+ * here. "Priority nops" are similarly careful not to clobber reserved
+ * bits.
+ */
+ gen_load_spr(t0, SPR_PPR);
+ tcg_gen_deposit_tl(t0, t0, cpu_gpr[gprn], 32, 32);
+ gen_store_spr(SPR_PPR, t0);
+ spr_store_dump_spr(SPR_PPR);
+}
#endif
#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
