qemu /
qemu /
1addf57177a5646f86ede4eee385932b0214ab72 target/riscv: Add RISC-V CSR qtest support
The RISC-V architecture supports the creation of custom
CSR-mapped devices. It would be convenient to test them in the same way
as MMIO-mapped devices. To do this, a new call has been added
to read/write CSR registers.
Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com>
Acked-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
3 files changed
