commit | 73c260c1a63cabe81676a28e957df10ea2395443 | [log] [tgz] |
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author | Siarhei Volkau <lis8215@gmail.com> | Thu Jun 08 13:41:52 2023 +0300 |
committer | Philippe Mathieu-Daudé <philmd@linaro.org> | Mon Jul 10 23:33:38 2023 +0200 |
tree | fb2ff4420f9d3d9bdb4d7521fa252ad67e0921fb | |
parent | 1980fa0a58ec8deada197e399a1c3c3b78c39e09 [diff] |
target/mips/mxu: Add LXW LXB LXH LXBU LXHU instructions These instructions used to load from memory to GPR via indexed address divided by base and index parts in GPR registers. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-4-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>