tree e2b4691002a2a8834973ab9adf79d8d08bcf708e
parent ea3f0ebc1a3ba380e682ea8aad38f8e8cbc0d6f7
author Jonathan Cameron <Jonathan.Cameron@huawei.com> 1726508117 +0100
committer Michael S. Tsirkin <mst@redhat.com> 1730754204 -0500

hw/mem/cxl-type3: Add properties to control link speed and width

To establish performance characteristics of a CXL device when used via a
particular CXL topology (root ports, switches, end points) it is necessary
to set the appropriate link speed and width in the PCI Express capability
structure.  Provide x-speed and x-link properties for this.

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20240916173518.1843023-6-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>