commit 12f7fb60863f5aae44fa7a6c1f52cbecd29d4e9c
author Guenter Roeck <linux@roeck-us.net> Fri Apr 25 08:39:47 2014 -0700
committer Edgar E. Iglesias <edgar.iglesias@xilinx.com> Tue May 13 09:12:40 2014 +1000
tree fae9729b76d18aef6fbe814fc647ba5b93fe0d0e
parent 6d35556caa0c43533a9bf43195bad0152d86ea68

xilinx_intc: Fix writes into MER register

The MER register only has two valid bits. This is now used by
the linux kernel to auto-detect endianness, and causes Linux 3.15-rc1
and later to hang when run under qemu-microblaze. Mask valid bits before
writing the register to solve the problem.

Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
[Edgar: Untabified]
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>

hw/intc/xilinx_intc.c

diff --git a/hw/intc/xilinx_intc.c b/hw/intc/xilinx_intc.c
index 1b228ff..c3682f1 100644
--- a/hw/intc/xilinx_intc.c
+++ b/hw/intc/xilinx_intc.c
@@ -121,6 +121,9 @@
         case R_CIE:
             p->regs[R_IER] &= ~value; /* Atomic clear ie.  */
             break;
+        case R_MER:
+            p->regs[R_MER] = value & 0x3;
+            break;
         case R_ISR:
             if ((p->regs[R_MER] & 2)) {
                 break;