)]}'
{
  "commit": "12f6b8280fa3a89db853bef8373ddc949dbfde6b",
  "tree": "3c421250d71ae616e7df245ecca792e0fa4435b9",
  "parents": [
    "0117067131f99acaab4f4d2cca0290c5510e37cf"
  ],
  "author": {
    "name": "Zhao Liu",
    "email": "zhao1.liu@intel.com",
    "time": "Wed Apr 24 23:49:13 2024 +0800"
  },
  "committer": {
    "name": "Paolo Bonzini",
    "email": "pbonzini@redhat.com",
    "time": "Wed May 22 19:39:33 2024 +0200"
  },
  "message": "i386/cpu: Fix i/d-cache topology to core level for Intel CPU\n\nFor i-cache and d-cache, current QEMU hardcodes the maximum IDs for CPUs\nsharing cache (CPUID.04H.00H:EAX[bits 25:14] and CPUID.04H.01H:EAX[bits\n25:14]) to 0, and this means i-cache and d-cache are shared in the SMT\nlevel.\n\nThis is correct if there\u0027s single thread per core, but is wrong for the\nhyper threading case (one core contains multiple threads) since the\ni-cache and d-cache are shared in the core level other than SMT level.\n\nFor AMD CPU, commit 8f4202fb1080 (\"i386: Populate AMD Processor Cache\nInformation for cpuid 0x8000001D\") has already introduced i/d cache\ntopology as core level by default.\n\nTherefore, in order to be compatible with both multi-threaded and\nsingle-threaded situations, we should set i-cache and d-cache be shared\nat the core level by default.\n\nThis fix changes the default i/d cache topology from per-thread to\nper-core. Potentially, this change in L1 cache topology may affect the\nperformance of the VM if the user does not specifically specify the\ntopology or bind the vCPU. However, the way to achieve optimal\nperformance should be to create a reasonable topology and set the\nappropriate vCPU affinity without relying on QEMU\u0027s default topology\nstructure.\n\nFixes: 7e3482f82480 (\"i386: Helpers to encode cache information consistently\")\nSuggested-by: Robert Hoo \u003crobert.hu@linux.intel.com\u003e\nSigned-off-by: Zhao Liu \u003czhao1.liu@intel.com\u003e\nReviewed-by: Xiaoyao Li \u003cxiaoyao.li@intel.com\u003e\nTested-by: Babu Moger \u003cbabu.moger@amd.com\u003e\nTested-by: Yongwei Ma \u003cyongwei.ma@intel.com\u003e\nAcked-by: Michael S. Tsirkin \u003cmst@redhat.com\u003e\nMessage-ID: \u003c20240424154929.1487382-6-zhao1.liu@intel.com\u003e\n[Add compat property. - Paolo]\nSigned-off-by: Paolo Bonzini \u003cpbonzini@redhat.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "4a2d6f5a97f3fcc108eae848028009e1bef618bb",
      "old_mode": 33188,
      "old_path": "hw/i386/pc.c",
      "new_id": "6126bfdd2a723cdf3879a02f442632224d4c2b70",
      "new_mode": 33188,
      "new_path": "hw/i386/pc.c"
    },
    {
      "type": "modify",
      "old_id": "de1ad7270cfe663960ec67e4c90e17c5469ef43a",
      "old_mode": 33188,
      "old_path": "target/i386/cpu.c",
      "new_id": "3c66242f6d3bf19aba39f53918bb94a778ea04e9",
      "new_mode": 33188,
      "new_path": "target/i386/cpu.c"
    }
  ]
}