)]}'
{
  "commit": "12f1e2ec0095b2b4bfe55f2a608bd87be58fb908",
  "tree": "f42a4bce3df519312fbbba34bc35af7b78c9ebe8",
  "parents": [
    "718780d20470c66a3a36d036b29148d5809dc855"
  ],
  "author": {
    "name": "Jason Chien",
    "email": "jason.chien@sifive.com",
    "time": "Tue Jul 23 01:50:04 2024 +0800"
  },
  "committer": {
    "name": "Alistair Francis",
    "email": "alistair.francis@wdc.com",
    "time": "Wed Oct 02 15:11:51 2024 +1000"
  },
  "message": "target/riscv: Add a property to set vl to ceil(AVL/2)\n\nRVV spec allows implementations to set vl with values within\n[ceil(AVL/2),VLMAX] when VLMAX \u003c AVL \u003c 2*VLMAX. This commit adds a\nproperty \"rvv_vl_half_avl\" to enable setting vl \u003d ceil(AVL/2). This\nbehavior helps identify compiler issues and bugs.\n\nSigned-off-by: Jason Chien \u003cjason.chien@sifive.com\u003e\nReviewed-by: Frank Chang \u003cfrank.chang@sifive.com\u003e\nMessage-ID: \u003c20240722175004.23666-1-jason.chien@sifive.com\u003e\nSigned-off-by: Alistair Francis \u003calistair.francis@wdc.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "4bda754b01304e02b0cb013ee2aef764fb8c0dc9",
      "old_mode": 33188,
      "old_path": "target/riscv/cpu.c",
      "new_id": "cc5552500af0beeee9dab8e000675b8d2cac8e71",
      "new_mode": 33188,
      "new_path": "target/riscv/cpu.c"
    },
    {
      "type": "modify",
      "old_id": "8b272fb826efe31173e3cfd0d407f4c526be0564",
      "old_mode": 33188,
      "old_path": "target/riscv/cpu_cfg.h",
      "new_id": "96fe26d4eac499f5791ae14e189d75c70a005021",
      "new_mode": 33188,
      "new_path": "target/riscv/cpu_cfg.h"
    },
    {
      "type": "modify",
      "old_id": "10a52ceb5b182cfb2c00e7e24820a49b1bc77002",
      "old_mode": 33188,
      "old_path": "target/riscv/vector_helper.c",
      "new_id": "072bd444b1dce161228c7ac385eb341f4b7351a1",
      "new_mode": 33188,
      "new_path": "target/riscv/vector_helper.c"
    }
  ]
}