)]}'
{
  "commit": "11a3c4a286d5dc603582ea0a1fca62c2ec0a1aee",
  "tree": "a5722bfd1fd76a7a7667036812895bab6136eb13",
  "parents": [
    "4705fc0c8511d073bee4751c3c974aab2b10a970"
  ],
  "author": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Mon Nov 20 15:01:21 2023 +0000"
  },
  "committer": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Mon Nov 27 14:50:13 2023 +0000"
  },
  "message": "target/arm: Set IL bit for pauth, SVE access, BTI trap syndromes\n\nThe syndrome register value always has an IL field at bit 25, which\nis 0 for a trap on a 16 bit instruction, and 1 for a trap on a 32\nbit instruction (or for exceptions which aren\u0027t traps on a known\ninstruction, like PC alignment faults). This means that our\nsyn_*() functions should always either take an is_16bit argument to\ndetermine whether to set the IL bit, or else unconditionally set it.\n\nWe missed setting the IL bit for the syndrome for three kinds of trap:\n * an SVE access exception\n * a pointer authentication check failure\n * a BTI (branch target identification) check failure\n\nAll of these traps are AArch64 only, and so the instruction causing\nthe trap is always 64 bit. This means we can unconditionally set\nthe IL bit in the syn_*() function.\n\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nMessage-id: 20231120150121.3458408-1-peter.maydell@linaro.org\nCc: qemu-stable@nongnu.org\nReviewed-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "5d34755508da19d04154887403348ecb757faeac",
      "old_mode": 33188,
      "old_path": "target/arm/syndrome.h",
      "new_id": "95454b5b3bb01be2800f0933da43635c9f6fcde5",
      "new_mode": 33188,
      "new_path": "target/arm/syndrome.h"
    }
  ]
}