tree 78dc8fcc630a6659520a2542375f84eab84d7e0b
parent 17a86b0e9f64c00f3e438d903d3fa475255630cf
author Max Filippov <jcmvbkbc@gmail.com> 1361104738 +0400
committer Max Filippov <jcmvbkbc@gmail.com> 1548705320 -0800

target/xtensa: add MX interrupt controller

MX interrupt controller is a collection of the following devices
accessible through the external registers interface:
- interrupt distributor can route each external IRQ line to the
  corresponding external IRQ pin of selected subset of connected xtensa
  cores. It has per-CPU and per-IRQ enable signals and per-IRQ software
  assert signals;
- IPI controller has 16 per-CPU IPI signals that may be routed to a
  combination of 3 designated external IRQ pins of connected xtensa
  cores;
- cache coherecy register controls core L1 cache participation in the
  SMP cluster cache coherency protocol;
- runstall register lets BSP core stall and unstall AP cores.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>