commit 1090b9c6ccfe837f1c76dafb7e56031bd7844075
author Peter Maydell <peter.maydell@linaro.org> Tue Apr 15 19:18:46 2014 +0100
committer Peter Maydell <peter.maydell@linaro.org> Thu Apr 17 21:34:05 2014 +0100
tree dcefb350ea9e9d53f395d506c55dd8b2ed14d717
parent 2eef0bf82146034f756d39cb02c8c8dd561a8942

target-arm: Implement ISR_EL1 register

Implement the ISR_EL1 register. This is actually present in
ARMv7 as well but was previously unimplemented. It is a
read-only register that indicates whether interrupts are
currently pending.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>

target-arm/helper.c

diff --git a/target-arm/helper.c b/target-arm/helper.c
index 32af1df..825c8c9 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -665,6 +665,21 @@
     env->cp15.c0_cssel = value & 0xf;
 }
 
+static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+    CPUState *cs = ENV_GET_CPU(env);
+    uint64_t ret = 0;
+
+    if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
+        ret |= CPSR_I;
+    }
+    if (cs->interrupt_request & CPU_INTERRUPT_FIQ) {
+        ret |= CPSR_F;
+    }
+    /* External aborts are not possible in QEMU so A bit is always clear */
+    return ret;
+}
+
 static const ARMCPRegInfo v7_cp_reginfo[] = {
     /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
      * debug components
@@ -782,6 +797,9 @@
       .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW,
       .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el1),
       .resetfn = arm_cp_reset_ignore },
+    { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
+      .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,
+      .type = ARM_CP_NO_MIGRATE, .access = PL1_R, .readfn = isr_read },
     REGINFO_SENTINEL
 };