tree 594d6a056b3e9c5611850bff22f8fcdde248bf6d
parent 2d8fbcb1eecd8d39171f457e583428758321d69d
author Shawn Anastasio <sanastasio@raptorengineering.com> 1689178402 -0500
committer Cédric Le Goater <clg@kaod.org> 1693991972 +0200

target/ppc: Generate storage interrupts for radix RC changes

Change radix model to always generate a storage interrupt when the R/C
bits are not set appropriately in a PTE instead of setting the bits
itself.  According to the ISA both behaviors are valid, but in practice
this change more closely matches behavior observed on the POWER9 CPU.

From the POWER9 Processor User's Manual, Section 4.10.13.1: "When
performing Radix translation, the POWER9 hardware triggers the
appropriate interrupt ... for the mode and type of access whenever
Reference (R) and Change (C) bits require setting in either the guest or
host page-table entry (PTE)."

Signed-off-by: Shawn Anastasio <sanastasio@raptorengineering.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>