Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-2.12-pull-request' into staging
# gpg: Signature made Tue 23 Jan 2018 14:47:41 GMT
# gpg: using RSA key 0xF30C38BD3F2FBE3C
# gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>"
# gpg: aka "Laurent Vivier <laurent@vivier.eu>"
# gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>"
# Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C
* remotes/vivier2/tags/linux-user-for-2.12-pull-request:
linux-user: implement renameat2
page_unprotect(): handle calls to pages that are PAGE_WRITE
linux-user: Propagate siginfo_t through to handle_cpu_signal()
linux-user: remove nmi.c and fw-path-provider.c
linux-user: Add getcpu() support
linux-user: Add AT_SECURE auxval
linux-user: Fix sched_get/setaffinity conversion
linux-user/mmap.c: Avoid choosing NULL as start address
linux-user: Translate flags argument to dup3 syscall
linux-user: Don't use CMSG_ALIGN(sizeof struct cmsghdr)
linux-user: Fix length calculations in host_to_target_cmsg()
linux-user: wrap fork() in a start/end exclusive section
linux-user: Fix locking order in fork_start()
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c
index 071f4f5..f290f48 100644
--- a/accel/kvm/kvm-all.c
+++ b/accel/kvm/kvm-all.c
@@ -812,10 +812,6 @@
if (r < 0) {
abort();
}
-
- if (e->cleanup) {
- e->cleanup(e);
- }
}
static void kvm_io_ioeventfd_add(MemoryListener *listener,
diff --git a/block/Makefile.objs b/block/Makefile.objs
index 6eaf78a..a73387f 100644
--- a/block/Makefile.objs
+++ b/block/Makefile.objs
@@ -47,3 +47,5 @@
dmg-bz2.o-libs := $(BZIP2_LIBS)
qcow.o-libs := -lz
linux-aio.o-libs := -laio
+parallels.o-cflags := $(LIBXML2_CFLAGS)
+parallels.o-libs := $(LIBXML2_LIBS)
diff --git a/block/parallels.c b/block/parallels.c
index 9545761..d380208 100644
--- a/block/parallels.c
+++ b/block/parallels.c
@@ -36,6 +36,7 @@
#include "qemu/bswap.h"
#include "qemu/bitmap.h"
#include "migration/blocker.h"
+#include "parallels.h"
/**************************************************************/
@@ -45,30 +46,6 @@
#define HEADER_INUSE_MAGIC (0x746F6E59)
#define MAX_PARALLELS_IMAGE_FACTOR (1ull << 32)
-#define DEFAULT_CLUSTER_SIZE 1048576 /* 1 MiB */
-
-
-// always little-endian
-typedef struct ParallelsHeader {
- char magic[16]; // "WithoutFreeSpace"
- uint32_t version;
- uint32_t heads;
- uint32_t cylinders;
- uint32_t tracks;
- uint32_t bat_entries;
- uint64_t nb_sectors;
- uint32_t inuse;
- uint32_t data_off;
- char padding[12];
-} QEMU_PACKED ParallelsHeader;
-
-
-typedef enum ParallelsPreallocMode {
- PRL_PREALLOC_MODE_FALLOCATE = 0,
- PRL_PREALLOC_MODE_TRUNCATE = 1,
- PRL_PREALLOC_MODE__MAX = 2,
-} ParallelsPreallocMode;
-
static QEnumLookup prealloc_mode_lookup = {
.array = (const char *const[]) {
"falloc",
@@ -77,34 +54,6 @@
.size = PRL_PREALLOC_MODE__MAX
};
-typedef struct BDRVParallelsState {
- /** Locking is conservative, the lock protects
- * - image file extending (truncate, fallocate)
- * - any access to block allocation table
- */
- CoMutex lock;
-
- ParallelsHeader *header;
- uint32_t header_size;
- bool header_unclean;
-
- unsigned long *bat_dirty_bmap;
- unsigned int bat_dirty_block;
-
- uint32_t *bat_bitmap;
- unsigned int bat_size;
-
- int64_t data_end;
- uint64_t prealloc_size;
- ParallelsPreallocMode prealloc_mode;
-
- unsigned int tracks;
-
- unsigned int off_multiplier;
- Error *migration_blocker;
-} BDRVParallelsState;
-
-
#define PARALLELS_OPT_PREALLOC_MODE "prealloc-mode"
#define PARALLELS_OPT_PREALLOC_SIZE "prealloc-size"
@@ -193,6 +142,7 @@
static int64_t allocate_clusters(BlockDriverState *bs, int64_t sector_num,
int nb_sectors, int *pnum)
{
+ int ret;
BDRVParallelsState *s = bs->opaque;
int64_t pos, space, idx, to_allocate, i, len;
@@ -221,7 +171,6 @@
return len;
}
if (s->data_end + space > (len >> BDRV_SECTOR_BITS)) {
- int ret;
space += s->prealloc_size;
if (s->prealloc_mode == PRL_PREALLOC_MODE_FALLOCATE) {
ret = bdrv_pwrite_zeroes(bs->file,
@@ -237,6 +186,37 @@
}
}
+ /* Try to read from backing to fill empty clusters
+ * FIXME: 1. previous write_zeroes may be redundant
+ * 2. most of data we read from backing will be rewritten by
+ * parallels_co_writev. On aligned-to-cluster write we do not need
+ * this read at all.
+ * 3. it would be good to combine write of data from backing and new
+ * data into one write call */
+ if (bs->backing) {
+ int64_t nb_cow_sectors = to_allocate * s->tracks;
+ int64_t nb_cow_bytes = nb_cow_sectors << BDRV_SECTOR_BITS;
+ QEMUIOVector qiov;
+ struct iovec iov = {
+ .iov_len = nb_cow_bytes,
+ .iov_base = qemu_blockalign(bs, nb_cow_bytes)
+ };
+ qemu_iovec_init_external(&qiov, &iov, 1);
+
+ ret = bdrv_co_readv(bs->backing, idx * s->tracks, nb_cow_sectors,
+ &qiov);
+ if (ret < 0) {
+ qemu_vfree(iov.iov_base);
+ return ret;
+ }
+
+ ret = bdrv_co_writev(bs->file, s->data_end, nb_cow_sectors, &qiov);
+ qemu_vfree(iov.iov_base);
+ if (ret < 0) {
+ return ret;
+ }
+ }
+
for (i = 0; i < to_allocate; i++) {
s->bat_bitmap[idx + i] = cpu_to_le32(s->data_end / s->off_multiplier);
s->data_end += s->tracks;
@@ -360,12 +340,19 @@
nbytes = n << BDRV_SECTOR_BITS;
- if (position < 0) {
- qemu_iovec_memset(qiov, bytes_done, 0, nbytes);
- } else {
- qemu_iovec_reset(&hd_qiov);
- qemu_iovec_concat(&hd_qiov, qiov, bytes_done, nbytes);
+ qemu_iovec_reset(&hd_qiov);
+ qemu_iovec_concat(&hd_qiov, qiov, bytes_done, nbytes);
+ if (position < 0) {
+ if (bs->backing) {
+ ret = bdrv_co_readv(bs->backing, sector_num, n, &hd_qiov);
+ if (ret < 0) {
+ break;
+ }
+ } else {
+ qemu_iovec_memset(&hd_qiov, 0, 0, nbytes);
+ }
+ } else {
ret = bdrv_co_readv(bs->file, position, n, &hd_qiov);
if (ret < 0) {
break;
@@ -527,8 +514,9 @@
memcpy(header.magic, HEADER_MAGIC2, sizeof(header.magic));
header.version = cpu_to_le32(HEADER_VERSION);
/* don't care much about geometry, it is not used on image level */
- header.heads = cpu_to_le32(16);
- header.cylinders = cpu_to_le32(total_size / BDRV_SECTOR_SIZE / 16 / 32);
+ header.heads = cpu_to_le32(HEADS_NUMBER);
+ header.cylinders = cpu_to_le32(total_size / BDRV_SECTOR_SIZE
+ / HEADS_NUMBER / SEC_IN_CYL);
header.tracks = cpu_to_le32(cl_size >> BDRV_SECTOR_BITS);
header.bat_entries = cpu_to_le32(bat_entries);
header.nb_sectors = cpu_to_le64(DIV_ROUND_UP(total_size, BDRV_SECTOR_SIZE));
@@ -798,7 +786,7 @@
.bdrv_co_flush_to_os = parallels_co_flush_to_os,
.bdrv_co_readv = parallels_co_readv,
.bdrv_co_writev = parallels_co_writev,
-
+ .supports_backing = true,
.bdrv_create = parallels_create,
.bdrv_check = parallels_check,
.create_opts = ¶llels_create_opts,
diff --git a/block/parallels.h b/block/parallels.h
new file mode 100644
index 0000000..4b04407
--- /dev/null
+++ b/block/parallels.h
@@ -0,0 +1,88 @@
+/*
+* Block driver for Parallels disk image format
+*
+* Copyright (c) 2015-2017 Virtuozzo, Inc.
+* Authors:
+* 2016-2017 Klim S. Kireev <klim.kireev@virtuozzo.com>
+* 2015 Denis V. Lunev <den@openvz.org>
+*
+* This code was originally based on comparing different disk images created
+* by Parallels. Currently it is based on opened OpenVZ sources
+* available at
+* https://github.com/OpenVZ/ploop
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*/
+#ifndef BLOCK_PARALLELS_H
+#define BLOCK_PARALLELS_H
+#include "qemu/coroutine.h"
+#include "qemu/typedefs.h"
+
+#define HEADS_NUMBER 16
+#define SEC_IN_CYL 32
+#define DEFAULT_CLUSTER_SIZE 1048576 /* 1 MiB */
+
+/* always little-endian */
+typedef struct ParallelsHeader {
+ char magic[16]; /* "WithoutFreeSpace" */
+ uint32_t version;
+ uint32_t heads;
+ uint32_t cylinders;
+ uint32_t tracks;
+ uint32_t bat_entries;
+ uint64_t nb_sectors;
+ uint32_t inuse;
+ uint32_t data_off;
+ char padding[12];
+} QEMU_PACKED ParallelsHeader;
+
+typedef enum ParallelsPreallocMode {
+ PRL_PREALLOC_MODE_FALLOCATE = 0,
+ PRL_PREALLOC_MODE_TRUNCATE = 1,
+ PRL_PREALLOC_MODE__MAX = 2,
+} ParallelsPreallocMode;
+
+typedef struct BDRVParallelsState {
+ /** Locking is conservative, the lock protects
+ * - image file extending (truncate, fallocate)
+ * - any access to block allocation table
+ */
+ CoMutex lock;
+
+ ParallelsHeader *header;
+ uint32_t header_size;
+ bool header_unclean;
+
+ unsigned long *bat_dirty_bmap;
+ unsigned int bat_dirty_block;
+
+ uint32_t *bat_bitmap;
+ unsigned int bat_size;
+
+ int64_t data_end;
+ uint64_t prealloc_size;
+ ParallelsPreallocMode prealloc_mode;
+
+ unsigned int tracks;
+
+ unsigned int off_multiplier;
+ Error *migration_blocker;
+} BDRVParallelsState;
+
+#endif
diff --git a/block/qcow.c b/block/qcow.c
index 9569dee..d552a6e 100644
--- a/block/qcow.c
+++ b/block/qcow.c
@@ -379,6 +379,7 @@
/* update the L1 entry */
s->l1_table[l1_index] = l2_offset;
tmp = cpu_to_be64(l2_offset);
+ BLKDBG_EVENT(bs->file, BLKDBG_L1_UPDATE);
ret = bdrv_pwrite_sync(bs->file,
s->l1_table_offset + l1_index * sizeof(tmp),
&tmp, sizeof(tmp));
@@ -409,6 +410,7 @@
}
}
l2_table = s->l2_cache + (min_index << s->l2_bits);
+ BLKDBG_EVENT(bs->file, BLKDBG_L2_LOAD);
if (new_l2_table) {
memset(l2_table, 0, s->l2_size * sizeof(uint64_t));
ret = bdrv_pwrite_sync(bs->file, l2_offset, l2_table,
@@ -432,6 +434,7 @@
((cluster_offset & QCOW_OFLAG_COMPRESSED) && allocate == 1)) {
if (!allocate)
return 0;
+ BLKDBG_EVENT(bs->file, BLKDBG_CLUSTER_ALLOC);
/* allocate a new cluster */
if ((cluster_offset & QCOW_OFLAG_COMPRESSED) &&
(n_end - n_start) < s->cluster_sectors) {
@@ -447,6 +450,7 @@
}
cluster_offset = QEMU_ALIGN_UP(cluster_offset, s->cluster_size);
/* write the cluster content */
+ BLKDBG_EVENT(bs->file, BLKDBG_WRITE_AIO);
ret = bdrv_pwrite(bs->file, cluster_offset, s->cluster_cache,
s->cluster_size);
if (ret < 0) {
@@ -486,6 +490,7 @@
NULL) < 0) {
return -EIO;
}
+ BLKDBG_EVENT(bs->file, BLKDBG_WRITE_AIO);
ret = bdrv_pwrite(bs->file,
cluster_offset + i * 512,
s->cluster_data, 512);
@@ -503,6 +508,11 @@
/* update L2 table */
tmp = cpu_to_be64(cluster_offset);
l2_table[l2_index] = tmp;
+ if (allocate == 2) {
+ BLKDBG_EVENT(bs->file, BLKDBG_L2_UPDATE_COMPRESSED);
+ } else {
+ BLKDBG_EVENT(bs->file, BLKDBG_L2_UPDATE);
+ }
ret = bdrv_pwrite_sync(bs->file, l2_offset + l2_index * sizeof(tmp),
&tmp, sizeof(tmp));
if (ret < 0) {
@@ -579,6 +589,7 @@
if (s->cluster_cache_offset != coffset) {
csize = cluster_offset >> (63 - s->cluster_bits);
csize &= (s->cluster_size - 1);
+ BLKDBG_EVENT(bs->file, BLKDBG_READ_COMPRESSED);
ret = bdrv_pread(bs->file, coffset, s->cluster_data, csize);
if (ret != csize)
return -1;
@@ -635,6 +646,8 @@
hd_iov.iov_len = n * 512;
qemu_iovec_init_external(&hd_qiov, &hd_iov, 1);
qemu_co_mutex_unlock(&s->lock);
+ /* qcow2 emits this on bs->file instead of bs->backing */
+ BLKDBG_EVENT(bs->file, BLKDBG_READ_BACKING_AIO);
ret = bdrv_co_readv(bs->backing, sector_num, n, &hd_qiov);
qemu_co_mutex_lock(&s->lock);
if (ret < 0) {
@@ -661,6 +674,7 @@
hd_iov.iov_len = n * 512;
qemu_iovec_init_external(&hd_qiov, &hd_iov, 1);
qemu_co_mutex_unlock(&s->lock);
+ BLKDBG_EVENT(bs->file, BLKDBG_READ_AIO);
ret = bdrv_co_readv(bs->file,
(cluster_offset >> 9) + index_in_cluster,
n, &hd_qiov);
@@ -754,6 +768,7 @@
hd_iov.iov_len = n * 512;
qemu_iovec_init_external(&hd_qiov, &hd_iov, 1);
qemu_co_mutex_unlock(&s->lock);
+ BLKDBG_EVENT(bs->file, BLKDBG_WRITE_AIO);
ret = bdrv_co_writev(bs->file,
(cluster_offset >> 9) + index_in_cluster,
n, &hd_qiov);
@@ -1048,6 +1063,7 @@
.iov_len = out_len,
};
qemu_iovec_init_external(&hd_qiov, &iov, 1);
+ BLKDBG_EVENT(bs->file, BLKDBG_WRITE_COMPRESSED);
ret = bdrv_co_pwritev(bs->file, cluster_offset, out_len, &hd_qiov, 0);
if (ret < 0) {
goto fail;
diff --git a/block/qcow2-bitmap.c b/block/qcow2-bitmap.c
index f45e46c..efa10c6 100644
--- a/block/qcow2-bitmap.c
+++ b/block/qcow2-bitmap.c
@@ -1449,6 +1449,16 @@
bool found;
Qcow2BitmapList *bm_list;
+ if (s->qcow_version < 3) {
+ /* Without autoclear_features, we would always have to assume
+ * that a program without persistent dirty bitmap support has
+ * accessed this qcow2 file when opening it, and would thus
+ * have to drop all dirty bitmaps (defeating their purpose).
+ */
+ error_setg(errp, "Cannot store dirty bitmaps in qcow2 v2 files");
+ goto fail;
+ }
+
if (check_constraints_on_bitmap(bs, name, granularity, errp) != 0) {
goto fail;
}
diff --git a/block/qcow2-refcount.c b/block/qcow2-refcount.c
index 3de1ab5..92701ab 100644
--- a/block/qcow2-refcount.c
+++ b/block/qcow2-refcount.c
@@ -1508,7 +1508,7 @@
static int check_refcounts_l2(BlockDriverState *bs, BdrvCheckResult *res,
void **refcount_table,
int64_t *refcount_table_size, int64_t l2_offset,
- int flags)
+ int flags, BdrvCheckMode fix)
{
BDRVQcow2State *s = bs->opaque;
uint64_t *l2_table, l2_entry;
@@ -1579,6 +1579,57 @@
next_contiguous_offset = offset + s->cluster_size;
}
+ /* Correct offsets are cluster aligned */
+ if (offset_into_cluster(s, offset)) {
+ if (qcow2_get_cluster_type(l2_entry) ==
+ QCOW2_CLUSTER_ZERO_ALLOC)
+ {
+ fprintf(stderr, "%s offset=%" PRIx64 ": Preallocated zero "
+ "cluster is not properly aligned; L2 entry "
+ "corrupted.\n",
+ fix & BDRV_FIX_ERRORS ? "Repairing" : "ERROR",
+ offset);
+ if (fix & BDRV_FIX_ERRORS) {
+ uint64_t l2e_offset =
+ l2_offset + (uint64_t)i * sizeof(uint64_t);
+
+ l2_entry = QCOW_OFLAG_ZERO;
+ l2_table[i] = cpu_to_be64(l2_entry);
+ ret = qcow2_pre_write_overlap_check(bs,
+ QCOW2_OL_ACTIVE_L2 | QCOW2_OL_INACTIVE_L2,
+ l2e_offset, sizeof(uint64_t));
+ if (ret < 0) {
+ fprintf(stderr, "ERROR: Overlap check failed\n");
+ res->check_errors++;
+ /* Something is seriously wrong, so abort checking
+ * this L2 table */
+ goto fail;
+ }
+
+ ret = bdrv_pwrite_sync(bs->file, l2e_offset,
+ &l2_table[i], sizeof(uint64_t));
+ if (ret < 0) {
+ fprintf(stderr, "ERROR: Failed to overwrite L2 "
+ "table entry: %s\n", strerror(-ret));
+ res->check_errors++;
+ /* Do not abort, continue checking the rest of this
+ * L2 table's entries */
+ } else {
+ res->corruptions_fixed++;
+ /* Skip marking the cluster as used
+ * (it is unused now) */
+ continue;
+ }
+ } else {
+ res->corruptions++;
+ }
+ } else {
+ fprintf(stderr, "ERROR offset=%" PRIx64 ": Data cluster is "
+ "not properly aligned; L2 entry corrupted.\n", offset);
+ res->corruptions++;
+ }
+ }
+
/* Mark cluster as used */
ret = qcow2_inc_refcounts_imrt(bs, res,
refcount_table, refcount_table_size,
@@ -1586,13 +1637,6 @@
if (ret < 0) {
goto fail;
}
-
- /* Correct offsets are cluster aligned */
- if (offset_into_cluster(s, offset)) {
- fprintf(stderr, "ERROR offset=%" PRIx64 ": Cluster is not "
- "properly aligned; L2 entry corrupted.\n", offset);
- res->corruptions++;
- }
break;
}
@@ -1626,7 +1670,7 @@
void **refcount_table,
int64_t *refcount_table_size,
int64_t l1_table_offset, int l1_size,
- int flags)
+ int flags, BdrvCheckMode fix)
{
BDRVQcow2State *s = bs->opaque;
uint64_t *l1_table = NULL, l2_offset, l1_size2;
@@ -1681,7 +1725,8 @@
/* Process and check L2 entries */
ret = check_refcounts_l2(bs, res, refcount_table,
- refcount_table_size, l2_offset, flags);
+ refcount_table_size, l2_offset, flags,
+ fix);
if (ret < 0) {
goto fail;
}
@@ -1957,7 +2002,8 @@
/* current L1 table */
ret = check_refcounts_l1(bs, res, refcount_table, nb_clusters,
- s->l1_table_offset, s->l1_size, CHECK_FRAG_INFO);
+ s->l1_table_offset, s->l1_size, CHECK_FRAG_INFO,
+ fix);
if (ret < 0) {
return ret;
}
@@ -1966,7 +2012,7 @@
for (i = 0; i < s->nb_snapshots; i++) {
sn = s->snapshots + i;
ret = check_refcounts_l1(bs, res, refcount_table, nb_clusters,
- sn->l1_table_offset, sn->l1_size, 0);
+ sn->l1_table_offset, sn->l1_size, 0, fix);
if (ret < 0) {
return ret;
}
diff --git a/block/qcow2.c b/block/qcow2.c
index 4348b2c..1f80961 100644
--- a/block/qcow2.c
+++ b/block/qcow2.c
@@ -302,9 +302,17 @@
}
if (!(s->autoclear_features & QCOW2_AUTOCLEAR_BITMAPS)) {
- warn_report("a program lacking bitmap support "
- "modified this file, so all bitmaps are now "
- "considered inconsistent");
+ if (s->qcow_version < 3) {
+ /* Let's be a bit more specific */
+ warn_report("This qcow2 v2 image contains bitmaps, but "
+ "they may have been modified by a program "
+ "without persistent bitmap support; so now "
+ "they must all be considered inconsistent");
+ } else {
+ warn_report("a program lacking bitmap support "
+ "modified this file, so all bitmaps are now "
+ "considered inconsistent");
+ }
error_printf("Some clusters may be leaked, "
"run 'qemu-img check -r' on the image "
"file to fix.");
diff --git a/block/vmdk.c b/block/vmdk.c
index c665bcc..d71cec4 100644
--- a/block/vmdk.c
+++ b/block/vmdk.c
@@ -1075,6 +1075,8 @@
/* Read backing data before skip range */
if (skip_start_bytes > 0) {
if (bs->backing) {
+ /* qcow2 emits this on bs->file instead of bs->backing */
+ BLKDBG_EVENT(extent->file, BLKDBG_COW_READ);
ret = bdrv_pread(bs->backing, offset, whole_grain,
skip_start_bytes);
if (ret < 0) {
@@ -1082,6 +1084,7 @@
goto exit;
}
}
+ BLKDBG_EVENT(extent->file, BLKDBG_COW_WRITE);
ret = bdrv_pwrite(extent->file, cluster_offset, whole_grain,
skip_start_bytes);
if (ret < 0) {
@@ -1092,6 +1095,8 @@
/* Read backing data after skip range */
if (skip_end_bytes < cluster_bytes) {
if (bs->backing) {
+ /* qcow2 emits this on bs->file instead of bs->backing */
+ BLKDBG_EVENT(extent->file, BLKDBG_COW_READ);
ret = bdrv_pread(bs->backing, offset + skip_end_bytes,
whole_grain + skip_end_bytes,
cluster_bytes - skip_end_bytes);
@@ -1100,6 +1105,7 @@
goto exit;
}
}
+ BLKDBG_EVENT(extent->file, BLKDBG_COW_WRITE);
ret = bdrv_pwrite(extent->file, cluster_offset + skip_end_bytes,
whole_grain + skip_end_bytes,
cluster_bytes - skip_end_bytes);
@@ -1120,6 +1126,7 @@
{
offset = cpu_to_le32(offset);
/* update L2 table */
+ BLKDBG_EVENT(extent->file, BLKDBG_L2_UPDATE);
if (bdrv_pwrite_sync(extent->file,
((int64_t)m_data->l2_offset * 512)
+ (m_data->l2_index * sizeof(offset)),
@@ -1218,6 +1225,7 @@
}
}
l2_table = extent->l2_cache + (min_index * extent->l2_size);
+ BLKDBG_EVENT(extent->file, BLKDBG_L2_LOAD);
if (bdrv_pread(extent->file,
(int64_t)l2_offset * 512,
l2_table,
@@ -1393,12 +1401,16 @@
.iov_len = n_bytes,
};
qemu_iovec_init_external(&local_qiov, &iov, 1);
+
+ BLKDBG_EVENT(extent->file, BLKDBG_WRITE_COMPRESSED);
} else {
qemu_iovec_init(&local_qiov, qiov->niov);
qemu_iovec_concat(&local_qiov, qiov, qiov_offset, n_bytes);
+
+ BLKDBG_EVENT(extent->file, BLKDBG_WRITE_AIO);
}
- write_offset = cluster_offset + offset_in_cluster,
+ write_offset = cluster_offset + offset_in_cluster;
ret = bdrv_co_pwritev(extent->file, write_offset, n_bytes,
&local_qiov, 0);
@@ -1437,6 +1449,7 @@
if (!extent->compressed) {
+ BLKDBG_EVENT(extent->file, BLKDBG_READ_AIO);
ret = bdrv_co_preadv(extent->file,
cluster_offset + offset_in_cluster, bytes,
qiov, 0);
@@ -1450,6 +1463,7 @@
buf_bytes = cluster_bytes * 2;
cluster_buf = g_malloc(buf_bytes);
uncomp_buf = g_malloc(cluster_bytes);
+ BLKDBG_EVENT(extent->file, BLKDBG_READ_COMPRESSED);
ret = bdrv_pread(extent->file,
cluster_offset,
cluster_buf, buf_bytes);
@@ -1527,6 +1541,8 @@
qemu_iovec_reset(&local_qiov);
qemu_iovec_concat(&local_qiov, qiov, bytes_done, n_bytes);
+ /* qcow2 emits this on bs->file instead of bs->backing */
+ BLKDBG_EVENT(bs->file, BLKDBG_READ_BACKING_AIO);
ret = bdrv_co_preadv(bs->backing, offset, n_bytes,
&local_qiov, 0);
if (ret < 0) {
diff --git a/blockdev.c b/blockdev.c
index 29d569a..8e977ee 100644
--- a/blockdev.c
+++ b/blockdev.c
@@ -60,6 +60,11 @@
static int do_open_tray(const char *blk_name, const char *qdev_id,
bool force, Error **errp);
+static void blockdev_remove_medium(bool has_device, const char *device,
+ bool has_id, const char *id, Error **errp);
+static void blockdev_insert_medium(bool has_device, const char *device,
+ bool has_id, const char *id,
+ const char *node_name, Error **errp);
static const char *const if_name[IF_COUNT] = {
[IF_NONE] = "none",
@@ -2323,7 +2328,7 @@
}
error_free(local_err);
- qmp_x_blockdev_remove_medium(has_device, device, has_id, id, errp);
+ blockdev_remove_medium(has_device, device, has_id, id, errp);
}
void qmp_block_passwd(bool has_device, const char *device,
@@ -2446,8 +2451,8 @@
}
}
-void qmp_x_blockdev_remove_medium(bool has_device, const char *device,
- bool has_id, const char *id, Error **errp)
+static void blockdev_remove_medium(bool has_device, const char *device,
+ bool has_id, const char *id, Error **errp)
{
BlockBackend *blk;
BlockDriverState *bs;
@@ -2503,6 +2508,11 @@
aio_context_release(aio_context);
}
+void qmp_blockdev_remove_medium(const char *id, Error **errp)
+{
+ blockdev_remove_medium(false, NULL, true, id, errp);
+}
+
static void qmp_blockdev_insert_anon_medium(BlockBackend *blk,
BlockDriverState *bs, Error **errp)
{
@@ -2548,9 +2558,9 @@
}
}
-void qmp_x_blockdev_insert_medium(bool has_device, const char *device,
- bool has_id, const char *id,
- const char *node_name, Error **errp)
+static void blockdev_insert_medium(bool has_device, const char *device,
+ bool has_id, const char *id,
+ const char *node_name, Error **errp)
{
BlockBackend *blk;
BlockDriverState *bs;
@@ -2576,6 +2586,12 @@
qmp_blockdev_insert_anon_medium(blk, bs, errp);
}
+void qmp_blockdev_insert_medium(const char *id, const char *node_name,
+ Error **errp)
+{
+ blockdev_insert_medium(false, NULL, true, id, node_name, errp);
+}
+
void qmp_blockdev_change_medium(bool has_device, const char *device,
bool has_id, const char *id,
const char *filename,
@@ -2650,7 +2666,7 @@
error_free(err);
err = NULL;
- qmp_x_blockdev_remove_medium(has_device, device, has_id, id, &err);
+ blockdev_remove_medium(has_device, device, has_id, id, &err);
if (err) {
error_propagate(errp, err);
goto fail;
diff --git a/configure b/configure
index 6d8c996..044c6fa 100755
--- a/configure
+++ b/configure
@@ -435,6 +435,7 @@
jemalloc="no"
replication="yes"
vxhs=""
+libxml2=""
supported_cpu="no"
supported_os="no"
@@ -1298,6 +1299,10 @@
;;
--enable-numa) numa="yes"
;;
+ --disable-libxml2) libxml2="no"
+ ;;
+ --enable-libxml2) libxml2="yes"
+ ;;
--disable-tcmalloc) tcmalloc="no"
;;
--enable-tcmalloc) tcmalloc="yes"
@@ -1573,6 +1578,7 @@
tpm TPM support
libssh2 ssh block device support
numa libnuma support
+ libxml2 for Parallels image format
tcmalloc tcmalloc support
jemalloc jemalloc support
replication replication support
@@ -3748,6 +3754,20 @@
fi
fi
+##########################################
+# libxml2 probe
+if test "$libxml2" != "no" ; then
+ if $pkg_config --exists libxml-2.0; then
+ libxml2="yes"
+ libxml2_cflags=$($pkg_config --cflags libxml-2.0)
+ libxml2_libs=$($pkg_config --libs libxml-2.0)
+ else
+ if test "$libxml2" = "yes"; then
+ feature_not_found "libxml2" "Install libxml2 devel"
+ fi
+ libxml2="no"
+ fi
+fi
##########################################
# glusterfs probe
@@ -5630,6 +5650,7 @@
echo "snappy support $snappy"
echo "bzip2 support $bzip2"
echo "NUMA host support $numa"
+echo "libxml2 $libxml2"
echo "tcmalloc support $tcmalloc"
echo "jemalloc support $jemalloc"
echo "avx2 optimization $avx2_opt"
@@ -6299,6 +6320,12 @@
echo "CONFIG_RTNETLINK=y" >> $config_host_mak
fi
+if test "$libxml2" = "yes" ; then
+ echo "CONFIG_LIBXML2=y" >> $config_host_mak
+ echo "LIBXML2_CFLAGS=$libxml2_cflags" >> $config_host_mak
+ echo "LIBXML2_LIBS=$libxml2_libs" >> $config_host_mak
+fi
+
if test "$replication" = "yes" ; then
echo "CONFIG_REPLICATION=y" >> $config_host_mak
fi
diff --git a/disas/xtensa.c b/disas/xtensa.c
index 114326a..5e3870b 100644
--- a/disas/xtensa.c
+++ b/disas/xtensa.c
@@ -37,7 +37,7 @@
bfd_byte *buffer = g_malloc(1);
int status = info->read_memory_func(memaddr, buffer, 1, info);
xtensa_format fmt;
- unsigned slot, slots;
+ int slot, slots;
unsigned len;
if (status) {
@@ -79,7 +79,7 @@
for (slot = 0; slot < slots; ++slot) {
xtensa_opcode opc;
- unsigned opnd, vopnd, opnds;
+ int opnd, vopnd, opnds;
if (slot) {
info->fprintf_func(info->stream, "; ");
diff --git a/docs/interop/prl-xml.txt b/docs/interop/prl-xml.txt
new file mode 100644
index 0000000..7031f87
--- /dev/null
+++ b/docs/interop/prl-xml.txt
@@ -0,0 +1,158 @@
+= License =
+
+Copyright (c) 2015-2017, Virtuozzo, Inc.
+Authors:
+ 2015 Denis Lunev <den@openvz.org>
+ 2015 Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
+ 2016-2017 Klim Kireev <klim.kireev@virtuozzo.com>
+ 2016-2017 Edgar Kaziakhmedov <edgar.kaziakhmedov@virtuozzo.com>
+
+This work is licensed under the terms of the GNU GPL, version 2 or later.
+See the COPYING file in the top-level directory.
+
+This specification contains minimal information about Parallels Disk Format,
+which is enough to proper work with QEMU. Nevertheless, Parallels Cloud Server
+and Parallels Desktop are able to add some unspecified nodes to xml and use
+them, but they are for internal work and don't affect functionality. Also it
+uses auxiliary xml "Snapshot.xml", which allows to store optional snapshot
+information, but it doesn't influence open/read/write functionality. QEMU and
+other software should not use fields not covered in this document and
+Snapshot.xml file and must leave them as is.
+
+= Parallels Disk Format =
+
+Parallels disk consists of two parts: the set of snapshots and the disk
+descriptor file, which stores information about all files and snapshots.
+
+== Definitions ==
+ Snapshot a record of the contents captured at a particular time,
+ capable of storing current state. A snapshot has UUID and
+ parent UUID.
+
+ Snapshot image an overlay representing the difference between this
+ snapshot and some earlier snapshot.
+
+ Overlay an image storing the different sectors between two captured
+ states.
+
+ Root image snapshot image with no parent, the root of snapshot tree.
+
+ Storage the backing storage for a subset of the virtual disk. When
+ there is more than one storage in a Parallels disk then that
+ is referred to as a split image. In this case every storage
+ covers specific address space area of the disk and has its
+ particular root image. Split images are not considered here
+ and are not supported. Each storage consists of disk
+ parameters and a list of images. The list of images always
+ contains a root image and may also contain overlays. The
+ root image can be an expandable Parallels image file or
+ plain. Overlays must be expandable.
+
+ Description DiskDescriptor.xml stores information about disk parameters,
+ file snapshots, storages.
+
+ Top The overlay between actual state and some previous snapshot.
+ Snapshot It is not a snapshot in the classical sense because it
+ serves as the active image that the guest writes to.
+
+ Sector a 512-byte data chunk.
+
+== Description file ==
+All information is placed in a single XML element Parallels_disk_image.
+The element has only one attribute "Version", that must be 1.0.
+Schema of DiskDescriptor.xml:
+
+<Parallels_disk_image Version="1.0">
+ <Disk_Parameters>
+ ...
+ </Disk_Parameters>
+ <StorageData>
+ ...
+ </StorageData>
+ <Snapshots>
+ ...
+ </Snapshots>
+</Parallels_disk_image>
+
+== Disk_Parameters element ==
+The Disk_Parameters element describes the physical layout of the virtual disk
+and some general settings.
+
+The Disk_Parameters element MUST contain the following child elements:
+ * Disk_size - number of sectors in the disk,
+ desired size of the disk.
+ * Cylinders - number of the disk cylinders.
+ * Heads - number of the disk heads.
+ * Sectors - number of the disk sectors per cylinder
+ (sector size is 512 bytes)
+ Limitation: Product of the Heads, Sectors and Cylinders
+ values MUST be equal to the value of the Disk_size parameter.
+ * Padding - must be 0. Parallels Cloud Server and Parallels Desktop may
+ use padding set to 1, however this case is not covered
+ by this spec, QEMU and other software should not open
+ such disks and should not create them.
+
+== StorageData element ==
+This element of the file describes the root image and all snapshot images.
+
+The StorageData element consists of the Storage child element, as shown below:
+<StorageData>
+ <Storage>
+ ...
+ </Storage>
+</StorageData>
+
+A Storage element has following child elements:
+ * Start - start sector of the storage, in case of non split storage
+ equals to 0.
+ * End - number of sector following the last sector, in case of non
+ split storage equals to Disk_size.
+ * Blocksize - storage cluster size, number of sectors per one cluster.
+ Cluster size for each "Compressed" (see below) image in
+ parallels disk must be equal to this field. Note: cluster
+ size for Parallels Expandable Image is in 'tracks' field of
+ its header (see docs/interop/parallels.txt).
+ * Several Image child elements.
+
+Each Image element has following child elements:
+ * GUID - image identifier, UUID in curly brackets.
+ For instance, {12345678-9abc-def1-2345-6789abcdef12}.
+ The GUID is used by the Snapshots element to reference images
+ (see below)
+ * Type - image type of the element. It can be:
+ "Plain" for raw files.
+ "Compressed" for expanding disks.
+ * File - path to image file. Path can be relative to DiskDecriptor.xml or
+ absolute.
+
+== Snapshots element ==
+The Snapshots element describes the snapshot relations with the snapshot tree.
+
+The element contains the set of Shot child elements, as shown below:
+<Snapshots>
+ <TopGUID> ... </TopGUID> /* Optional child element */
+ <Shot>
+ ...
+ </Shot>
+ <Shot>
+ ...
+ </Shot>
+ ...
+</Snapshots>
+
+Each Shot element contains the following child elements:
+ * GUID - an image GUID.
+ * ParentGUID - GUID of the image of the parent snapshot.
+
+The software may traverse snapshots from child to parent using <ParentGUID>
+field as reference. ParentGUID of root snapshot is
+{00000000-0000-0000-0000-000000000000}. There should be only one root
+snapshot. Top snapshot could be described via two ways: via TopGUID child
+element of the Snapshots element or via predefined GUID
+{5fbaabe3-6958-40ff-92a7-860e329aab41}. If TopGUID is defined, predefined GUID is
+interpreted as usual GUID. All snapshot images (except Top Snapshot) should be
+opened read-only. There is another predefined GUID,
+BackupID = {704718e1-2314-44c8-9087-d78ed36b0f4e}, which is used by original and
+some third-party software for backup, QEMU and other software may operate with
+images with GUID = BackupID as usual, however, it is not recommended to use this
+GUID for new disks. Top snapshot cannot have this GUID.
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index 1ac356d..51a58fe 100644
--- a/hw/block/nvme.c
+++ b/hw/block/nvme.c
@@ -91,7 +91,19 @@
return sq->head == sq->tail;
}
-static void nvme_isr_notify(NvmeCtrl *n, NvmeCQueue *cq)
+static void nvme_irq_check(NvmeCtrl *n)
+{
+ if (msix_enabled(&(n->parent_obj))) {
+ return;
+ }
+ if (~n->bar.intms & n->irq_status) {
+ pci_irq_assert(&n->parent_obj);
+ } else {
+ pci_irq_deassert(&n->parent_obj);
+ }
+}
+
+static void nvme_irq_assert(NvmeCtrl *n, NvmeCQueue *cq)
{
if (cq->irq_enabled) {
if (msix_enabled(&(n->parent_obj))) {
@@ -99,13 +111,28 @@
msix_notify(&(n->parent_obj), cq->vector);
} else {
trace_nvme_irq_pin();
- pci_irq_pulse(&n->parent_obj);
+ assert(cq->cqid < 64);
+ n->irq_status |= 1 << cq->cqid;
+ nvme_irq_check(n);
}
} else {
trace_nvme_irq_masked();
}
}
+static void nvme_irq_deassert(NvmeCtrl *n, NvmeCQueue *cq)
+{
+ if (cq->irq_enabled) {
+ if (msix_enabled(&(n->parent_obj))) {
+ return;
+ } else {
+ assert(cq->cqid < 64);
+ n->irq_status &= ~(1 << cq->cqid);
+ nvme_irq_check(n);
+ }
+ }
+}
+
static uint16_t nvme_map_prp(QEMUSGList *qsg, QEMUIOVector *iov, uint64_t prp1,
uint64_t prp2, uint32_t len, NvmeCtrl *n)
{
@@ -242,7 +269,7 @@
sizeof(req->cqe));
QTAILQ_INSERT_TAIL(&sq->req_list, req, entry);
}
- nvme_isr_notify(n, cq);
+ nvme_irq_assert(n, cq);
}
static void nvme_enqueue_req_completion(NvmeCQueue *cq, NvmeRequest *req)
@@ -905,6 +932,7 @@
n->bar.intmc = n->bar.intms;
trace_nvme_mmio_intm_set(data & 0xffffffff,
n->bar.intmc);
+ nvme_irq_check(n);
break;
case 0x10: /* INTMC */
if (unlikely(msix_enabled(&(n->parent_obj)))) {
@@ -917,6 +945,7 @@
n->bar.intmc = n->bar.intms;
trace_nvme_mmio_intm_clr(data & 0xffffffff,
n->bar.intmc);
+ nvme_irq_check(n);
break;
case 0x14: /* CC */
trace_nvme_mmio_cfg(data & 0xffffffff);
@@ -1085,8 +1114,8 @@
timer_mod(cq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500);
}
- if (cq->tail != cq->head) {
- nvme_isr_notify(n, cq);
+ if (cq->tail == cq->head) {
+ nvme_irq_deassert(n, cq);
}
} else {
/* Submission queue doorbell write */
diff --git a/hw/block/nvme.h b/hw/block/nvme.h
index 6aab338..7b62dad 100644
--- a/hw/block/nvme.h
+++ b/hw/block/nvme.h
@@ -775,6 +775,7 @@
uint32_t cmbsz;
uint32_t cmbloc;
uint8_t *cmbuf;
+ uint64_t irq_status;
char *serial;
NvmeNamespace *namespaces;
diff --git a/hw/s390x/s390-stattrib-kvm.c b/hw/s390x/s390-stattrib-kvm.c
index 41770a7..480551c 100644
--- a/hw/s390x/s390-stattrib-kvm.c
+++ b/hw/s390x/s390-stattrib-kvm.c
@@ -116,7 +116,7 @@
for (cx = 0; cx + len <= max; cx += len) {
clog.start_gfn = cx;
clog.count = len;
- clog.values = (uint64_t)(sas->incoming_buffer + cx * len);
+ clog.values = (uint64_t)(sas->incoming_buffer + cx);
r = kvm_vm_ioctl(kvm_state, KVM_S390_SET_CMMA_BITS, &clog);
if (r) {
error_report("KVM_S390_SET_CMMA_BITS failed: %s", strerror(-r));
@@ -126,7 +126,7 @@
if (cx < max) {
clog.start_gfn = cx;
clog.count = max - cx;
- clog.values = (uint64_t)(sas->incoming_buffer + cx * len);
+ clog.values = (uint64_t)(sas->incoming_buffer + cx);
r = kvm_vm_ioctl(kvm_state, KVM_S390_SET_CMMA_BITS, &clog);
if (r) {
error_report("KVM_S390_SET_CMMA_BITS failed: %s", strerror(-r));
diff --git a/hw/s390x/sclp.c b/hw/s390x/sclp.c
index 9be0cb8..276972b 100644
--- a/hw/s390x/sclp.c
+++ b/hw/s390x/sclp.c
@@ -67,7 +67,7 @@
prepare_cpu_entries(sclp, read_info->entries, &cpu_count);
read_info->entries_cpu = cpu_to_be16(cpu_count);
read_info->offset_cpu = cpu_to_be16(offsetof(ReadInfo, entries));
- read_info->highest_cpu = cpu_to_be16(max_cpus);
+ read_info->highest_cpu = cpu_to_be16(max_cpus - 1);
read_info->ibc_val = cpu_to_be32(s390_get_ibc_val());
@@ -233,7 +233,7 @@
sccb->h.response_code = cpu_to_be16(SCLP_RC_INVALID_SCLP_COMMAND);
return;
}
- assign_addr = (assign_info->rn - 1) * mhd->rzm;
+ assign_addr = (be16_to_cpu(assign_info->rn) - 1) * mhd->rzm;
if ((assign_addr % MEM_SECTION_SIZE == 0) &&
(assign_addr >= mhd->padded_ram_size)) {
@@ -292,7 +292,7 @@
sccb->h.response_code = cpu_to_be16(SCLP_RC_INVALID_SCLP_COMMAND);
return;
}
- unassign_addr = (assign_info->rn - 1) * mhd->rzm;
+ unassign_addr = (be16_to_cpu(assign_info->rn) - 1) * mhd->rzm;
/* if the addr is a multiple of 256 MB */
if ((unassign_addr % MEM_SECTION_SIZE == 0) &&
diff --git a/hw/s390x/virtio-ccw.c b/hw/s390x/virtio-ccw.c
index 38f6a8a..3d8f269 100644
--- a/hw/s390x/virtio-ccw.c
+++ b/hw/s390x/virtio-ccw.c
@@ -426,8 +426,9 @@
* passes us zeroes for those we don't support.
*/
if (features.features) {
- fprintf(stderr, "Guest bug: features[%i]=%x (expected 0)\n",
- features.index, features.features);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Guest bug: features[%i]=%x (expected 0)",
+ features.index, features.features);
/* XXX: do a unit check here? */
}
}
diff --git a/hw/virtio/virtio-bus.c b/hw/virtio/virtio-bus.c
index 8106346..3042232 100644
--- a/hw/virtio/virtio-bus.c
+++ b/hw/virtio/virtio-bus.c
@@ -256,15 +256,6 @@
return k->ioeventfd_assign && k->ioeventfd_enabled(proxy);
}
-static void virtio_bus_cleanup_event_notifier(EventNotifier *notifier)
-{
- /* Test and clear notifier after disabling event,
- * in case poll callback didn't have time to run.
- */
- virtio_queue_host_notifier_read(notifier);
- event_notifier_cleanup(notifier);
-}
-
/*
* This function switches ioeventfd on/off in the device.
* The caller must set or clear the handlers for the EventNotifier.
@@ -292,13 +283,19 @@
r = k->ioeventfd_assign(proxy, notifier, n, true);
if (r < 0) {
error_report("%s: unable to assign ioeventfd: %d", __func__, r);
- virtio_bus_cleanup_event_notifier(notifier);
+ goto cleanup_event_notifier;
}
+ return 0;
} else {
- notifier->cleanup = virtio_bus_cleanup_event_notifier;
k->ioeventfd_assign(proxy, notifier, n, false);
}
+cleanup_event_notifier:
+ /* Test and clear notifier after disabling event,
+ * in case poll callback didn't have time to run.
+ */
+ virtio_queue_host_notifier_read(notifier);
+ event_notifier_cleanup(notifier);
return r;
}
diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c
index 3ac3491..d6002ee 100644
--- a/hw/virtio/virtio.c
+++ b/hw/virtio/virtio.c
@@ -2574,7 +2574,6 @@
VirtioBusState *qbus = VIRTIO_BUS(qdev_get_parent_bus(DEVICE(vdev)));
int n, r, err;
- memory_region_transaction_begin();
for (n = 0; n < VIRTIO_QUEUE_MAX; n++) {
VirtQueue *vq = &vdev->vq[n];
if (!virtio_queue_get_num(vdev, n)) {
@@ -2597,7 +2596,6 @@
}
event_notifier_set(&vq->host_notifier);
}
- memory_region_transaction_commit();
return 0;
assign_error:
@@ -2611,7 +2609,6 @@
r = virtio_bus_set_host_notifier(qbus, n, false);
assert(r >= 0);
}
- memory_region_transaction_commit();
return err;
}
@@ -2628,7 +2625,6 @@
VirtioBusState *qbus = VIRTIO_BUS(qdev_get_parent_bus(DEVICE(vdev)));
int n, r;
- memory_region_transaction_begin();
for (n = 0; n < VIRTIO_QUEUE_MAX; n++) {
VirtQueue *vq = &vdev->vq[n];
@@ -2639,7 +2635,6 @@
r = virtio_bus_set_host_notifier(qbus, n, false);
assert(r >= 0);
}
- memory_region_transaction_commit();
}
void virtio_device_stop_ioeventfd(VirtIODevice *vdev)
diff --git a/hw/xtensa/Makefile.objs b/hw/xtensa/Makefile.objs
index cb77dc3..cb4998d 100644
--- a/hw/xtensa/Makefile.objs
+++ b/hw/xtensa/Makefile.objs
@@ -1,3 +1,4 @@
obj-y += pic_cpu.o
obj-y += sim.o
+obj-y += xtensa_memory.o
obj-y += xtfpga.o
diff --git a/hw/xtensa/sim.c b/hw/xtensa/sim.c
index 2bb883b..5c0ba23 100644
--- a/hw/xtensa/sim.c
+++ b/hw/xtensa/sim.c
@@ -36,25 +36,7 @@
#include "exec/memory.h"
#include "exec/address-spaces.h"
#include "qemu/error-report.h"
-
-static void xtensa_create_memory_regions(const XtensaMemory *memory,
- const char *name)
-{
- unsigned i;
- GString *num_name = g_string_new(NULL);
-
- for (i = 0; i < memory->num; ++i) {
- MemoryRegion *m;
-
- g_string_printf(num_name, "%s%u", name, i);
- m = g_new(MemoryRegion, 1);
- memory_region_init_ram(m, NULL, num_name->str,
- memory->location[i].size, &error_fatal);
- memory_region_add_subregion(get_system_memory(),
- memory->location[i].addr, m);
- }
- g_string_free(num_name, true);
-}
+#include "xtensa_memory.h"
static uint64_t translate_phys_addr(void *opaque, uint64_t addr)
{
@@ -94,12 +76,18 @@
XtensaMemory sysram = env->config->sysram;
sysram.location[0].size = ram_size;
- xtensa_create_memory_regions(&env->config->instrom, "xtensa.instrom");
- xtensa_create_memory_regions(&env->config->instram, "xtensa.instram");
- xtensa_create_memory_regions(&env->config->datarom, "xtensa.datarom");
- xtensa_create_memory_regions(&env->config->dataram, "xtensa.dataram");
- xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom");
- xtensa_create_memory_regions(&sysram, "xtensa.sysram");
+ xtensa_create_memory_regions(&env->config->instrom, "xtensa.instrom",
+ get_system_memory());
+ xtensa_create_memory_regions(&env->config->instram, "xtensa.instram",
+ get_system_memory());
+ xtensa_create_memory_regions(&env->config->datarom, "xtensa.datarom",
+ get_system_memory());
+ xtensa_create_memory_regions(&env->config->dataram, "xtensa.dataram",
+ get_system_memory());
+ xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom",
+ get_system_memory());
+ xtensa_create_memory_regions(&sysram, "xtensa.sysram",
+ get_system_memory());
}
if (serial_hds[0]) {
diff --git a/hw/xtensa/xtensa_memory.c b/hw/xtensa/xtensa_memory.c
new file mode 100644
index 0000000..394967f
--- /dev/null
+++ b/hw/xtensa/xtensa_memory.c
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2017, Max Filippov, Open Source and Linux Lab.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the Open Source and Linux Lab nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu-common.h"
+#include "cpu.h"
+#include "sysemu/sysemu.h"
+#include "hw/boards.h"
+#include "exec/memory.h"
+#include "qemu/error-report.h"
+#include "xtensa_memory.h"
+
+void xtensa_create_memory_regions(const XtensaMemory *memory,
+ const char *name,
+ MemoryRegion *super)
+{
+ unsigned i;
+ GString *num_name = g_string_new(NULL);
+
+ for (i = 0; i < memory->num; ++i) {
+ MemoryRegion *m;
+
+ g_string_printf(num_name, "%s%u", name, i);
+ m = g_new(MemoryRegion, 1);
+ memory_region_init_ram(m, NULL, num_name->str,
+ memory->location[i].size, &error_fatal);
+ memory_region_add_subregion(super, memory->location[i].addr, m);
+ }
+ g_string_free(num_name, true);
+}
diff --git a/hw/xtensa/xtensa_memory.h b/hw/xtensa/xtensa_memory.h
new file mode 100644
index 0000000..cab4d17
--- /dev/null
+++ b/hw/xtensa/xtensa_memory.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2017, Max Filippov, Open Source and Linux Lab.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the Open Source and Linux Lab nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _XTENSA_MEMORY_H
+#define _XTENSA_MEMORY_H
+
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "cpu.h"
+#include "exec/memory.h"
+
+void xtensa_create_memory_regions(const XtensaMemory *memory,
+ const char *name,
+ MemoryRegion *super);
+
+#endif
diff --git a/hw/xtensa/xtfpga.c b/hw/xtensa/xtfpga.c
index 1971ecf..76ea970 100644
--- a/hw/xtensa/xtfpga.c
+++ b/hw/xtensa/xtfpga.c
@@ -44,33 +44,39 @@
#include "sysemu/device_tree.h"
#include "qemu/error-report.h"
#include "bootparam.h"
+#include "xtensa_memory.h"
-typedef struct LxBoardDesc {
- hwaddr flash_base;
- size_t flash_size;
- size_t flash_boot_base;
- size_t flash_sector_size;
+typedef struct XtfpgaFlashDesc {
+ hwaddr base;
+ size_t size;
+ size_t boot_base;
+ size_t sector_size;
+} XtfpgaFlashDesc;
+
+typedef struct XtfpgaBoardDesc {
+ const XtfpgaFlashDesc *flash;
size_t sram_size;
-} LxBoardDesc;
+ const hwaddr *io;
+} XtfpgaBoardDesc;
-typedef struct Lx60FpgaState {
+typedef struct XtfpgaFpgaState {
MemoryRegion iomem;
uint32_t leds;
uint32_t switches;
-} Lx60FpgaState;
+} XtfpgaFpgaState;
-static void lx60_fpga_reset(void *opaque)
+static void xtfpga_fpga_reset(void *opaque)
{
- Lx60FpgaState *s = opaque;
+ XtfpgaFpgaState *s = opaque;
s->leds = 0;
s->switches = 0;
}
-static uint64_t lx60_fpga_read(void *opaque, hwaddr addr,
+static uint64_t xtfpga_fpga_read(void *opaque, hwaddr addr,
unsigned size)
{
- Lx60FpgaState *s = opaque;
+ XtfpgaFpgaState *s = opaque;
switch (addr) {
case 0x0: /*build date code*/
@@ -88,10 +94,10 @@
return 0;
}
-static void lx60_fpga_write(void *opaque, hwaddr addr,
+static void xtfpga_fpga_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
- Lx60FpgaState *s = opaque;
+ XtfpgaFpgaState *s = opaque;
switch (addr) {
case 0x8: /*LEDs (off = 0, on = 1)*/
@@ -106,26 +112,26 @@
}
}
-static const MemoryRegionOps lx60_fpga_ops = {
- .read = lx60_fpga_read,
- .write = lx60_fpga_write,
+static const MemoryRegionOps xtfpga_fpga_ops = {
+ .read = xtfpga_fpga_read,
+ .write = xtfpga_fpga_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static Lx60FpgaState *lx60_fpga_init(MemoryRegion *address_space,
+static XtfpgaFpgaState *xtfpga_fpga_init(MemoryRegion *address_space,
hwaddr base)
{
- Lx60FpgaState *s = g_malloc(sizeof(Lx60FpgaState));
+ XtfpgaFpgaState *s = g_malloc(sizeof(XtfpgaFpgaState));
- memory_region_init_io(&s->iomem, NULL, &lx60_fpga_ops, s,
- "lx60.fpga", 0x10000);
+ memory_region_init_io(&s->iomem, NULL, &xtfpga_fpga_ops, s,
+ "xtfpga.fpga", 0x10000);
memory_region_add_subregion(address_space, base, &s->iomem);
- lx60_fpga_reset(s);
- qemu_register_reset(lx60_fpga_reset, s);
+ xtfpga_fpga_reset(s);
+ qemu_register_reset(xtfpga_fpga_reset, s);
return s;
}
-static void lx60_net_init(MemoryRegion *address_space,
+static void xtfpga_net_init(MemoryRegion *address_space,
hwaddr base,
hwaddr descriptors,
hwaddr buffers,
@@ -154,7 +160,7 @@
}
static pflash_t *xtfpga_flash_init(MemoryRegion *address_space,
- const LxBoardDesc *board,
+ const XtfpgaBoardDesc *board,
DriveInfo *dinfo, int be)
{
SysBusDevice *s;
@@ -163,14 +169,14 @@
qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
&error_abort);
qdev_prop_set_uint32(dev, "num-blocks",
- board->flash_size / board->flash_sector_size);
- qdev_prop_set_uint64(dev, "sector-length", board->flash_sector_size);
+ board->flash->size / board->flash->sector_size);
+ qdev_prop_set_uint64(dev, "sector-length", board->flash->sector_size);
qdev_prop_set_uint8(dev, "width", 2);
qdev_prop_set_bit(dev, "big-endian", be);
- qdev_prop_set_string(dev, "name", "lx60.io.flash");
+ qdev_prop_set_string(dev, "name", "xtfpga.io.flash");
qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
- memory_region_add_subregion(address_space, board->flash_base,
+ memory_region_add_subregion(address_space, board->flash->base,
sysbus_mmio_get_region(s, 0));
return OBJECT_CHECK(pflash_t, (dev), "cfi.pflash01");
}
@@ -182,31 +188,31 @@
return cpu_get_phys_page_debug(CPU(cpu), addr);
}
-static void lx60_reset(void *opaque)
+static void xtfpga_reset(void *opaque)
{
XtensaCPU *cpu = opaque;
cpu_reset(CPU(cpu));
}
-static uint64_t lx60_io_read(void *opaque, hwaddr addr,
+static uint64_t xtfpga_io_read(void *opaque, hwaddr addr,
unsigned size)
{
return 0;
}
-static void lx60_io_write(void *opaque, hwaddr addr,
+static void xtfpga_io_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
}
-static const MemoryRegionOps lx60_io_ops = {
- .read = lx60_io_read,
- .write = lx60_io_write,
+static const MemoryRegionOps xtfpga_io_ops = {
+ .read = xtfpga_io_read,
+ .write = xtfpga_io_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static void lx_init(const LxBoardDesc *board, MachineState *machine)
+static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine)
{
#ifdef TARGET_WORDS_BIGENDIAN
int be = 1;
@@ -216,7 +222,7 @@
MemoryRegion *system_memory = get_system_memory();
XtensaCPU *cpu = NULL;
CPUXtensaState *env = NULL;
- MemoryRegion *ram, *rom, *system_io;
+ MemoryRegion *system_io;
DriveInfo *dinfo;
pflash_t *flash = NULL;
QemuOpts *machine_opts = qemu_get_machine_opts();
@@ -224,6 +230,7 @@
const char *kernel_cmdline = qemu_opt_get(machine_opts, "append");
const char *dtb_filename = qemu_opt_get(machine_opts, "dtb");
const char *initrd_filename = qemu_opt_get(machine_opts, "initrd");
+ const unsigned system_io_size = 224 * 1024 * 1024;
int n;
for (n = 0; n < smp_cpus; n++) {
@@ -231,25 +238,43 @@
env = &cpu->env;
env->sregs[PRID] = n;
- qemu_register_reset(lx60_reset, cpu);
+ qemu_register_reset(xtfpga_reset, cpu);
/* Need MMU initialized prior to ELF loading,
* so that ELF gets loaded into virtual addresses
*/
cpu_reset(CPU(cpu));
}
- ram = g_malloc(sizeof(*ram));
- memory_region_init_ram(ram, NULL, "lx60.dram", machine->ram_size,
- &error_fatal);
- memory_region_add_subregion(system_memory, 0, ram);
+ if (env) {
+ XtensaMemory sysram = env->config->sysram;
+
+ sysram.location[0].size = machine->ram_size;
+ xtensa_create_memory_regions(&env->config->instrom, "xtensa.instrom",
+ system_memory);
+ xtensa_create_memory_regions(&env->config->instram, "xtensa.instram",
+ system_memory);
+ xtensa_create_memory_regions(&env->config->datarom, "xtensa.datarom",
+ system_memory);
+ xtensa_create_memory_regions(&env->config->dataram, "xtensa.dataram",
+ system_memory);
+ xtensa_create_memory_regions(&sysram, "xtensa.sysram",
+ system_memory);
+ }
system_io = g_malloc(sizeof(*system_io));
- memory_region_init_io(system_io, NULL, &lx60_io_ops, NULL, "lx60.io",
- 224 * 1024 * 1024);
- memory_region_add_subregion(system_memory, 0xf0000000, system_io);
- lx60_fpga_init(system_io, 0x0d020000);
+ memory_region_init_io(system_io, NULL, &xtfpga_io_ops, NULL, "xtfpga.io",
+ system_io_size);
+ memory_region_add_subregion(system_memory, board->io[0], system_io);
+ if (board->io[1]) {
+ MemoryRegion *io = g_malloc(sizeof(*io));
+
+ memory_region_init_alias(io, NULL, "xtfpga.io.cached",
+ system_io, 0, system_io_size);
+ memory_region_add_subregion(system_memory, board->io[1], io);
+ }
+ xtfpga_fpga_init(system_io, 0x0d020000);
if (nd_table[0].used) {
- lx60_net_init(system_io, 0x0d030000, 0x0d030400, 0x0d800000,
+ xtfpga_net_init(system_io, 0x0d030000, 0x0d030400, 0x0d800000,
xtensa_get_extint(env, 1), nd_table);
}
@@ -269,21 +294,24 @@
if (kernel_filename) {
uint32_t entry_point = env->pc;
size_t bp_size = 3 * get_tag_size(0); /* first/last and memory tags */
- uint32_t tagptr = 0xfe000000 + board->sram_size;
+ uint32_t tagptr = env->config->sysrom.location[0].addr +
+ board->sram_size;
uint32_t cur_tagptr;
BpMemInfo memory_location = {
.type = tswap32(MEMORY_TYPE_CONVENTIONAL),
- .start = tswap32(0),
- .end = tswap32(machine->ram_size),
+ .start = tswap32(env->config->sysram.location[0].addr),
+ .end = tswap32(env->config->sysram.location[0].addr +
+ machine->ram_size),
};
uint32_t lowmem_end = machine->ram_size < 0x08000000 ?
machine->ram_size : 0x08000000;
uint32_t cur_lowmem = QEMU_ALIGN_UP(lowmem_end / 2, 4096);
- rom = g_malloc(sizeof(*rom));
- memory_region_init_ram(rom, NULL, "lx60.sram", board->sram_size,
- &error_fatal);
- memory_region_add_subregion(system_memory, 0xfe000000, rom);
+ lowmem_end += env->config->sysram.location[0].addr;
+ cur_lowmem += env->config->sysram.location[0].addr;
+
+ xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom",
+ system_memory);
if (kernel_cmdline) {
bp_size += get_tag_size(strlen(kernel_cmdline) + 1);
@@ -372,146 +400,308 @@
}
}
if (entry_point != env->pc) {
- static const uint8_t jx_a0[] = {
+ uint8_t boot[] = {
#ifdef TARGET_WORDS_BIGENDIAN
- 0x0a, 0, 0,
+ 0x60, 0x00, 0x08, /* j 1f */
+ 0x00, /* .literal_position */
+ 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */
+ 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */
+ /* 1: */
+ 0x10, 0xff, 0xfe, /* l32r a0, entry_pc */
+ 0x12, 0xff, 0xfe, /* l32r a2, entry_a2 */
+ 0x0a, 0x00, 0x00, /* jx a0 */
#else
- 0xa0, 0, 0,
+ 0x06, 0x02, 0x00, /* j 1f */
+ 0x00, /* .literal_position */
+ 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */
+ 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */
+ /* 1: */
+ 0x01, 0xfe, 0xff, /* l32r a0, entry_pc */
+ 0x21, 0xfe, 0xff, /* l32r a2, entry_a2 */
+ 0xa0, 0x00, 0x00, /* jx a0 */
#endif
};
- env->regs[0] = entry_point;
- cpu_physical_memory_write(env->pc, jx_a0, sizeof(jx_a0));
+ uint32_t entry_pc = tswap32(entry_point);
+ uint32_t entry_a2 = tswap32(tagptr);
+
+ memcpy(boot + 4, &entry_pc, sizeof(entry_pc));
+ memcpy(boot + 8, &entry_a2, sizeof(entry_a2));
+ cpu_physical_memory_write(env->pc, boot, sizeof(boot));
}
} else {
if (flash) {
MemoryRegion *flash_mr = pflash_cfi01_get_memory(flash);
MemoryRegion *flash_io = g_malloc(sizeof(*flash_io));
+ uint32_t size = env->config->sysrom.location[0].size;
- memory_region_init_alias(flash_io, NULL, "lx60.flash",
- flash_mr, board->flash_boot_base,
- board->flash_size - board->flash_boot_base < 0x02000000 ?
- board->flash_size - board->flash_boot_base : 0x02000000);
- memory_region_add_subregion(system_memory, 0xfe000000,
- flash_io);
+ if (board->flash->size - board->flash->boot_base < size) {
+ size = board->flash->size - board->flash->boot_base;
+ }
+
+ memory_region_init_alias(flash_io, NULL, "xtfpga.flash",
+ flash_mr, board->flash->boot_base, size);
+ memory_region_add_subregion(system_memory,
+ env->config->sysrom.location[0].addr,
+ flash_io);
+ } else {
+ xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom",
+ system_memory);
}
}
}
-static void xtensa_lx60_init(MachineState *machine)
+static const hwaddr xtfpga_mmu_io[2] = {
+ 0xf0000000,
+};
+
+static const hwaddr xtfpga_nommu_io[2] = {
+ 0x90000000,
+ 0x70000000,
+};
+
+static const XtfpgaFlashDesc lx60_flash = {
+ .base = 0x08000000,
+ .size = 0x00400000,
+ .sector_size = 0x10000,
+};
+
+static void xtfpga_lx60_init(MachineState *machine)
{
- static const LxBoardDesc lx60_board = {
- .flash_base = 0x08000000,
- .flash_size = 0x00400000,
- .flash_sector_size = 0x10000,
+ static const XtfpgaBoardDesc lx60_board = {
+ .flash = &lx60_flash,
.sram_size = 0x20000,
+ .io = xtfpga_mmu_io,
};
- lx_init(&lx60_board, machine);
+ xtfpga_init(&lx60_board, machine);
}
-static void xtensa_lx200_init(MachineState *machine)
+static void xtfpga_lx60_nommu_init(MachineState *machine)
{
- static const LxBoardDesc lx200_board = {
- .flash_base = 0x08000000,
- .flash_size = 0x01000000,
- .flash_sector_size = 0x20000,
- .sram_size = 0x2000000,
+ static const XtfpgaBoardDesc lx60_board = {
+ .flash = &lx60_flash,
+ .sram_size = 0x20000,
+ .io = xtfpga_nommu_io,
};
- lx_init(&lx200_board, machine);
+ xtfpga_init(&lx60_board, machine);
}
-static void xtensa_ml605_init(MachineState *machine)
+static const XtfpgaFlashDesc lx200_flash = {
+ .base = 0x08000000,
+ .size = 0x01000000,
+ .sector_size = 0x20000,
+};
+
+static void xtfpga_lx200_init(MachineState *machine)
{
- static const LxBoardDesc ml605_board = {
- .flash_base = 0x08000000,
- .flash_size = 0x01000000,
- .flash_sector_size = 0x20000,
+ static const XtfpgaBoardDesc lx200_board = {
+ .flash = &lx200_flash,
.sram_size = 0x2000000,
+ .io = xtfpga_mmu_io,
};
- lx_init(&ml605_board, machine);
+ xtfpga_init(&lx200_board, machine);
}
-static void xtensa_kc705_init(MachineState *machine)
+static void xtfpga_lx200_nommu_init(MachineState *machine)
{
- static const LxBoardDesc kc705_board = {
- .flash_base = 0x00000000,
- .flash_size = 0x08000000,
- .flash_boot_base = 0x06000000,
- .flash_sector_size = 0x20000,
+ static const XtfpgaBoardDesc lx200_board = {
+ .flash = &lx200_flash,
.sram_size = 0x2000000,
+ .io = xtfpga_nommu_io,
};
- lx_init(&kc705_board, machine);
+ xtfpga_init(&lx200_board, machine);
}
-static void xtensa_lx60_class_init(ObjectClass *oc, void *data)
+static const XtfpgaFlashDesc ml605_flash = {
+ .base = 0x08000000,
+ .size = 0x01000000,
+ .sector_size = 0x20000,
+};
+
+static void xtfpga_ml605_init(MachineState *machine)
+{
+ static const XtfpgaBoardDesc ml605_board = {
+ .flash = &ml605_flash,
+ .sram_size = 0x2000000,
+ .io = xtfpga_mmu_io,
+ };
+ xtfpga_init(&ml605_board, machine);
+}
+
+static void xtfpga_ml605_nommu_init(MachineState *machine)
+{
+ static const XtfpgaBoardDesc ml605_board = {
+ .flash = &ml605_flash,
+ .sram_size = 0x2000000,
+ .io = xtfpga_nommu_io,
+ };
+ xtfpga_init(&ml605_board, machine);
+}
+
+static const XtfpgaFlashDesc kc705_flash = {
+ .base = 0x00000000,
+ .size = 0x08000000,
+ .boot_base = 0x06000000,
+ .sector_size = 0x20000,
+};
+
+static void xtfpga_kc705_init(MachineState *machine)
+{
+ static const XtfpgaBoardDesc kc705_board = {
+ .flash = &kc705_flash,
+ .sram_size = 0x2000000,
+ .io = xtfpga_mmu_io,
+ };
+ xtfpga_init(&kc705_board, machine);
+}
+
+static void xtfpga_kc705_nommu_init(MachineState *machine)
+{
+ static const XtfpgaBoardDesc kc705_board = {
+ .flash = &kc705_flash,
+ .sram_size = 0x2000000,
+ .io = xtfpga_nommu_io,
+ };
+ xtfpga_init(&kc705_board, machine);
+}
+
+static void xtfpga_lx60_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "lx60 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
- mc->init = xtensa_lx60_init;
+ mc->init = xtfpga_lx60_init;
mc->max_cpus = 4;
mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
}
-static const TypeInfo xtensa_lx60_type = {
+static const TypeInfo xtfpga_lx60_type = {
.name = MACHINE_TYPE_NAME("lx60"),
.parent = TYPE_MACHINE,
- .class_init = xtensa_lx60_class_init,
+ .class_init = xtfpga_lx60_class_init,
};
-static void xtensa_lx200_class_init(ObjectClass *oc, void *data)
+static void xtfpga_lx60_nommu_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ mc->desc = "lx60 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")";
+ mc->init = xtfpga_lx60_nommu_init;
+ mc->max_cpus = 4;
+ mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE;
+}
+
+static const TypeInfo xtfpga_lx60_nommu_type = {
+ .name = MACHINE_TYPE_NAME("lx60-nommu"),
+ .parent = TYPE_MACHINE,
+ .class_init = xtfpga_lx60_nommu_class_init,
+};
+
+static void xtfpga_lx200_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "lx200 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
- mc->init = xtensa_lx200_init;
+ mc->init = xtfpga_lx200_init;
mc->max_cpus = 4;
mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
}
-static const TypeInfo xtensa_lx200_type = {
+static const TypeInfo xtfpga_lx200_type = {
.name = MACHINE_TYPE_NAME("lx200"),
.parent = TYPE_MACHINE,
- .class_init = xtensa_lx200_class_init,
+ .class_init = xtfpga_lx200_class_init,
};
-static void xtensa_ml605_class_init(ObjectClass *oc, void *data)
+static void xtfpga_lx200_nommu_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ mc->desc = "lx200 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")";
+ mc->init = xtfpga_lx200_nommu_init;
+ mc->max_cpus = 4;
+ mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE;
+}
+
+static const TypeInfo xtfpga_lx200_nommu_type = {
+ .name = MACHINE_TYPE_NAME("lx200-nommu"),
+ .parent = TYPE_MACHINE,
+ .class_init = xtfpga_lx200_nommu_class_init,
+};
+
+static void xtfpga_ml605_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "ml605 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
- mc->init = xtensa_ml605_init;
+ mc->init = xtfpga_ml605_init;
mc->max_cpus = 4;
mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
}
-static const TypeInfo xtensa_ml605_type = {
+static const TypeInfo xtfpga_ml605_type = {
.name = MACHINE_TYPE_NAME("ml605"),
.parent = TYPE_MACHINE,
- .class_init = xtensa_ml605_class_init,
+ .class_init = xtfpga_ml605_class_init,
};
-static void xtensa_kc705_class_init(ObjectClass *oc, void *data)
+static void xtfpga_ml605_nommu_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ mc->desc = "ml605 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")";
+ mc->init = xtfpga_ml605_nommu_init;
+ mc->max_cpus = 4;
+ mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE;
+}
+
+static const TypeInfo xtfpga_ml605_nommu_type = {
+ .name = MACHINE_TYPE_NAME("ml605-nommu"),
+ .parent = TYPE_MACHINE,
+ .class_init = xtfpga_ml605_nommu_class_init,
+};
+
+static void xtfpga_kc705_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "kc705 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
- mc->init = xtensa_kc705_init;
+ mc->init = xtfpga_kc705_init;
mc->max_cpus = 4;
mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
}
-static const TypeInfo xtensa_kc705_type = {
+static const TypeInfo xtfpga_kc705_type = {
.name = MACHINE_TYPE_NAME("kc705"),
.parent = TYPE_MACHINE,
- .class_init = xtensa_kc705_class_init,
+ .class_init = xtfpga_kc705_class_init,
};
-static void xtensa_lx_machines_init(void)
+static void xtfpga_kc705_nommu_class_init(ObjectClass *oc, void *data)
{
- type_register_static(&xtensa_lx60_type);
- type_register_static(&xtensa_lx200_type);
- type_register_static(&xtensa_ml605_type);
- type_register_static(&xtensa_kc705_type);
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ mc->desc = "kc705 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")";
+ mc->init = xtfpga_kc705_nommu_init;
+ mc->max_cpus = 4;
+ mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE;
}
-type_init(xtensa_lx_machines_init)
+static const TypeInfo xtfpga_kc705_nommu_type = {
+ .name = MACHINE_TYPE_NAME("kc705-nommu"),
+ .parent = TYPE_MACHINE,
+ .class_init = xtfpga_kc705_nommu_class_init,
+};
+
+static void xtfpga_machines_init(void)
+{
+ type_register_static(&xtfpga_lx60_type);
+ type_register_static(&xtfpga_lx200_type);
+ type_register_static(&xtfpga_ml605_type);
+ type_register_static(&xtfpga_kc705_type);
+ type_register_static(&xtfpga_lx60_nommu_type);
+ type_register_static(&xtfpga_lx200_nommu_type);
+ type_register_static(&xtfpga_ml605_nommu_type);
+ type_register_static(&xtfpga_kc705_nommu_type);
+}
+
+type_init(xtfpga_machines_init)
diff --git a/include/qemu/event_notifier.h b/include/qemu/event_notifier.h
index b30a454..599c99f 100644
--- a/include/qemu/event_notifier.h
+++ b/include/qemu/event_notifier.h
@@ -26,7 +26,6 @@
int rfd;
int wfd;
#endif
- void (*cleanup)(EventNotifier *);
};
typedef void EventNotifierHandler(EventNotifier *);
diff --git a/include/standard-headers/asm-s390/virtio-ccw.h b/include/standard-headers/asm-s390/virtio-ccw.h
index 967aad3..2b605f7 100644
--- a/include/standard-headers/asm-s390/virtio-ccw.h
+++ b/include/standard-headers/asm-s390/virtio-ccw.h
@@ -1,13 +1,9 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */
/*
* Definitions for virtio-ccw devices.
*
* Copyright IBM Corp. 2013
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License (version 2 only)
- * as published by the Free Software Foundation.
- *
* Author(s): Cornelia Huck <cornelia.huck@de.ibm.com>
*/
#ifndef __KVM_VIRTIO_CCW_H
diff --git a/linux-headers/asm-powerpc/kvm.h b/linux-headers/asm-powerpc/kvm.h
index 61d6049..637b726 100644
--- a/linux-headers/asm-powerpc/kvm.h
+++ b/linux-headers/asm-powerpc/kvm.h
@@ -443,6 +443,31 @@
__u32 ap_encodings[8];
};
+/* For KVM_PPC_GET_CPU_CHAR */
+struct kvm_ppc_cpu_char {
+ __u64 character; /* characteristics of the CPU */
+ __u64 behaviour; /* recommended software behaviour */
+ __u64 character_mask; /* valid bits in character */
+ __u64 behaviour_mask; /* valid bits in behaviour */
+};
+
+/*
+ * Values for character and character_mask.
+ * These are identical to the values used by H_GET_CPU_CHARACTERISTICS.
+ */
+#define KVM_PPC_CPU_CHAR_SPEC_BAR_ORI31 (1ULL << 63)
+#define KVM_PPC_CPU_CHAR_BCCTRL_SERIALISED (1ULL << 62)
+#define KVM_PPC_CPU_CHAR_L1D_FLUSH_ORI30 (1ULL << 61)
+#define KVM_PPC_CPU_CHAR_L1D_FLUSH_TRIG2 (1ULL << 60)
+#define KVM_PPC_CPU_CHAR_L1D_THREAD_PRIV (1ULL << 59)
+#define KVM_PPC_CPU_CHAR_BR_HINT_HONOURED (1ULL << 58)
+#define KVM_PPC_CPU_CHAR_MTTRIG_THR_RECONF (1ULL << 57)
+#define KVM_PPC_CPU_CHAR_COUNT_CACHE_DIS (1ULL << 56)
+
+#define KVM_PPC_CPU_BEHAV_FAVOUR_SECURITY (1ULL << 63)
+#define KVM_PPC_CPU_BEHAV_L1D_FLUSH_PR (1ULL << 62)
+#define KVM_PPC_CPU_BEHAV_BNDS_CHK_SPEC_BAR (1ULL << 61)
+
/* Per-vcpu XICS interrupt controller state */
#define KVM_REG_PPC_ICP_STATE (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8c)
diff --git a/linux-headers/asm-s390/kvm.h b/linux-headers/asm-s390/kvm.h
index 32d372e..11def14 100644
--- a/linux-headers/asm-s390/kvm.h
+++ b/linux-headers/asm-s390/kvm.h
@@ -6,10 +6,6 @@
*
* Copyright IBM Corp. 2008
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License (version 2 only)
- * as published by the Free Software Foundation.
- *
* Author(s): Carsten Otte <cotte@de.ibm.com>
* Christian Borntraeger <borntraeger@de.ibm.com>
*/
@@ -228,6 +224,7 @@
#define KVM_SYNC_RICCB (1UL << 7)
#define KVM_SYNC_FPRS (1UL << 8)
#define KVM_SYNC_GSCB (1UL << 9)
+#define KVM_SYNC_BPBC (1UL << 10)
/* length and alignment of the sdnx as a power of two */
#define SDNXC 8
#define SDNXL (1UL << SDNXC)
@@ -251,7 +248,9 @@
};
__u8 reserved[512]; /* for future vector expansion */
__u32 fpc; /* valid on KVM_SYNC_VRS or KVM_SYNC_FPRS */
- __u8 padding1[52]; /* riccb needs to be 64byte aligned */
+ __u8 bpbc : 1; /* bp mode */
+ __u8 reserved2 : 7;
+ __u8 padding1[51]; /* riccb needs to be 64byte aligned */
__u8 riccb[64]; /* runtime instrumentation controls block */
__u8 padding2[192]; /* sdnx needs to be 256byte aligned */
union {
diff --git a/linux-headers/asm-s390/kvm_para.h b/linux-headers/asm-s390/kvm_para.h
index 0dc86b3..b9ab584 100644
--- a/linux-headers/asm-s390/kvm_para.h
+++ b/linux-headers/asm-s390/kvm_para.h
@@ -4,9 +4,5 @@
*
* Copyright IBM Corp. 2008
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License (version 2 only)
- * as published by the Free Software Foundation.
- *
* Author(s): Christian Borntraeger <borntraeger@de.ibm.com>
*/
diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
index ce6c2f1..d92c9b2 100644
--- a/linux-headers/linux/kvm.h
+++ b/linux-headers/linux/kvm.h
@@ -630,9 +630,9 @@
struct kvm_s390_irq_state {
__u64 buf;
- __u32 flags;
+ __u32 flags; /* will stay unused for compatibility reasons */
__u32 len;
- __u32 reserved[4];
+ __u32 reserved[4]; /* will stay unused for compatibility reasons */
};
/* for KVM_SET_GUEST_DEBUG */
@@ -932,6 +932,8 @@
#define KVM_CAP_HYPERV_SYNIC2 148
#define KVM_CAP_HYPERV_VP_INDEX 149
#define KVM_CAP_S390_AIS_MIGRATION 150
+#define KVM_CAP_PPC_GET_CPU_CHAR 151
+#define KVM_CAP_S390_BPB 152
#ifdef KVM_CAP_IRQ_ROUTING
@@ -1261,6 +1263,8 @@
#define KVM_PPC_CONFIGURE_V3_MMU _IOW(KVMIO, 0xaf, struct kvm_ppc_mmuv3_cfg)
/* Available with KVM_CAP_PPC_RADIX_MMU */
#define KVM_PPC_GET_RMMU_INFO _IOW(KVMIO, 0xb0, struct kvm_ppc_rmmu_info)
+/* Available with KVM_CAP_PPC_GET_CPU_CHAR */
+#define KVM_PPC_GET_CPU_CHAR _IOR(KVMIO, 0xb1, struct kvm_ppc_cpu_char)
/* ioctl for vm fd */
#define KVM_CREATE_DEVICE _IOWR(KVMIO, 0xe0, struct kvm_create_device)
diff --git a/qapi/block-core.json b/qapi/block-core.json
index e94a688..8225308 100644
--- a/qapi/block-core.json
+++ b/qapi/block-core.json
@@ -1799,6 +1799,24 @@
# Example:
#
# -> { "execute": "block_set_io_throttle",
+# "arguments": { "id": "virtio-blk-pci0/virtio-backend",
+# "bps": 0,
+# "bps_rd": 0,
+# "bps_wr": 0,
+# "iops": 512,
+# "iops_rd": 0,
+# "iops_wr": 0,
+# "bps_max": 0,
+# "bps_rd_max": 0,
+# "bps_wr_max": 0,
+# "iops_max": 0,
+# "iops_rd_max": 0,
+# "iops_wr_max": 0,
+# "bps_max_length": 0,
+# "iops_size": 0 } }
+# <- { "return": {} }
+#
+# -> { "execute": "block_set_io_throttle",
# "arguments": { "id": "ide0-1-0",
# "bps": 1000000,
# "bps_rd": 0,
@@ -3403,7 +3421,7 @@
'*id': 'str' } }
##
-# @x-blockdev-remove-medium:
+# @blockdev-remove-medium:
#
# Removes a medium (a block driver state tree) from a block device. That block
# device's tray must currently be open (unless there is no attached guest
@@ -3411,18 +3429,13 @@
#
# If the tray is open and there is no medium inserted, this will be a no-op.
#
-# @device: Block device name (deprecated, use @id instead)
+# @id: The name or QOM path of the guest device
#
-# @id: The name or QOM path of the guest device (since: 2.8)
-#
-# Note: This command is still a work in progress and is considered experimental.
-# Stay away from it unless you want to help with its development.
-#
-# Since: 2.5
+# Since: 2.12
#
# Example:
#
-# -> { "execute": "x-blockdev-remove-medium",
+# -> { "execute": "blockdev-remove-medium",
# "arguments": { "id": "ide0-1-0" } }
#
# <- { "error": { "class": "GenericError",
@@ -3440,33 +3453,27 @@
#
# <- { "return": {} }
#
-# -> { "execute": "x-blockdev-remove-medium",
+# -> { "execute": "blockdev-remove-medium",
# "arguments": { "id": "ide0-1-0" } }
#
# <- { "return": {} }
#
##
-{ 'command': 'x-blockdev-remove-medium',
- 'data': { '*device': 'str',
- '*id': 'str' } }
+{ 'command': 'blockdev-remove-medium',
+ 'data': { 'id': 'str' } }
##
-# @x-blockdev-insert-medium:
+# @blockdev-insert-medium:
#
# Inserts a medium (a block driver state tree) into a block device. That block
# device's tray must currently be open (unless there is no attached guest
# device) and there must be no medium inserted already.
#
-# @device: Block device name (deprecated, use @id instead)
-#
-# @id: The name or QOM path of the guest device (since: 2.8)
+# @id: The name or QOM path of the guest device
#
# @node-name: name of a node in the block driver state graph
#
-# Note: This command is still a work in progress and is considered experimental.
-# Stay away from it unless you want to help with its development.
-#
-# Since: 2.5
+# Since: 2.12
#
# Example:
#
@@ -3478,16 +3485,15 @@
# "filename": "fedora.iso" } } }
# <- { "return": {} }
#
-# -> { "execute": "x-blockdev-insert-medium",
+# -> { "execute": "blockdev-insert-medium",
# "arguments": { "id": "ide0-1-0",
# "node-name": "node0" } }
#
# <- { "return": {} }
#
##
-{ 'command': 'x-blockdev-insert-medium',
- 'data': { '*device': 'str',
- '*id': 'str',
+{ 'command': 'blockdev-insert-medium',
+ 'data': { 'id': 'str',
'node-name': 'str'} }
@@ -3515,8 +3521,8 @@
#
# Changes the medium inserted into a block device by ejecting the current medium
# and loading a new image file which is inserted as the new medium (this command
-# combines blockdev-open-tray, x-blockdev-remove-medium,
-# x-blockdev-insert-medium and blockdev-close-tray).
+# combines blockdev-open-tray, blockdev-remove-medium, blockdev-insert-medium
+# and blockdev-close-tray).
#
# @device: Block device name (deprecated, use @id instead)
#
diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
index accba24..1b4b812 100755
--- a/scripts/checkpatch.pl
+++ b/scripts/checkpatch.pl
@@ -265,6 +265,7 @@
qr{${Ident}_handler_fn},
qr{target_(?:u)?long},
qr{hwaddr},
+ qr{xml${Ident}},
);
# This can be modified by sub possible. Since it can be empty, be careful
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index ae3cee9..d2e6b9f 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -89,6 +89,7 @@
CPUS390XState *env = &cpu->env;
env->pfault_token = -1UL;
+ env->bpbc = false;
scc->parent_reset(s);
cpu->env.sigp_order = 0;
s390_cpu_set_state(CPU_STATE_STOPPED, cpu);
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index 1a8b6b9..a1123ad 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -93,6 +93,7 @@
uint32_t fpc; /* floating-point control register */
uint32_t cc_op;
+ bool bpbc; /* branch prediction blocking */
float_status fpu_status; /* passed to softfloat lib */
@@ -759,6 +760,8 @@
s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false)
#define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len) \
s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true)
+#define s390_cpu_virt_mem_check_read(cpu, laddr, ar, len) \
+ s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, false)
#define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len) \
s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true)
void s390_cpu_virt_mem_handle_exc(S390CPU *cpu, uintptr_t ra);
diff --git a/target/s390x/cpu_features.c b/target/s390x/cpu_features.c
index 31a4676..85d10b5 100644
--- a/target/s390x/cpu_features.c
+++ b/target/s390x/cpu_features.c
@@ -89,6 +89,8 @@
FEAT_INIT("msa4-base", S390_FEAT_TYPE_STFL, 77, "Message-security-assist-extension-4 facility (excluding subfunctions)"),
FEAT_INIT("edat2", S390_FEAT_TYPE_STFL, 78, "Enhanced-DAT facility 2"),
FEAT_INIT("dfppc", S390_FEAT_TYPE_STFL, 80, "Decimal-floating-point packed-conversion facility"),
+ FEAT_INIT("ppa15", S390_FEAT_TYPE_STFL, 81, "PPA15 is installed"),
+ FEAT_INIT("bpb", S390_FEAT_TYPE_STFL, 82, "Branch prediction blocking"),
FEAT_INIT("vx", S390_FEAT_TYPE_STFL, 129, "Vector facility"),
FEAT_INIT("iep", S390_FEAT_TYPE_STFL, 130, "Instruction-execution-protection facility"),
FEAT_INIT("sea_esop2", S390_FEAT_TYPE_STFL, 131, "Side-effect-access facility and Enhanced-suppression-on-protection facility 2"),
diff --git a/target/s390x/cpu_features_def.h b/target/s390x/cpu_features_def.h
index 4b6d4e9..4d93087 100644
--- a/target/s390x/cpu_features_def.h
+++ b/target/s390x/cpu_features_def.h
@@ -80,6 +80,8 @@
S390_FEAT_MSA_EXT_4,
S390_FEAT_EDAT_2,
S390_FEAT_DFP_PACKED_CONVERSION,
+ S390_FEAT_PPA15,
+ S390_FEAT_BPB,
S390_FEAT_VECTOR,
S390_FEAT_INSTRUCTION_EXEC_PROT,
S390_FEAT_SIDE_EFFECT_ACCESS_ESOP2,
diff --git a/target/s390x/gen-features.c b/target/s390x/gen-features.c
index b24f6ad..0570f59 100644
--- a/target/s390x/gen-features.c
+++ b/target/s390x/gen-features.c
@@ -352,6 +352,8 @@
* support these features yet.
*/
static uint16_t full_GEN7_GA1[] = {
+ S390_FEAT_PPA15,
+ S390_FEAT_BPB,
S390_FEAT_SIE_F2,
S390_FEAT_SIE_SKEY,
S390_FEAT_SIE_GPERE,
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 2f17b62..59a1d98 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -137,7 +137,7 @@
DEF_HELPER_FLAGS_4(stctl, TCG_CALL_NO_WG, void, env, i32, i64, i32)
DEF_HELPER_FLAGS_4(stctg, TCG_CALL_NO_WG, void, env, i32, i64, i32)
DEF_HELPER_FLAGS_2(testblock, TCG_CALL_NO_WG, i32, env, i64)
-DEF_HELPER_FLAGS_2(tprot, TCG_CALL_NO_RWG, i32, i64, i64)
+DEF_HELPER_FLAGS_3(tprot, TCG_CALL_NO_WG, i32, env, i64, i64)
DEF_HELPER_FLAGS_2(iske, TCG_CALL_NO_RWG_SE, i64, env, i64)
DEF_HELPER_FLAGS_3(sske, TCG_CALL_NO_RWG, void, env, i64, i64)
DEF_HELPER_FLAGS_2(rrbe, TCG_CALL_NO_RWG, i32, env, i64)
diff --git a/target/s390x/kvm.c b/target/s390x/kvm.c
index 6a18a41..8736001 100644
--- a/target/s390x/kvm.c
+++ b/target/s390x/kvm.c
@@ -490,6 +490,11 @@
cs->kvm_run->kvm_dirty_regs |= KVM_SYNC_GSCB;
}
+ if (can_sync_regs(cs, KVM_SYNC_BPBC)) {
+ cs->kvm_run->s.regs.bpbc = env->bpbc;
+ cs->kvm_run->kvm_dirty_regs |= KVM_SYNC_BPBC;
+ }
+
/* Finally the prefix */
if (can_sync_regs(cs, KVM_SYNC_PREFIX)) {
cs->kvm_run->s.regs.prefix = env->psa;
@@ -600,6 +605,10 @@
memcpy(env->gscb, cs->kvm_run->s.regs.gscb, 32);
}
+ if (can_sync_regs(cs, KVM_SYNC_BPBC)) {
+ env->bpbc = cs->kvm_run->s.regs.bpbc;
+ }
+
/* pfault parameters */
if (can_sync_regs(cs, KVM_SYNC_PFAULT)) {
env->pfault_token = cs->kvm_run->s.regs.pft;
@@ -2278,6 +2287,11 @@
clear_bit(S390_FEAT_CMM_NT, model->features);
}
+ /* bpb needs kernel support for migration, VSIE and reset */
+ if (!kvm_check_extension(kvm_state, KVM_CAP_S390_BPB)) {
+ clear_bit(S390_FEAT_BPB, model->features);
+ }
+
/* We emulate a zPCI bus and AEN, therefore we don't need HW support */
if (pci_available) {
set_bit(S390_FEAT_ZPCI, model->features);
diff --git a/target/s390x/machine.c b/target/s390x/machine.c
index b78f326..84b4928 100644
--- a/target/s390x/machine.c
+++ b/target/s390x/machine.c
@@ -194,6 +194,22 @@
}
};
+static bool bpbc_needed(void *opaque)
+{
+ return s390_has_feat(S390_FEAT_BPB);
+}
+
+const VMStateDescription vmstate_bpbc = {
+ .name = "cpu/bpbc",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = bpbc_needed,
+ .fields = (VMStateField[]) {
+ VMSTATE_BOOL(env.bpbc, S390CPU),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
const VMStateDescription vmstate_s390_cpu = {
.name = "cpu",
.post_load = cpu_post_load,
@@ -228,6 +244,7 @@
&vmstate_riccb,
&vmstate_exval,
&vmstate_gscb,
+ &vmstate_bpbc,
NULL
},
};
diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c
index 2625d84..c957feb 100644
--- a/target/s390x/mem_helper.c
+++ b/target/s390x/mem_helper.c
@@ -1717,10 +1717,44 @@
return 0;
}
-uint32_t HELPER(tprot)(uint64_t a1, uint64_t a2)
+uint32_t HELPER(tprot)(CPUS390XState *env, uint64_t a1, uint64_t a2)
{
- /* XXX implement */
- return 0;
+ S390CPU *cpu = s390_env_get_cpu(env);
+ CPUState *cs = CPU(cpu);
+
+ /*
+ * TODO: we currently don't handle all access protection types
+ * (including access-list and key-controlled) as well as AR mode.
+ */
+ if (!s390_cpu_virt_mem_check_write(cpu, a1, 0, 1)) {
+ /* Fetching permitted; storing permitted */
+ return 0;
+ }
+
+ if (env->int_pgm_code == PGM_PROTECTION) {
+ /* retry if reading is possible */
+ cs->exception_index = 0;
+ if (!s390_cpu_virt_mem_check_read(cpu, a1, 0, 1)) {
+ /* Fetching permitted; storing not permitted */
+ return 1;
+ }
+ }
+
+ switch (env->int_pgm_code) {
+ case PGM_PROTECTION:
+ /* Fetching not permitted; storing not permitted */
+ cs->exception_index = 0;
+ return 2;
+ case PGM_ADDRESSING:
+ case PGM_TRANS_SPEC:
+ /* exceptions forwarded to the guest */
+ s390_cpu_virt_mem_handle_exc(cpu, GETPC());
+ return 0;
+ }
+
+ /* Translation not available */
+ cs->exception_index = 0;
+ return 3;
}
/* insert storage key extended */
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index ac55886..df0b416 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -4532,7 +4532,7 @@
static ExitStatus op_tprot(DisasContext *s, DisasOps *o)
{
- gen_helper_tprot(cc_op, o->addr1, o->in2);
+ gen_helper_tprot(cc_op, cpu_env, o->addr1, o->in2);
set_cc_static(s);
return NO_EXIT;
}
diff --git a/target/xtensa/Makefile.objs b/target/xtensa/Makefile.objs
index 0429706..e158515 100644
--- a/target/xtensa/Makefile.objs
+++ b/target/xtensa/Makefile.objs
@@ -1,7 +1,9 @@
obj-y += xtensa-semi.o
obj-y += core-dc232b.o
obj-y += core-dc233c.o
+obj-y += core-de212.o
obj-y += core-fsf.o
+obj-y += core-sample_controller.o
obj-$(CONFIG_SOFTMMU) += monitor.o
obj-y += xtensa-isa.o
obj-y += translate.o op_helper.o helper.o cpu.o
diff --git a/target/xtensa/core-de212.c b/target/xtensa/core-de212.c
new file mode 100644
index 0000000..466a467
--- /dev/null
+++ b/target/xtensa/core-de212.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2018, Max Filippov, Open Source and Linux Lab.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the Open Source and Linux Lab nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "exec/exec-all.h"
+#include "exec/gdbstub.h"
+#include "qemu-common.h"
+#include "qemu/host-utils.h"
+
+#include "core-de212/core-isa.h"
+#include "overlay_tool.h"
+
+#define xtensa_modules xtensa_modules_de212
+#include "core-de212/xtensa-modules.c"
+
+static XtensaConfig de212 __attribute__((unused)) = {
+ .name = "de212",
+ .gdb_regmap = {
+ .reg = {
+#include "core-de212/gdb-config.c"
+ }
+ },
+ .isa_internal = &xtensa_modules,
+ .clock_freq_khz = 40000,
+ DEFAULT_SECTIONS
+};
+
+REGISTER_CORE(de212)
diff --git a/target/xtensa/core-de212/core-isa.h b/target/xtensa/core-de212/core-isa.h
new file mode 100644
index 0000000..78e7f38
--- /dev/null
+++ b/target/xtensa/core-de212/core-isa.h
@@ -0,0 +1,622 @@
+/*
+ * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
+ * processor CORE configuration
+ *
+ * See <xtensa/config/core.h>, which includes this file, for more details.
+ */
+
+/* Xtensa processor core configuration information.
+
+ Copyright (c) 1999-2015 Tensilica Inc.
+
+ Permission is hereby granted, free of charge, to any person obtaining
+ a copy of this software and associated documentation files (the
+ "Software"), to deal in the Software without restriction, including
+ without limitation the rights to use, copy, modify, merge, publish,
+ distribute, sublicense, and/or sell copies of the Software, and to
+ permit persons to whom the Software is furnished to do so, subject to
+ the following conditions:
+
+ The above copyright notice and this permission notice shall be included
+ in all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+#ifndef _XTENSA_CORE_CONFIGURATION_H
+#define _XTENSA_CORE_CONFIGURATION_H
+
+
+/****************************************************************************
+ Parameters Useful for Any Code, USER or PRIVILEGED
+ ****************************************************************************/
+
+/*
+ * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
+ * configured, and a value of 0 otherwise. These macros are always defined.
+ */
+
+
+/*----------------------------------------------------------------------
+ ISA
+ ----------------------------------------------------------------------*/
+
+#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
+#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
+#define XCHAL_NUM_AREGS 32 /* num of physical addr regs */
+#define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */
+#define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */
+#define XCHAL_HAVE_DEBUG 1 /* debug option */
+#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
+#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
+#define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */
+#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
+#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
+#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
+#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */
+#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */
+#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
+#define XCHAL_HAVE_MUL32 1 /* MULL instruction */
+#define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */
+#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */
+#define XCHAL_HAVE_L32R 1 /* L32R instruction */
+#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */
+#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
+#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
+#define XCHAL_HAVE_EXCLUSIVE 0 /* L32EX/S32EX instructions */
+#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
+#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
+#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
+#define XCHAL_HAVE_ABS 1 /* ABS instruction */
+/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */
+/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */
+#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */
+#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */
+#define XCHAL_HAVE_SPECULATION 0 /* speculation */
+#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */
+#define XCHAL_NUM_CONTEXTS 1 /* */
+#define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */
+#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
+#define XCHAL_HAVE_PRID 1 /* processor ID register */
+#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */
+#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */
+#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */
+#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */
+#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */
+#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */
+#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */
+#define XCHAL_HAVE_THREADPTR 0 /* THREADPTR register */
+#define XCHAL_HAVE_BOOLEANS 0 /* boolean registers */
+#define XCHAL_HAVE_CP 0 /* CPENABLE reg (coprocessor) */
+#define XCHAL_CP_MAXCFG 0 /* max allowed cp id plus one */
+#define XCHAL_HAVE_MAC16 1 /* MAC16 package */
+
+#define XCHAL_HAVE_FUSION 0 /* Fusion*/
+#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */
+#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */
+#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */
+#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */
+#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */
+#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */
+#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */
+#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */
+#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */
+#define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */
+#define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */
+#define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */
+#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */
+#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */
+#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */
+#define XCHAL_HAVE_HIFI_MINI 0
+
+
+
+#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
+#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */
+#define XCHAL_HAVE_USER_SPFPU 0 /* user DP floating-point pkg */
+#define XCHAL_HAVE_FP 0 /* single prec floating point */
+#define XCHAL_HAVE_FP_DIV 0 /* FP with DIV instructions */
+#define XCHAL_HAVE_FP_RECIP 0 /* FP with RECIP instructions */
+#define XCHAL_HAVE_FP_SQRT 0 /* FP with SQRT instructions */
+#define XCHAL_HAVE_FP_RSQRT 0 /* FP with RSQRT instructions */
+#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */
+#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */
+#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/
+#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */
+#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/
+#define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */
+#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */
+
+#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */
+#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */
+#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
+#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
+#define XCHAL_HAVE_PDX4 0 /* PDX4 */
+#define XCHAL_HAVE_PDX8 0 /* PDX8 */
+#define XCHAL_HAVE_PDX16 0 /* PDX16 */
+#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */
+#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */
+#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */
+#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */
+#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */
+#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */
+#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */
+#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */
+#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */
+#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */
+#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */
+#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */
+#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */
+#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */
+#define XCHAL_HAVE_GRIVPEP 0 /* General Release of IVPEP */
+#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */
+
+#define XCHAL_HAVE_VISION 0 /* Vision */
+#define XCHAL_VISION_TYPE 0 /* Vision P5 or P3 */
+#define XCHAL_VISION_SIMD16 0 /* Vision simd16 */
+#define XCHAL_HAVE_VISION_HISTOGRAM 0 /* histogram option on Vision */
+#define XCHAL_HAVE_VISION_SP_VFPU 0 /* sp_vfpu option on Vision */
+
+
+/*----------------------------------------------------------------------
+ MISC
+ ----------------------------------------------------------------------*/
+
+#define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */
+#define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */
+#define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */
+#define XCHAL_DATA_WIDTH 4 /* data width in bytes */
+#define XCHAL_DATA_PIPE_DELAY 1 /* d-side pipeline delay
+ (1 = 5-stage, 2 = 7-stage) */
+#define XCHAL_CLOCK_GATING_GLOBAL 0 /* global clock gating */
+#define XCHAL_CLOCK_GATING_FUNCUNIT 0 /* funct. unit clock gating */
+/* In T1050, applies to selected core load and store instructions (see ISA): */
+#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */
+#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/
+#define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */
+#define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/
+
+#define XCHAL_SW_VERSION 1200000 /* sw version of this header */
+
+#define XCHAL_CORE_ID "de212_371077" /* alphanum core name
+ (CoreID) set in the Xtensa
+ Processor Generator */
+
+#define XCHAL_BUILD_UNIQUE_ID 0x0005A9EB /* 22-bit sw build ID */
+
+/*
+ * These definitions describe the hardware targeted by this software.
+ */
+#define XCHAL_HW_CONFIGID0 0xC283DFFE /* ConfigID hi 32 bits*/
+#define XCHAL_HW_CONFIGID1 0x1C85A985 /* ConfigID lo 32 bits*/
+#define XCHAL_HW_VERSION_NAME "LX6.0.2" /* full version name */
+#define XCHAL_HW_VERSION_MAJOR 2600 /* major ver# of targeted hw */
+#define XCHAL_HW_VERSION_MINOR 2 /* minor ver# of targeted hw */
+#define XCHAL_HW_VERSION 260002 /* major*100+minor */
+#define XCHAL_HW_REL_LX6 1
+#define XCHAL_HW_REL_LX6_0 1
+#define XCHAL_HW_REL_LX6_0_2 1
+#define XCHAL_HW_CONFIGID_RELIABLE 1
+/* If software targets a *range* of hardware versions, these are the bounds: */
+#define XCHAL_HW_MIN_VERSION_MAJOR 2600 /* major v of earliest tgt hw */
+#define XCHAL_HW_MIN_VERSION_MINOR 2 /* minor v of earliest tgt hw */
+#define XCHAL_HW_MIN_VERSION 260002 /* earliest targeted hw */
+#define XCHAL_HW_MAX_VERSION_MAJOR 2600 /* major v of latest tgt hw */
+#define XCHAL_HW_MAX_VERSION_MINOR 2 /* minor v of latest tgt hw */
+#define XCHAL_HW_MAX_VERSION 260002 /* latest targeted hw */
+
+
+/*----------------------------------------------------------------------
+ CACHE
+ ----------------------------------------------------------------------*/
+
+#define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */
+#define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */
+#define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */
+#define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */
+
+#define XCHAL_ICACHE_SIZE 8192 /* I-cache size in bytes or 0 */
+#define XCHAL_DCACHE_SIZE 8192 /* D-cache size in bytes or 0 */
+
+#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */
+#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */
+
+#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */
+#define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */
+#define XCHAL_PREFETCH_CASTOUT_LINES 0 /* dcache pref. castout bufsz */
+#define XCHAL_PREFETCH_ENTRIES 0 /* cache prefetch entries */
+#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */
+#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */
+#define XCHAL_HAVE_ICACHE_TEST 1 /* Icache test instructions */
+#define XCHAL_HAVE_DCACHE_TEST 1 /* Dcache test instructions */
+#define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */
+#define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */
+
+
+
+
+/****************************************************************************
+ Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
+ ****************************************************************************/
+
+
+#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
+
+/*----------------------------------------------------------------------
+ CACHE
+ ----------------------------------------------------------------------*/
+
+#define XCHAL_HAVE_PIF 1 /* any outbound bus present */
+#define XCHAL_HAVE_AXI 0 /* AXI bus */
+#define XCHAL_HAVE_AXI_ECC 0 /* ECC on AXI bus */
+#define XCHAL_HAVE_ACELITE 0 /* ACELite bus */
+
+/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
+
+/* Number of cache sets in log2(lines per way): */
+#define XCHAL_ICACHE_SETWIDTH 7
+#define XCHAL_DCACHE_SETWIDTH 7
+
+/* Cache set associativity (number of ways): */
+#define XCHAL_ICACHE_WAYS 2
+#define XCHAL_DCACHE_WAYS 2
+
+/* Cache features: */
+#define XCHAL_ICACHE_LINE_LOCKABLE 1
+#define XCHAL_DCACHE_LINE_LOCKABLE 1
+#define XCHAL_ICACHE_ECC_PARITY 0
+#define XCHAL_DCACHE_ECC_PARITY 0
+
+/* Cache access size in bytes (affects operation of SICW instruction): */
+#define XCHAL_ICACHE_ACCESS_SIZE 4
+#define XCHAL_DCACHE_ACCESS_SIZE 4
+
+#define XCHAL_DCACHE_BANKS 1 /* number of banks */
+
+/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
+#define XCHAL_CA_BITS 4
+
+
+/*----------------------------------------------------------------------
+ INTERNAL I/D RAM/ROMs and XLMI
+ ----------------------------------------------------------------------*/
+#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */
+#define XCHAL_NUM_INSTRAM 1 /* number of core instr. RAMs */
+#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */
+#define XCHAL_NUM_DATARAM 1 /* number of core data RAMs */
+#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
+#define XCHAL_NUM_XLMI 1 /* number of core XLMI ports */
+
+/* Instruction RAM 0: */
+#define XCHAL_INSTRAM0_VADDR 0x40000000 /* virtual address */
+#define XCHAL_INSTRAM0_PADDR 0x40000000 /* physical address */
+#define XCHAL_INSTRAM0_SIZE 131072 /* size in bytes */
+#define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
+#define XCHAL_HAVE_INSTRAM0
+#define XCHAL_INSTRAM0_HAVE_IDMA 0 /* idma supported by this local memory */
+
+/* Data RAM 0: */
+#define XCHAL_DATARAM0_VADDR 0x3FFE0000 /* virtual address */
+#define XCHAL_DATARAM0_PADDR 0x3FFE0000 /* physical address */
+#define XCHAL_DATARAM0_SIZE 131072 /* size in bytes */
+#define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
+#define XCHAL_DATARAM0_BANKS 1 /* number of banks */
+#define XCHAL_HAVE_DATARAM0
+#define XCHAL_DATARAM0_HAVE_IDMA 0 /* idma supported by this local memory */
+
+/* XLMI Port 0: */
+#define XCHAL_XLMI0_VADDR 0x3FFC0000 /* virtual address */
+#define XCHAL_XLMI0_PADDR 0x3FFC0000 /* physical address */
+#define XCHAL_XLMI0_SIZE 131072 /* size in bytes */
+#define XCHAL_XLMI0_ECC_PARITY 0 /* ECC/parity type, 0=none */
+
+#define XCHAL_HAVE_IDMA 0
+#define XCHAL_HAVE_IDMA_TRANSPOSE 0
+
+#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/
+
+
+/*----------------------------------------------------------------------
+ INTERRUPTS and TIMERS
+ ----------------------------------------------------------------------*/
+
+#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
+#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
+#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */
+#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
+#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */
+#define XCHAL_NUM_INTERRUPTS 22 /* number of interrupts */
+#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */
+#define XCHAL_NUM_EXTINTERRUPTS 17 /* num of external interrupts */
+#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels
+ (not including level zero) */
+#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */
+ /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
+
+/* Masks of interrupts at each interrupt level: */
+#define XCHAL_INTLEVEL1_MASK 0x001F80FF
+#define XCHAL_INTLEVEL2_MASK 0x00000100
+#define XCHAL_INTLEVEL3_MASK 0x00200E00
+#define XCHAL_INTLEVEL4_MASK 0x00001000
+#define XCHAL_INTLEVEL5_MASK 0x00002000
+#define XCHAL_INTLEVEL6_MASK 0x00000000
+#define XCHAL_INTLEVEL7_MASK 0x00004000
+
+/* Masks of interrupts at each range 1..n of interrupt levels: */
+#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x001F80FF
+#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x001F81FF
+#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x003F8FFF
+#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x003F9FFF
+#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x003FBFFF
+#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x003FBFFF
+#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x003FFFFF
+
+/* Level of each interrupt: */
+#define XCHAL_INT0_LEVEL 1
+#define XCHAL_INT1_LEVEL 1
+#define XCHAL_INT2_LEVEL 1
+#define XCHAL_INT3_LEVEL 1
+#define XCHAL_INT4_LEVEL 1
+#define XCHAL_INT5_LEVEL 1
+#define XCHAL_INT6_LEVEL 1
+#define XCHAL_INT7_LEVEL 1
+#define XCHAL_INT8_LEVEL 2
+#define XCHAL_INT9_LEVEL 3
+#define XCHAL_INT10_LEVEL 3
+#define XCHAL_INT11_LEVEL 3
+#define XCHAL_INT12_LEVEL 4
+#define XCHAL_INT13_LEVEL 5
+#define XCHAL_INT14_LEVEL 7
+#define XCHAL_INT15_LEVEL 1
+#define XCHAL_INT16_LEVEL 1
+#define XCHAL_INT17_LEVEL 1
+#define XCHAL_INT18_LEVEL 1
+#define XCHAL_INT19_LEVEL 1
+#define XCHAL_INT20_LEVEL 1
+#define XCHAL_INT21_LEVEL 3
+#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */
+#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
+#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with
+ EXCSAVE/EPS/EPC_n, RFI n) */
+
+/* Type of each interrupt: */
+#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER
+#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE
+#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER
+#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE
+#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER
+#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI
+#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE
+
+/* Masks of interrupts for each type of interrupt: */
+#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFC00000
+#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000880
+#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x003F8000
+#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000133F
+#define XCHAL_INTTYPE_MASK_TIMER 0x00002440
+#define XCHAL_INTTYPE_MASK_NMI 0x00004000
+#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
+#define XCHAL_INTTYPE_MASK_PROFILING 0x00000000
+#define XCHAL_INTTYPE_MASK_IDMA_DONE 0x00000000
+#define XCHAL_INTTYPE_MASK_IDMA_ERR 0x00000000
+#define XCHAL_INTTYPE_MASK_SG_ERR 0x00000000
+
+/* Interrupt numbers assigned to specific interrupt sources: */
+#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */
+#define XCHAL_TIMER1_INTERRUPT 10 /* CCOMPARE1 */
+#define XCHAL_TIMER2_INTERRUPT 13 /* CCOMPARE2 */
+#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
+#define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */
+
+/* Interrupt numbers for levels at which only one interrupt is configured: */
+#define XCHAL_INTLEVEL2_NUM 8
+#define XCHAL_INTLEVEL4_NUM 12
+#define XCHAL_INTLEVEL5_NUM 13
+#define XCHAL_INTLEVEL7_NUM 14
+/* (There are many interrupts each at level(s) 1, 3.) */
+
+
+/*
+ * External interrupt mapping.
+ * These macros describe how Xtensa processor interrupt numbers
+ * (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
+ * map to external BInterrupt<n> pins, for those interrupts
+ * configured as external (level-triggered, edge-triggered, or NMI).
+ * See the Xtensa processor databook for more details.
+ */
+
+/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */
+#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
+#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */
+#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */
+#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
+#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */
+#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */
+#define XCHAL_EXTINT6_NUM 8 /* (intlevel 2) */
+#define XCHAL_EXTINT7_NUM 9 /* (intlevel 3) */
+#define XCHAL_EXTINT8_NUM 12 /* (intlevel 4) */
+#define XCHAL_EXTINT9_NUM 14 /* (intlevel 7) */
+#define XCHAL_EXTINT10_NUM 15 /* (intlevel 1) */
+#define XCHAL_EXTINT11_NUM 16 /* (intlevel 1) */
+#define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */
+#define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */
+#define XCHAL_EXTINT14_NUM 19 /* (intlevel 1) */
+#define XCHAL_EXTINT15_NUM 20 /* (intlevel 1) */
+#define XCHAL_EXTINT16_NUM 21 /* (intlevel 3) */
+/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */
+#define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */
+#define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */
+#define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */
+#define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */
+#define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */
+#define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */
+#define XCHAL_INT8_EXTNUM 6 /* (intlevel 2) */
+#define XCHAL_INT9_EXTNUM 7 /* (intlevel 3) */
+#define XCHAL_INT12_EXTNUM 8 /* (intlevel 4) */
+#define XCHAL_INT14_EXTNUM 9 /* (intlevel 7) */
+#define XCHAL_INT15_EXTNUM 10 /* (intlevel 1) */
+#define XCHAL_INT16_EXTNUM 11 /* (intlevel 1) */
+#define XCHAL_INT17_EXTNUM 12 /* (intlevel 1) */
+#define XCHAL_INT18_EXTNUM 13 /* (intlevel 1) */
+#define XCHAL_INT19_EXTNUM 14 /* (intlevel 1) */
+#define XCHAL_INT20_EXTNUM 15 /* (intlevel 1) */
+#define XCHAL_INT21_EXTNUM 16 /* (intlevel 3) */
+
+
+/*----------------------------------------------------------------------
+ EXCEPTIONS and VECTORS
+ ----------------------------------------------------------------------*/
+
+#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
+ number: 1 == XEA1 (old)
+ 2 == XEA2 (new)
+ 0 == XEAX (extern) or TX */
+#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
+#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
+#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
+#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
+#define XCHAL_HAVE_HALT 0 /* halt architecture option */
+#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */
+#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
+#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */
+#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */
+#define XCHAL_VECBASE_RESET_VADDR 0x60000000 /* VECBASE reset value */
+#define XCHAL_VECBASE_RESET_PADDR 0x60000000
+#define XCHAL_RESET_VECBASE_OVERLAP 0
+
+#define XCHAL_RESET_VECTOR0_VADDR 0x50000000
+#define XCHAL_RESET_VECTOR0_PADDR 0x50000000
+#define XCHAL_RESET_VECTOR1_VADDR 0x40000400
+#define XCHAL_RESET_VECTOR1_PADDR 0x40000400
+#define XCHAL_RESET_VECTOR_VADDR 0x50000000
+#define XCHAL_RESET_VECTOR_PADDR 0x50000000
+#define XCHAL_USER_VECOFS 0x00000340
+#define XCHAL_USER_VECTOR_VADDR 0x60000340
+#define XCHAL_USER_VECTOR_PADDR 0x60000340
+#define XCHAL_KERNEL_VECOFS 0x00000300
+#define XCHAL_KERNEL_VECTOR_VADDR 0x60000300
+#define XCHAL_KERNEL_VECTOR_PADDR 0x60000300
+#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0
+#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x600003C0
+#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x600003C0
+#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
+#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
+#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
+#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
+#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
+#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
+#define XCHAL_WINDOW_VECTORS_VADDR 0x60000000
+#define XCHAL_WINDOW_VECTORS_PADDR 0x60000000
+#define XCHAL_INTLEVEL2_VECOFS 0x00000180
+#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x60000180
+#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x60000180
+#define XCHAL_INTLEVEL3_VECOFS 0x000001C0
+#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x600001C0
+#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x600001C0
+#define XCHAL_INTLEVEL4_VECOFS 0x00000200
+#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x60000200
+#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x60000200
+#define XCHAL_INTLEVEL5_VECOFS 0x00000240
+#define XCHAL_INTLEVEL5_VECTOR_VADDR 0x60000240
+#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x60000240
+#define XCHAL_INTLEVEL6_VECOFS 0x00000280
+#define XCHAL_INTLEVEL6_VECTOR_VADDR 0x60000280
+#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x60000280
+#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS
+#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR
+#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR
+#define XCHAL_NMI_VECOFS 0x000002C0
+#define XCHAL_NMI_VECTOR_VADDR 0x600002C0
+#define XCHAL_NMI_VECTOR_PADDR 0x600002C0
+#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS
+#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
+#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
+
+
+/*----------------------------------------------------------------------
+ DEBUG MODULE
+ ----------------------------------------------------------------------*/
+
+/* Misc */
+#define XCHAL_HAVE_DEBUG_ERI 1 /* ERI to debug module */
+#define XCHAL_HAVE_DEBUG_APB 0 /* APB to debug module */
+#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */
+
+/* On-Chip Debug (OCD) */
+#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
+#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */
+#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
+#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */
+#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */
+
+/* TRAX (in core) */
+#define XCHAL_HAVE_TRAX 1 /* TRAX in debug module */
+#define XCHAL_TRAX_MEM_SIZE 262144 /* TRAX memory size in bytes */
+#define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */
+#define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */
+#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */
+
+/* Perf counters */
+#define XCHAL_NUM_PERF_COUNTERS 0 /* performance counters */
+
+
+/*----------------------------------------------------------------------
+ MMU
+ ----------------------------------------------------------------------*/
+
+/* See core-matmap.h header file for more details. */
+
+#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
+#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */
+#define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */
+#define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */
+#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
+#define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */
+#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */
+#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table
+ [autorefill] and protection)
+ usable for an MMU-based OS */
+
+/* If none of the above last 5 are set, it's a custom TLB configuration. */
+
+#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */
+#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */
+#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */
+
+/*----------------------------------------------------------------------
+ MPU
+ ----------------------------------------------------------------------*/
+#define XCHAL_HAVE_MPU 0
+#define XCHAL_MPU_ENTRIES 0
+
+#define XCHAL_MPU_ALIGN_REQ 1 /* MPU requires alignment of entries to background map */
+#define XCHAL_MPU_BACKGROUND_ENTRIES 0 /* number of entries in background map */
+
+#define XCHAL_MPU_ALIGN_BITS 0
+#define XCHAL_MPU_ALIGN 0
+
+#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
+
+
+#endif /* _XTENSA_CORE_CONFIGURATION_H */
+
diff --git a/target/xtensa/core-de212/gdb-config.c b/target/xtensa/core-de212/gdb-config.c
new file mode 100644
index 0000000..25510fc
--- /dev/null
+++ b/target/xtensa/core-de212/gdb-config.c
@@ -0,0 +1,198 @@
+/* Configuration for the Xtensa architecture for GDB, the GNU debugger.
+
+ Copyright (c) 2003-2015 Tensilica Inc.
+
+ Permission is hereby granted, free of charge, to any person obtaining
+ a copy of this software and associated documentation files (the
+ "Software"), to deal in the Software without restriction, including
+ without limitation the rights to use, copy, modify, merge, publish,
+ distribute, sublicense, and/or sell copies of the Software, and to
+ permit persons to whom the Software is furnished to do so, subject to
+ the following conditions:
+
+ The above copyright notice and this permission notice shall be included
+ in all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+ XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0)
+ XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
+ XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
+ XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
+ XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
+ XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
+ XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
+ XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
+ XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
+ XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0)
+ XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9, 0,0,0,0,0,0)
+ XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10, 0,0,0,0,0,0)
+ XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, 0,0,0,0,0,0)
+ XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12, 0,0,0,0,0,0)
+ XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13, 0,0,0,0,0,0)
+ XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14, 0,0,0,0,0,0)
+ XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15, 0,0,0,0,0,0)
+ XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16, 0,0,0,0,0,0)
+ XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17, 0,0,0,0,0,0)
+ XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18, 0,0,0,0,0,0)
+ XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19, 0,0,0,0,0,0)
+ XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20, 0,0,0,0,0,0)
+ XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21, 0,0,0,0,0,0)
+ XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22, 0,0,0,0,0,0)
+ XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23, 0,0,0,0,0,0)
+ XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24, 0,0,0,0,0,0)
+ XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25, 0,0,0,0,0,0)
+ XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26, 0,0,0,0,0,0)
+ XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27, 0,0,0,0,0,0)
+ XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28, 0,0,0,0,0,0)
+ XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, 0,0,0,0,0,0)
+ XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, 0,0,0,0,0,0)
+ XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, 0,0,0,0,0,0)
+ XTREG( 33,132,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg, 0,0,0,0,0,0)
+ XTREG( 34,136,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend, 0,0,0,0,0,0)
+ XTREG( 35,140,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount, 0,0,0,0,0,0)
+ XTREG( 36,144, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0)
+ XTREG( 37,148, 3, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0)
+ XTREG( 38,152, 8, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0)
+ XTREG( 39,156,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0, 0,0,0,0,0,0)
+ XTREG( 40,160,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1, 0,0,0,0,0,0)
+ XTREG( 41,164,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0)
+ XTREG( 42,168,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1, 0,0,0,0,0,0)
+ XTREG( 43,172,32, 4, 4,0x0210,0x0006,-1, 2,0x1100,acclo, 0,0,0,0,0,0)
+ XTREG( 44,176, 8, 4, 4,0x0211,0x0006,-1, 2,0x1100,acchi, 0,0,0,0,0,0)
+ XTREG( 45,180,32, 4, 4,0x0220,0x0006,-1, 2,0x1100,m0, 0,0,0,0,0,0)
+ XTREG( 46,184,32, 4, 4,0x0221,0x0006,-1, 2,0x1100,m1, 0,0,0,0,0,0)
+ XTREG( 47,188,32, 4, 4,0x0222,0x0006,-1, 2,0x1100,m2, 0,0,0,0,0,0)
+ XTREG( 48,192,32, 4, 4,0x0223,0x0006,-1, 2,0x1100,m3, 0,0,0,0,0,0)
+ XTREG( 49,196,32, 4, 4,0x03e6,0x000e,-1, 3,0x0110,expstate, 0,0,0,0,0,0)
+ XTREG( 50,200,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid, 0,0,0,0,0,0)
+ XTREG( 51,204, 2, 4, 4,0x0260,0x0007,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0)
+ XTREG( 52,208, 6, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl, 0,0,0,0,0,0)
+ XTREG( 53,212,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0)
+ XTREG( 54,216,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0, 0,0,0,0,0,0)
+ XTREG( 55,220,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1, 0,0,0,0,0,0)
+ XTREG( 56,224,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0, 0,0,0,0,0,0)
+ XTREG( 57,228,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1, 0,0,0,0,0,0)
+ XTREG( 58,232,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0, 0,0,0,0,0,0)
+ XTREG( 59,236,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1, 0,0,0,0,0,0)
+ XTREG( 60,240,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0)
+ XTREG( 61,244,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0)
+ XTREG( 62,248,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3, 0,0,0,0,0,0)
+ XTREG( 63,252,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4, 0,0,0,0,0,0)
+ XTREG( 64,256,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, 0,0,0,0,0,0)
+ XTREG( 65,260,32, 4, 4,0x02b6,0x0007,-2, 2,0x1000,epc6, 0,0,0,0,0,0)
+ XTREG( 66,264,32, 4, 4,0x02b7,0x0007,-2, 2,0x1000,epc7, 0,0,0,0,0,0)
+ XTREG( 67,268,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0)
+ XTREG( 68,272,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0)
+ XTREG( 69,276,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3, 0,0,0,0,0,0)
+ XTREG( 70,280,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4, 0,0,0,0,0,0)
+ XTREG( 71,284,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5, 0,0,0,0,0,0)
+ XTREG( 72,288,19, 4, 4,0x02c6,0x0007,-2, 2,0x1000,eps6, 0,0,0,0,0,0)
+ XTREG( 73,292,19, 4, 4,0x02c7,0x0007,-2, 2,0x1000,eps7, 0,0,0,0,0,0)
+ XTREG( 74,296,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0)
+ XTREG( 75,300,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0)
+ XTREG( 76,304,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3, 0,0,0,0,0,0)
+ XTREG( 77,308,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4, 0,0,0,0,0,0)
+ XTREG( 78,312,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5, 0,0,0,0,0,0)
+ XTREG( 79,316,32, 4, 4,0x02d6,0x0007,-2, 2,0x1000,excsave6, 0,0,0,0,0,0)
+ XTREG( 80,320,32, 4, 4,0x02d7,0x0007,-2, 2,0x1000,excsave7, 0,0,0,0,0,0)
+ XTREG( 81,324,22, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0)
+ XTREG( 82,328,22, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0)
+ XTREG( 83,332,22, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0)
+ XTREG( 84,336,22, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0)
+ XTREG( 85,340,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0)
+ XTREG( 86,344, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0)
+ XTREG( 87,348,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0)
+ XTREG( 88,352,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0)
+ XTREG( 89,356,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0)
+ XTREG( 90,360,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0)
+ XTREG( 91,364, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0)
+ XTREG( 92,368,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0)
+ XTREG( 93,372,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0)
+ XTREG( 94,376,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0)
+ XTREG( 95,380,32, 4, 4,0x02f2,0x000f,-2, 2,0x1000,ccompare2, 0,0,0,0,0,0)
+ XTREG( 96,384,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0, 0,0,0,0,0,0)
+ XTREG( 97,388,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, 0,0,0,0,0,0)
+ XTREG( 98,392,32, 8, 4,0x2015,0x000f,-2, 4,0x0101,pwrctl,
+ "03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:20:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:20:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG( 99,400,32, 8, 4,0x2016,0x000f,-2, 4,0x0101,pwrstat,
+ "03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:24:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:24:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(100,408, 1, 8, 4,0x2017,0x000f,-2, 4,0x0101,eristat,
+ "03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:28:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:28:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(101,416,32, 8, 4,0x2018,0x000f,-2, 4,0x0101,cs_itctrl,
+ "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:d5:03:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:d5:03:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(102,424,16, 8, 4,0x2019,0x000f,-2, 4,0x0101,cs_claimset,
+ "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a0:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a0:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(103,432,16, 8, 4,0x201a,0x000f,-2, 4,0x0101,cs_claimclr,
+ "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a4:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a4:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(104,440,32, 8, 4,0x201b,0x000f,-2, 4,0x0101,cs_lockaccess,
+ "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b0:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b0:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(105,448,32, 8, 4,0x201c,0x000f,-2, 4,0x0101,cs_lockstatus,
+ "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b4:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b4:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(106,456, 1, 8, 4,0x201d,0x000f,-2, 4,0x0101,cs_authstatus,
+ "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b8:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b8:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(107,464,32, 8, 4,0x202c,0x0007,-2, 4,0x0101,trax_id,
+ "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(108,472,32, 8, 4,0x202d,0x000f,-2, 4,0x0101,trax_control,
+ "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(109,480,32, 8, 4,0x202e,0x000f,-2, 4,0x0101,trax_status,
+ "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:08:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:08:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(110,488,32, 8, 4,0x202f,0x000f,-2, 4,0x0101,trax_data,
+ "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:0c:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:0c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(111,496,32, 8, 4,0x2030,0x000f,-2, 4,0x0101,trax_address,
+ "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:10:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:10:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(112,504,32, 8, 4,0x2031,0x000f,-2, 4,0x0101,trax_pctrigger,
+ "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:14:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:14:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(113,512,32, 8, 4,0x2032,0x000f,-2, 4,0x0101,trax_pcmatch,
+ "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:18:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:18:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(114,520,32, 8, 4,0x2033,0x000f,-2, 4,0x0101,trax_delay,
+ "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:1c:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:1c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(115,528,32, 8, 4,0x2034,0x000f,-2, 4,0x0101,trax_memstart,
+ "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:20:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:20:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(116,536,32, 8, 4,0x2035,0x000f,-2, 4,0x0101,trax_memend,
+ "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:24:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:24:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(117,544,32, 8, 4,0x2043,0x0007,-2, 4,0x0101,ocdid,
+ "03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(118,552,32, 8, 4,0x2044,0x000f,-2, 4,0x0101,ocd_dcrclr,
+ "03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:08:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:08:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(119,560,32, 8, 4,0x2045,0x000f,-2, 4,0x0101,ocd_dcrset,
+ "03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:0c:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:0c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(120,568,32, 8, 4,0x2046,0x000f,-2, 4,0x0101,ocd_dsr,
+ "03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:10:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:10:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(121,576,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0, 0,0,0,0,0,0)
+ XTREG(122,580,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1, 0,0,0,0,0,0)
+ XTREG(123,584,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2, 0,0,0,0,0,0)
+ XTREG(124,588,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3, 0,0,0,0,0,0)
+ XTREG(125,592,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4, 0,0,0,0,0,0)
+ XTREG(126,596,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5, 0,0,0,0,0,0)
+ XTREG(127,600,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6, 0,0,0,0,0,0)
+ XTREG(128,604,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7, 0,0,0,0,0,0)
+ XTREG(129,608,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8, 0,0,0,0,0,0)
+ XTREG(130,612,32, 4, 4,0x0009,0x0006,-2, 8,0x0100,a9, 0,0,0,0,0,0)
+ XTREG(131,616,32, 4, 4,0x000a,0x0006,-2, 8,0x0100,a10, 0,0,0,0,0,0)
+ XTREG(132,620,32, 4, 4,0x000b,0x0006,-2, 8,0x0100,a11, 0,0,0,0,0,0)
+ XTREG(133,624,32, 4, 4,0x000c,0x0006,-2, 8,0x0100,a12, 0,0,0,0,0,0)
+ XTREG(134,628,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13, 0,0,0,0,0,0)
+ XTREG(135,632,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14, 0,0,0,0,0,0)
+ XTREG(136,636,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15, 0,0,0,0,0,0)
+ XTREG(137,640, 4, 4, 4,0x2008,0x0006,-2, 6,0x1010,psintlevel,
+ 0,0,&xtensa_mask0,0,0,0)
+ XTREG(138,644, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,psum,
+ 0,0,&xtensa_mask1,0,0,0)
+ XTREG(139,648, 1, 4, 4,0x200a,0x0006,-2, 6,0x1010,pswoe,
+ 0,0,&xtensa_mask2,0,0,0)
+ XTREG(140,652, 1, 4, 4,0x200b,0x0006,-2, 6,0x1010,psexcm,
+ 0,0,&xtensa_mask3,0,0,0)
+ XTREG(141,656, 2, 4, 4,0x200c,0x0006,-2, 6,0x1010,pscallinc,
+ 0,0,&xtensa_mask4,0,0,0)
+ XTREG(142,660, 4, 4, 4,0x200d,0x0006,-2, 6,0x1010,psowb,
+ 0,0,&xtensa_mask5,0,0,0)
+ XTREG(143,664,40, 8, 4,0x200e,0x0006,-2, 6,0x1010,acc,
+ 0,0,&xtensa_mask6,0,0,0)
+ XTREG_END
diff --git a/target/xtensa/core-de212/xtensa-modules.c b/target/xtensa/core-de212/xtensa-modules.c
new file mode 100644
index 0000000..4a87358
--- /dev/null
+++ b/target/xtensa/core-de212/xtensa-modules.c
@@ -0,0 +1,14566 @@
+/* Xtensa configuration-specific ISA information.
+
+ Copyright (c) 2003-2015 Tensilica Inc.
+
+ Permission is hereby granted, free of charge, to any person obtaining
+ a copy of this software and associated documentation files (the
+ "Software"), to deal in the Software without restriction, including
+ without limitation the rights to use, copy, modify, merge, publish,
+ distribute, sublicense, and/or sell copies of the Software, and to
+ permit persons to whom the Software is furnished to do so, subject to
+ the following conditions:
+
+ The above copyright notice and this permission notice shall be included
+ in all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+#include <xtensa-isa.h>
+#include "xtensa-isa-internal.h"
+
+
+/* Sysregs. */
+
+static xtensa_sysreg_internal sysregs[] = {
+ { "LBEG", 0, 0 },
+ { "LEND", 1, 0 },
+ { "LCOUNT", 2, 0 },
+ { "ACCLO", 16, 0 },
+ { "ACCHI", 17, 0 },
+ { "M0", 32, 0 },
+ { "M1", 33, 0 },
+ { "M2", 34, 0 },
+ { "M3", 35, 0 },
+ { "MMID", 89, 0 },
+ { "DDR", 104, 0 },
+ { "CONFIGID0", 176, 0 },
+ { "CONFIGID1", 208, 0 },
+ { "INTERRUPT", 226, 0 },
+ { "INTCLEAR", 227, 0 },
+ { "CCOUNT", 234, 0 },
+ { "PRID", 235, 0 },
+ { "ICOUNT", 236, 0 },
+ { "CCOMPARE0", 240, 0 },
+ { "CCOMPARE1", 241, 0 },
+ { "CCOMPARE2", 242, 0 },
+ { "VECBASE", 231, 0 },
+ { "EPC1", 177, 0 },
+ { "EPC2", 178, 0 },
+ { "EPC3", 179, 0 },
+ { "EPC4", 180, 0 },
+ { "EPC5", 181, 0 },
+ { "EPC6", 182, 0 },
+ { "EPC7", 183, 0 },
+ { "EXCSAVE1", 209, 0 },
+ { "EXCSAVE2", 210, 0 },
+ { "EXCSAVE3", 211, 0 },
+ { "EXCSAVE4", 212, 0 },
+ { "EXCSAVE5", 213, 0 },
+ { "EXCSAVE6", 214, 0 },
+ { "EXCSAVE7", 215, 0 },
+ { "EPS2", 194, 0 },
+ { "EPS3", 195, 0 },
+ { "EPS4", 196, 0 },
+ { "EPS5", 197, 0 },
+ { "EPS6", 198, 0 },
+ { "EPS7", 199, 0 },
+ { "EXCCAUSE", 232, 0 },
+ { "DEPC", 192, 0 },
+ { "EXCVADDR", 238, 0 },
+ { "WINDOWBASE", 72, 0 },
+ { "WINDOWSTART", 73, 0 },
+ { "SAR", 3, 0 },
+ { "PS", 230, 0 },
+ { "MISC0", 244, 0 },
+ { "MISC1", 245, 0 },
+ { "INTENABLE", 228, 0 },
+ { "DBREAKA0", 144, 0 },
+ { "DBREAKC0", 160, 0 },
+ { "DBREAKA1", 145, 0 },
+ { "DBREAKC1", 161, 0 },
+ { "IBREAKA0", 128, 0 },
+ { "IBREAKA1", 129, 0 },
+ { "IBREAKENABLE", 96, 0 },
+ { "ICOUNTLEVEL", 237, 0 },
+ { "DEBUGCAUSE", 233, 0 },
+ { "SCOMPARE1", 12, 0 },
+ { "ATOMCTL", 99, 0 },
+ { "EXPSTATE", 230, 1 }
+};
+
+#define NUM_SYSREGS 64
+#define MAX_SPECIAL_REG 245
+#define MAX_USER_REG 230
+
+
+/* Processor states. */
+
+static xtensa_state_internal states[] = {
+ { "LCOUNT", 32, 0 },
+ { "PC", 32, 0 },
+ { "ICOUNT", 32, 0 },
+ { "DDR", 32, 0 },
+ { "INTERRUPT", 22, 0 },
+ { "CCOUNT", 32, 0 },
+ { "XTSYNC", 1, 0 },
+ { "VECBASE", 22, 0 },
+ { "EPC1", 32, 0 },
+ { "EPC2", 32, 0 },
+ { "EPC3", 32, 0 },
+ { "EPC4", 32, 0 },
+ { "EPC5", 32, 0 },
+ { "EPC6", 32, 0 },
+ { "EPC7", 32, 0 },
+ { "EXCSAVE1", 32, 0 },
+ { "EXCSAVE2", 32, 0 },
+ { "EXCSAVE3", 32, 0 },
+ { "EXCSAVE4", 32, 0 },
+ { "EXCSAVE5", 32, 0 },
+ { "EXCSAVE6", 32, 0 },
+ { "EXCSAVE7", 32, 0 },
+ { "EPS2", 13, 0 },
+ { "EPS3", 13, 0 },
+ { "EPS4", 13, 0 },
+ { "EPS5", 13, 0 },
+ { "EPS6", 13, 0 },
+ { "EPS7", 13, 0 },
+ { "EXCCAUSE", 6, 0 },
+ { "PSINTLEVEL", 4, 0 },
+ { "PSUM", 1, 0 },
+ { "PSWOE", 1, 0 },
+ { "PSEXCM", 1, 0 },
+ { "DEPC", 32, 0 },
+ { "EXCVADDR", 32, 0 },
+ { "WindowBase", 3, 0 },
+ { "WindowStart", 8, 0 },
+ { "PSCALLINC", 2, 0 },
+ { "PSOWB", 4, 0 },
+ { "LBEG", 32, 0 },
+ { "LEND", 32, 0 },
+ { "SAR", 6, 0 },
+ { "MISC0", 32, 0 },
+ { "MISC1", 32, 0 },
+ { "ACC", 40, 0 },
+ { "InOCDMode", 1, 0 },
+ { "INTENABLE", 22, 0 },
+ { "DBREAKA0", 32, 0 },
+ { "DBREAKC0", 8, 0 },
+ { "DBREAKA1", 32, 0 },
+ { "DBREAKC1", 8, 0 },
+ { "IBREAKA0", 32, 0 },
+ { "IBREAKA1", 32, 0 },
+ { "IBREAKENABLE", 2, 0 },
+ { "ICOUNTLEVEL", 4, 0 },
+ { "DEBUGCAUSE", 6, 0 },
+ { "DBNUM", 4, 0 },
+ { "CCOMPARE0", 32, 0 },
+ { "CCOMPARE1", 32, 0 },
+ { "CCOMPARE2", 32, 0 },
+ { "SCOMPARE1", 32, 0 },
+ { "ATOMCTL", 6, 0 },
+ { "ERI_RAW_INTERLOCK", 1, 0 },
+ { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED }
+};
+
+#define NUM_STATES 64
+
+enum xtensa_state_id {
+ STATE_LCOUNT,
+ STATE_PC,
+ STATE_ICOUNT,
+ STATE_DDR,
+ STATE_INTERRUPT,
+ STATE_CCOUNT,
+ STATE_XTSYNC,
+ STATE_VECBASE,
+ STATE_EPC1,
+ STATE_EPC2,
+ STATE_EPC3,
+ STATE_EPC4,
+ STATE_EPC5,
+ STATE_EPC6,
+ STATE_EPC7,
+ STATE_EXCSAVE1,
+ STATE_EXCSAVE2,
+ STATE_EXCSAVE3,
+ STATE_EXCSAVE4,
+ STATE_EXCSAVE5,
+ STATE_EXCSAVE6,
+ STATE_EXCSAVE7,
+ STATE_EPS2,
+ STATE_EPS3,
+ STATE_EPS4,
+ STATE_EPS5,
+ STATE_EPS6,
+ STATE_EPS7,
+ STATE_EXCCAUSE,
+ STATE_PSINTLEVEL,
+ STATE_PSUM,
+ STATE_PSWOE,
+ STATE_PSEXCM,
+ STATE_DEPC,
+ STATE_EXCVADDR,
+ STATE_WindowBase,
+ STATE_WindowStart,
+ STATE_PSCALLINC,
+ STATE_PSOWB,
+ STATE_LBEG,
+ STATE_LEND,
+ STATE_SAR,
+ STATE_MISC0,
+ STATE_MISC1,
+ STATE_ACC,
+ STATE_InOCDMode,
+ STATE_INTENABLE,
+ STATE_DBREAKA0,
+ STATE_DBREAKC0,
+ STATE_DBREAKA1,
+ STATE_DBREAKC1,
+ STATE_IBREAKA0,
+ STATE_IBREAKA1,
+ STATE_IBREAKENABLE,
+ STATE_ICOUNTLEVEL,
+ STATE_DEBUGCAUSE,
+ STATE_DBNUM,
+ STATE_CCOMPARE0,
+ STATE_CCOMPARE1,
+ STATE_CCOMPARE2,
+ STATE_SCOMPARE1,
+ STATE_ATOMCTL,
+ STATE_ERI_RAW_INTERLOCK,
+ STATE_EXPSTATE
+};
+
+
+/* Field definitions. */
+
+static unsigned
+Field_t_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_s_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_r_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
+ return tie_t;
+}
+
+static void
+Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
+}
+
+static unsigned
+Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
+ return tie_t;
+}
+
+static void
+Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
+}
+
+static unsigned
+Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_n_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ return tie_t;
+}
+
+static void
+Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_m_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
+ return tie_t;
+}
+
+static void
+Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
+ return tie_t;
+}
+
+static void
+Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
+}
+
+static unsigned
+Field_t3_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+}
+
+static unsigned
+Field_tlo_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ return tie_t;
+}
+
+static void
+Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_w_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
+ return tie_t;
+}
+
+static void
+Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
+}
+
+static unsigned
+Field_r3_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+ return tie_t;
+}
+
+static void
+Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+}
+
+static unsigned
+Field_rhi_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ return tie_t;
+}
+
+static void
+Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_st_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+ return tie_t;
+}
+
+static void
+Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+}
+
+static unsigned
+Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_t_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
+ return tie_t;
+}
+
+static void
+Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
+}
+
+static unsigned
+Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+}
+
+static unsigned
+Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_t_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
+ return tie_t;
+}
+
+static void
+Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
+}
+
+static unsigned
+Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20);
+ return tie_t;
+}
+
+static void
+Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 20) >> 20;
+ insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
+ return tie_t;
+}
+
+static void
+Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
+}
+
+static unsigned
+Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
+ return tie_t;
+}
+
+static void
+Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
+ tie_t = (val << 20) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16);
+ return tie_t;
+}
+
+static void
+Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 16) >> 16;
+ insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8);
+}
+
+static unsigned
+Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
+ return tie_t;
+}
+
+static void
+Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 14) >> 14;
+ insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
+ return tie_t;
+}
+
+static void
+Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
+}
+
+static unsigned
+Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
+ return tie_t;
+}
+
+static void
+Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
+}
+
+static unsigned
+Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
+}
+
+static unsigned
+Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
+}
+
+static unsigned
+Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
+}
+
+static unsigned
+Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
+ return tie_t;
+}
+
+static void
+Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
+}
+
+static unsigned
+Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
+}
+
+static unsigned
+Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_st_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_st_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_mn_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ return tie_t;
+}
+
+static void
+Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+}
+
+static unsigned
+Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ return tie_t;
+}
+
+static void
+Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ return tie_t;
+}
+
+static void
+Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
+ return tie_t;
+}
+
+static void
+Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
+ return tie_t;
+}
+
+static void
+Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
+}
+
+static unsigned
+Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
+ return tie_t;
+}
+
+static void
+Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
+}
+
+static unsigned
+Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+ tie_t = (val << 25) >> 29;
+ insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+ tie_t = (val << 25) >> 29;
+ insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
+}
+
+static unsigned
+Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
+ return tie_t;
+}
+
+static void
+Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
+}
+
+static unsigned
+Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
+ return tie_t;
+}
+
+static void
+Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
+}
+
+static unsigned
+Field_y_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
+ return tie_t;
+}
+
+static void
+Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
+}
+
+static unsigned
+Field_x_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
+ return tie_t;
+}
+
+static void
+Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
+}
+
+static unsigned
+Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17);
+ return tie_t;
+}
+
+static void
+Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 17) >> 17;
+ insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9);
+}
+
+static unsigned
+Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
+ return tie_t;
+}
+
+static void
+Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 14) >> 14;
+ insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
+}
+
+static unsigned
+Field_bitindex_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_bitindex_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
+}
+
+static unsigned
+Field_bitindex_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_bitindex_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
+}
+
+static unsigned
+Field_s3to1_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+ return tie_t;
+}
+
+static void
+Field_s3to1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+}
+
+static unsigned
+Field_s3to1_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+ return tie_t;
+}
+
+static void
+Field_s3to1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+}
+
+static void
+Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
+ uint32 val ATTRIBUTE_UNUSED)
+{
+ /* Do nothing. */
+}
+
+static unsigned
+Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static unsigned
+Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 4;
+}
+
+static unsigned
+Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 8;
+}
+
+static unsigned
+Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 12;
+}
+
+static unsigned
+Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static unsigned
+Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 1;
+}
+
+static unsigned
+Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 2;
+}
+
+static unsigned
+Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 3;
+}
+
+enum xtensa_field_id {
+ FIELD_t,
+ FIELD_bbi4,
+ FIELD_bbi,
+ FIELD_imm12,
+ FIELD_imm8,
+ FIELD_s,
+ FIELD_imm12b,
+ FIELD_imm16,
+ FIELD_m,
+ FIELD_n,
+ FIELD_offset,
+ FIELD_op0,
+ FIELD_op1,
+ FIELD_op2,
+ FIELD_r,
+ FIELD_sa4,
+ FIELD_sae4,
+ FIELD_sae,
+ FIELD_sal,
+ FIELD_sargt,
+ FIELD_sas4,
+ FIELD_sas,
+ FIELD_sr,
+ FIELD_st,
+ FIELD_thi3,
+ FIELD_imm4,
+ FIELD_mn,
+ FIELD_i,
+ FIELD_imm6lo,
+ FIELD_imm6hi,
+ FIELD_imm7lo,
+ FIELD_imm7hi,
+ FIELD_z,
+ FIELD_imm6,
+ FIELD_imm7,
+ FIELD_r3,
+ FIELD_rbit2,
+ FIELD_rhi,
+ FIELD_t3,
+ FIELD_tbit2,
+ FIELD_tlo,
+ FIELD_w,
+ FIELD_y,
+ FIELD_x,
+ FIELD_xt_wbr15_imm,
+ FIELD_xt_wbr18_imm,
+ FIELD_bitindex,
+ FIELD_s3to1,
+ FIELD__ar0,
+ FIELD__ar4,
+ FIELD__ar8,
+ FIELD__ar12,
+ FIELD__mr0,
+ FIELD__mr1,
+ FIELD__mr2,
+ FIELD__mr3
+};
+
+
+/* Functional units. */
+
+#define funcUnits 0
+
+
+/* Register files. */
+
+enum xtensa_regfile_id {
+ REGFILE_AR,
+ REGFILE_MR
+};
+
+static xtensa_regfile_internal regfiles[] = {
+ { "AR", "a", REGFILE_AR, 32, 32 },
+ { "MR", "m", REGFILE_MR, 32, 4 }
+};
+
+
+/* Interfaces. */
+
+static xtensa_interface_internal interfaces[] = {
+ { "ERI_RD_Out", 14, 0, 0, 'o' },
+ { "ERI_RD_In", 32, 0, 1, 'i' },
+ { "ERI_RD_Rdy", 1, 0, 0, 'i' },
+ { "ERI_WR_Out", 46, 0, 2, 'o' },
+ { "ERI_WR_In", 1, 0, 3, 'i' },
+ { "IMPWIRE", 32, 0, 4, 'i' }
+};
+
+enum xtensa_interface_id {
+ INTERFACE_ERI_RD_Out,
+ INTERFACE_ERI_RD_In,
+ INTERFACE_ERI_RD_Rdy,
+ INTERFACE_ERI_WR_Out,
+ INTERFACE_ERI_WR_In,
+ INTERFACE_IMPWIRE
+};
+
+
+/* Constant tables. */
+
+/* constant table ai4c */
+static const unsigned CONST_TBL_ai4c_0[] = {
+ 0xffffffff,
+ 0x1,
+ 0x2,
+ 0x3,
+ 0x4,
+ 0x5,
+ 0x6,
+ 0x7,
+ 0x8,
+ 0x9,
+ 0xa,
+ 0xb,
+ 0xc,
+ 0xd,
+ 0xe,
+ 0xf,
+ 0
+};
+
+/* constant table b4c */
+static const unsigned CONST_TBL_b4c_0[] = {
+ 0xffffffff,
+ 0x1,
+ 0x2,
+ 0x3,
+ 0x4,
+ 0x5,
+ 0x6,
+ 0x7,
+ 0x8,
+ 0xa,
+ 0xc,
+ 0x10,
+ 0x20,
+ 0x40,
+ 0x80,
+ 0x100,
+ 0
+};
+
+/* constant table b4cu */
+static const unsigned CONST_TBL_b4cu_0[] = {
+ 0x8000,
+ 0x10000,
+ 0x2,
+ 0x3,
+ 0x4,
+ 0x5,
+ 0x6,
+ 0x7,
+ 0x8,
+ 0xa,
+ 0xc,
+ 0x10,
+ 0x20,
+ 0x40,
+ 0x80,
+ 0x100,
+ 0
+};
+
+
+/* Instruction operands. */
+
+static int
+OperandSem_opnd_sem_MR_0_decode (uint32 *valp)
+{
+ *valp += 2;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_MR_0_encode (uint32 *valp)
+{
+ int error;
+ error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0);
+ *valp = *valp & 1;
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_soffsetx4_decode (uint32 *valp)
+{
+ unsigned soffsetx4_out_0;
+ unsigned soffsetx4_in_0;
+ soffsetx4_in_0 = *valp & 0x3ffff;
+ soffsetx4_out_0 = 0x4 + ((((int) soffsetx4_in_0 << 14) >> 14) << 2);
+ *valp = soffsetx4_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_soffsetx4_encode (uint32 *valp)
+{
+ unsigned soffsetx4_in_0;
+ unsigned soffsetx4_out_0;
+ soffsetx4_out_0 = *valp;
+ soffsetx4_in_0 = ((soffsetx4_out_0 - 0x4) >> 2) & 0x3ffff;
+ *valp = soffsetx4_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm12x8_decode (uint32 *valp)
+{
+ unsigned uimm12x8_out_0;
+ unsigned uimm12x8_in_0;
+ uimm12x8_in_0 = *valp & 0xfff;
+ uimm12x8_out_0 = uimm12x8_in_0 << 3;
+ *valp = uimm12x8_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm12x8_encode (uint32 *valp)
+{
+ unsigned uimm12x8_in_0;
+ unsigned uimm12x8_out_0;
+ uimm12x8_out_0 = *valp;
+ uimm12x8_in_0 = ((uimm12x8_out_0 >> 3) & 0xfff);
+ *valp = uimm12x8_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm4_decode (uint32 *valp)
+{
+ unsigned simm4_out_0;
+ unsigned simm4_in_0;
+ simm4_in_0 = *valp & 0xf;
+ simm4_out_0 = ((int) simm4_in_0 << 28) >> 28;
+ *valp = simm4_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm4_encode (uint32 *valp)
+{
+ unsigned simm4_in_0;
+ unsigned simm4_out_0;
+ simm4_out_0 = *valp;
+ simm4_in_0 = (simm4_out_0 & 0xf);
+ *valp = simm4_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_encode (uint32 *valp)
+{
+ int error;
+ error = (*valp >= 32);
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_AR_0_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_0_encode (uint32 *valp)
+{
+ int error;
+ error = (*valp >= 32);
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_AR_1_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_1_encode (uint32 *valp)
+{
+ int error;
+ error = (*valp >= 32);
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_AR_2_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_2_encode (uint32 *valp)
+{
+ int error;
+ error = (*valp >= 32);
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_AR_3_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_3_encode (uint32 *valp)
+{
+ int error;
+ error = (*valp >= 32);
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_AR_4_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_4_encode (uint32 *valp)
+{
+ int error;
+ error = (*valp >= 32);
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_immrx4_decode (uint32 *valp)
+{
+ unsigned immrx4_out_0;
+ unsigned immrx4_in_0;
+ immrx4_in_0 = *valp & 0xf;
+ immrx4_out_0 = (((0xfffffff) << 4) | immrx4_in_0) << 2;
+ *valp = immrx4_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_immrx4_encode (uint32 *valp)
+{
+ unsigned immrx4_in_0;
+ unsigned immrx4_out_0;
+ immrx4_out_0 = *valp;
+ immrx4_in_0 = ((immrx4_out_0 >> 2) & 0xf);
+ *valp = immrx4_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_lsi4x4_decode (uint32 *valp)
+{
+ unsigned lsi4x4_out_0;
+ unsigned lsi4x4_in_0;
+ lsi4x4_in_0 = *valp & 0xf;
+ lsi4x4_out_0 = lsi4x4_in_0 << 2;
+ *valp = lsi4x4_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_lsi4x4_encode (uint32 *valp)
+{
+ unsigned lsi4x4_in_0;
+ unsigned lsi4x4_out_0;
+ lsi4x4_out_0 = *valp;
+ lsi4x4_in_0 = ((lsi4x4_out_0 >> 2) & 0xf);
+ *valp = lsi4x4_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm7_decode (uint32 *valp)
+{
+ unsigned simm7_out_0;
+ unsigned simm7_in_0;
+ simm7_in_0 = *valp & 0x7f;
+ simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | simm7_in_0;
+ *valp = simm7_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm7_encode (uint32 *valp)
+{
+ unsigned simm7_in_0;
+ unsigned simm7_out_0;
+ simm7_out_0 = *valp;
+ simm7_in_0 = (simm7_out_0 & 0x7f);
+ *valp = simm7_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm6_decode (uint32 *valp)
+{
+ unsigned uimm6_out_0;
+ unsigned uimm6_in_0;
+ uimm6_in_0 = *valp & 0x3f;
+ uimm6_out_0 = 0x4 + (((0) << 6) | uimm6_in_0);
+ *valp = uimm6_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm6_encode (uint32 *valp)
+{
+ unsigned uimm6_in_0;
+ unsigned uimm6_out_0;
+ uimm6_out_0 = *valp;
+ uimm6_in_0 = (uimm6_out_0 - 0x4) & 0x3f;
+ *valp = uimm6_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_ai4const_decode (uint32 *valp)
+{
+ unsigned ai4const_out_0;
+ unsigned ai4const_in_0;
+ ai4const_in_0 = *valp & 0xf;
+ ai4const_out_0 = CONST_TBL_ai4c_0[ai4const_in_0 & 0xf];
+ *valp = ai4const_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_ai4const_encode (uint32 *valp)
+{
+ unsigned ai4const_in_0;
+ unsigned ai4const_out_0;
+ ai4const_out_0 = *valp;
+ switch (ai4const_out_0)
+ {
+ case 0xffffffff: ai4const_in_0 = 0; break;
+ case 0x1: ai4const_in_0 = 0x1; break;
+ case 0x2: ai4const_in_0 = 0x2; break;
+ case 0x3: ai4const_in_0 = 0x3; break;
+ case 0x4: ai4const_in_0 = 0x4; break;
+ case 0x5: ai4const_in_0 = 0x5; break;
+ case 0x6: ai4const_in_0 = 0x6; break;
+ case 0x7: ai4const_in_0 = 0x7; break;
+ case 0x8: ai4const_in_0 = 0x8; break;
+ case 0x9: ai4const_in_0 = 0x9; break;
+ case 0xa: ai4const_in_0 = 0xa; break;
+ case 0xb: ai4const_in_0 = 0xb; break;
+ case 0xc: ai4const_in_0 = 0xc; break;
+ case 0xd: ai4const_in_0 = 0xd; break;
+ case 0xe: ai4const_in_0 = 0xe; break;
+ default: ai4const_in_0 = 0xf; break;
+ }
+ *valp = ai4const_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_b4const_decode (uint32 *valp)
+{
+ unsigned b4const_out_0;
+ unsigned b4const_in_0;
+ b4const_in_0 = *valp & 0xf;
+ b4const_out_0 = CONST_TBL_b4c_0[b4const_in_0 & 0xf];
+ *valp = b4const_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_b4const_encode (uint32 *valp)
+{
+ unsigned b4const_in_0;
+ unsigned b4const_out_0;
+ b4const_out_0 = *valp;
+ switch (b4const_out_0)
+ {
+ case 0xffffffff: b4const_in_0 = 0; break;
+ case 0x1: b4const_in_0 = 0x1; break;
+ case 0x2: b4const_in_0 = 0x2; break;
+ case 0x3: b4const_in_0 = 0x3; break;
+ case 0x4: b4const_in_0 = 0x4; break;
+ case 0x5: b4const_in_0 = 0x5; break;
+ case 0x6: b4const_in_0 = 0x6; break;
+ case 0x7: b4const_in_0 = 0x7; break;
+ case 0x8: b4const_in_0 = 0x8; break;
+ case 0xa: b4const_in_0 = 0x9; break;
+ case 0xc: b4const_in_0 = 0xa; break;
+ case 0x10: b4const_in_0 = 0xb; break;
+ case 0x20: b4const_in_0 = 0xc; break;
+ case 0x40: b4const_in_0 = 0xd; break;
+ case 0x80: b4const_in_0 = 0xe; break;
+ default: b4const_in_0 = 0xf; break;
+ }
+ *valp = b4const_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_b4constu_decode (uint32 *valp)
+{
+ unsigned b4constu_out_0;
+ unsigned b4constu_in_0;
+ b4constu_in_0 = *valp & 0xf;
+ b4constu_out_0 = CONST_TBL_b4cu_0[b4constu_in_0 & 0xf];
+ *valp = b4constu_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_b4constu_encode (uint32 *valp)
+{
+ unsigned b4constu_in_0;
+ unsigned b4constu_out_0;
+ b4constu_out_0 = *valp;
+ switch (b4constu_out_0)
+ {
+ case 0x8000: b4constu_in_0 = 0; break;
+ case 0x10000: b4constu_in_0 = 0x1; break;
+ case 0x2: b4constu_in_0 = 0x2; break;
+ case 0x3: b4constu_in_0 = 0x3; break;
+ case 0x4: b4constu_in_0 = 0x4; break;
+ case 0x5: b4constu_in_0 = 0x5; break;
+ case 0x6: b4constu_in_0 = 0x6; break;
+ case 0x7: b4constu_in_0 = 0x7; break;
+ case 0x8: b4constu_in_0 = 0x8; break;
+ case 0xa: b4constu_in_0 = 0x9; break;
+ case 0xc: b4constu_in_0 = 0xa; break;
+ case 0x10: b4constu_in_0 = 0xb; break;
+ case 0x20: b4constu_in_0 = 0xc; break;
+ case 0x40: b4constu_in_0 = 0xd; break;
+ case 0x80: b4constu_in_0 = 0xe; break;
+ default: b4constu_in_0 = 0xf; break;
+ }
+ *valp = b4constu_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8_decode (uint32 *valp)
+{
+ unsigned uimm8_out_0;
+ unsigned uimm8_in_0;
+ uimm8_in_0 = *valp & 0xff;
+ uimm8_out_0 = uimm8_in_0;
+ *valp = uimm8_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8_encode (uint32 *valp)
+{
+ unsigned uimm8_in_0;
+ unsigned uimm8_out_0;
+ uimm8_out_0 = *valp;
+ uimm8_in_0 = (uimm8_out_0 & 0xff);
+ *valp = uimm8_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8x2_decode (uint32 *valp)
+{
+ unsigned uimm8x2_out_0;
+ unsigned uimm8x2_in_0;
+ uimm8x2_in_0 = *valp & 0xff;
+ uimm8x2_out_0 = uimm8x2_in_0 << 1;
+ *valp = uimm8x2_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8x2_encode (uint32 *valp)
+{
+ unsigned uimm8x2_in_0;
+ unsigned uimm8x2_out_0;
+ uimm8x2_out_0 = *valp;
+ uimm8x2_in_0 = ((uimm8x2_out_0 >> 1) & 0xff);
+ *valp = uimm8x2_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8x4_decode (uint32 *valp)
+{
+ unsigned uimm8x4_out_0;
+ unsigned uimm8x4_in_0;
+ uimm8x4_in_0 = *valp & 0xff;
+ uimm8x4_out_0 = uimm8x4_in_0 << 2;
+ *valp = uimm8x4_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8x4_encode (uint32 *valp)
+{
+ unsigned uimm8x4_in_0;
+ unsigned uimm8x4_out_0;
+ uimm8x4_out_0 = *valp;
+ uimm8x4_in_0 = ((uimm8x4_out_0 >> 2) & 0xff);
+ *valp = uimm8x4_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm4x16_decode (uint32 *valp)
+{
+ unsigned uimm4x16_out_0;
+ unsigned uimm4x16_in_0;
+ uimm4x16_in_0 = *valp & 0xf;
+ uimm4x16_out_0 = uimm4x16_in_0 << 4;
+ *valp = uimm4x16_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm4x16_encode (uint32 *valp)
+{
+ unsigned uimm4x16_in_0;
+ unsigned uimm4x16_out_0;
+ uimm4x16_out_0 = *valp;
+ uimm4x16_in_0 = ((uimm4x16_out_0 >> 4) & 0xf);
+ *valp = uimm4x16_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimmrx4_decode (uint32 *valp)
+{
+ unsigned uimmrx4_out_0;
+ unsigned uimmrx4_in_0;
+ uimmrx4_in_0 = *valp & 0xf;
+ uimmrx4_out_0 = uimmrx4_in_0 << 2;
+ *valp = uimmrx4_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimmrx4_encode (uint32 *valp)
+{
+ unsigned uimmrx4_in_0;
+ unsigned uimmrx4_out_0;
+ uimmrx4_out_0 = *valp;
+ uimmrx4_in_0 = ((uimmrx4_out_0 >> 2) & 0xf);
+ *valp = uimmrx4_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm8_decode (uint32 *valp)
+{
+ unsigned simm8_out_0;
+ unsigned simm8_in_0;
+ simm8_in_0 = *valp & 0xff;
+ simm8_out_0 = ((int) simm8_in_0 << 24) >> 24;
+ *valp = simm8_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm8_encode (uint32 *valp)
+{
+ unsigned simm8_in_0;
+ unsigned simm8_out_0;
+ simm8_out_0 = *valp;
+ simm8_in_0 = (simm8_out_0 & 0xff);
+ *valp = simm8_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm8x256_decode (uint32 *valp)
+{
+ unsigned simm8x256_out_0;
+ unsigned simm8x256_in_0;
+ simm8x256_in_0 = *valp & 0xff;
+ simm8x256_out_0 = (((int) simm8x256_in_0 << 24) >> 24) << 8;
+ *valp = simm8x256_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm8x256_encode (uint32 *valp)
+{
+ unsigned simm8x256_in_0;
+ unsigned simm8x256_out_0;
+ simm8x256_out_0 = *valp;
+ simm8x256_in_0 = ((simm8x256_out_0 >> 8) & 0xff);
+ *valp = simm8x256_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm12b_decode (uint32 *valp)
+{
+ unsigned simm12b_out_0;
+ unsigned simm12b_in_0;
+ simm12b_in_0 = *valp & 0xfff;
+ simm12b_out_0 = ((int) simm12b_in_0 << 20) >> 20;
+ *valp = simm12b_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm12b_encode (uint32 *valp)
+{
+ unsigned simm12b_in_0;
+ unsigned simm12b_out_0;
+ simm12b_out_0 = *valp;
+ simm12b_in_0 = (simm12b_out_0 & 0xfff);
+ *valp = simm12b_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_msalp32_decode (uint32 *valp)
+{
+ unsigned msalp32_out_0;
+ unsigned msalp32_in_0;
+ msalp32_in_0 = *valp & 0x1f;
+ msalp32_out_0 = 0x20 - msalp32_in_0;
+ *valp = msalp32_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_msalp32_encode (uint32 *valp)
+{
+ unsigned msalp32_in_0;
+ unsigned msalp32_out_0;
+ msalp32_out_0 = *valp;
+ msalp32_in_0 = (0x20 - msalp32_out_0) & 0x1f;
+ *valp = msalp32_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_op2p1_decode (uint32 *valp)
+{
+ unsigned op2p1_out_0;
+ unsigned op2p1_in_0;
+ op2p1_in_0 = *valp & 0xf;
+ op2p1_out_0 = op2p1_in_0 + 0x1;
+ *valp = op2p1_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_op2p1_encode (uint32 *valp)
+{
+ unsigned op2p1_in_0;
+ unsigned op2p1_out_0;
+ op2p1_out_0 = *valp;
+ op2p1_in_0 = (op2p1_out_0 - 0x1) & 0xf;
+ *valp = op2p1_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_label8_decode (uint32 *valp)
+{
+ unsigned label8_out_0;
+ unsigned label8_in_0;
+ label8_in_0 = *valp & 0xff;
+ label8_out_0 = 0x4 + (((int) label8_in_0 << 24) >> 24);
+ *valp = label8_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_label8_encode (uint32 *valp)
+{
+ unsigned label8_in_0;
+ unsigned label8_out_0;
+ label8_out_0 = *valp;
+ label8_in_0 = (label8_out_0 - 0x4) & 0xff;
+ *valp = label8_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_ulabel8_decode (uint32 *valp)
+{
+ unsigned ulabel8_out_0;
+ unsigned ulabel8_in_0;
+ ulabel8_in_0 = *valp & 0xff;
+ ulabel8_out_0 = 0x4 + (((0) << 8) | ulabel8_in_0);
+ *valp = ulabel8_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_ulabel8_encode (uint32 *valp)
+{
+ unsigned ulabel8_in_0;
+ unsigned ulabel8_out_0;
+ ulabel8_out_0 = *valp;
+ ulabel8_in_0 = (ulabel8_out_0 - 0x4) & 0xff;
+ *valp = ulabel8_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_label12_decode (uint32 *valp)
+{
+ unsigned label12_out_0;
+ unsigned label12_in_0;
+ label12_in_0 = *valp & 0xfff;
+ label12_out_0 = 0x4 + (((int) label12_in_0 << 20) >> 20);
+ *valp = label12_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_label12_encode (uint32 *valp)
+{
+ unsigned label12_in_0;
+ unsigned label12_out_0;
+ label12_out_0 = *valp;
+ label12_in_0 = (label12_out_0 - 0x4) & 0xfff;
+ *valp = label12_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_soffset_decode (uint32 *valp)
+{
+ unsigned soffset_out_0;
+ unsigned soffset_in_0;
+ soffset_in_0 = *valp & 0x3ffff;
+ soffset_out_0 = 0x4 + (((int) soffset_in_0 << 14) >> 14);
+ *valp = soffset_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_soffset_encode (uint32 *valp)
+{
+ unsigned soffset_in_0;
+ unsigned soffset_out_0;
+ soffset_out_0 = *valp;
+ soffset_in_0 = (soffset_out_0 - 0x4) & 0x3ffff;
+ *valp = soffset_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm16x4_decode (uint32 *valp)
+{
+ unsigned uimm16x4_out_0;
+ unsigned uimm16x4_in_0;
+ uimm16x4_in_0 = *valp & 0xffff;
+ uimm16x4_out_0 = (((0xffff) << 16) | uimm16x4_in_0) << 2;
+ *valp = uimm16x4_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm16x4_encode (uint32 *valp)
+{
+ unsigned uimm16x4_in_0;
+ unsigned uimm16x4_out_0;
+ uimm16x4_out_0 = *valp;
+ uimm16x4_in_0 = (uimm16x4_out_0 >> 2) & 0xffff;
+ *valp = uimm16x4_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_bbi_decode (uint32 *valp)
+{
+ unsigned bbi_out_0;
+ unsigned bbi_in_0;
+ bbi_in_0 = *valp & 0x1f;
+ bbi_out_0 = (0 << 5) | bbi_in_0;
+ *valp = bbi_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_bbi_encode (uint32 *valp)
+{
+ unsigned bbi_in_0;
+ unsigned bbi_out_0;
+ bbi_out_0 = *valp;
+ bbi_in_0 = (bbi_out_0 & 0x1f);
+ *valp = bbi_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_s_decode (uint32 *valp)
+{
+ unsigned s_out_0;
+ unsigned s_in_0;
+ s_in_0 = *valp & 0xf;
+ s_out_0 = (0 << 4) | s_in_0;
+ *valp = s_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_s_encode (uint32 *valp)
+{
+ unsigned s_in_0;
+ unsigned s_out_0;
+ s_out_0 = *valp;
+ s_in_0 = (s_out_0 & 0xf);
+ *valp = s_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_MR_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_MR_encode (uint32 *valp)
+{
+ int error;
+ error = (*valp >= 4);
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_MR_1_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_MR_1_encode (uint32 *valp)
+{
+ int error;
+ error = (*valp >= 4);
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_MR_2_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_MR_2_encode (uint32 *valp)
+{
+ int error;
+ error = (*valp >= 4);
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_MR_3_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_MR_3_encode (uint32 *valp)
+{
+ int error;
+ error = (*valp >= 4);
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_MR_4_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_MR_4_encode (uint32 *valp)
+{
+ int error;
+ error = (*valp >= 4);
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_MR_5_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_MR_5_encode (uint32 *valp)
+{
+ int error;
+ error = (*valp >= 4);
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_immt_decode (uint32 *valp)
+{
+ unsigned immt_out_0;
+ unsigned immt_in_0;
+ immt_in_0 = *valp & 0xf;
+ immt_out_0 = immt_in_0;
+ *valp = immt_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_immt_encode (uint32 *valp)
+{
+ unsigned immt_in_0;
+ unsigned immt_out_0;
+ immt_out_0 = *valp;
+ immt_in_0 = immt_out_0 & 0xf;
+ *valp = immt_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_tp7_decode (uint32 *valp)
+{
+ unsigned tp7_out_0;
+ unsigned tp7_in_0;
+ tp7_in_0 = *valp & 0xf;
+ tp7_out_0 = tp7_in_0 + 0x7;
+ *valp = tp7_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_tp7_encode (uint32 *valp)
+{
+ unsigned tp7_in_0;
+ unsigned tp7_out_0;
+ tp7_out_0 = *valp;
+ tp7_in_0 = (tp7_out_0 - 0x7) & 0xf;
+ *valp = tp7_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_xt_wbr15_label_decode (uint32 *valp)
+{
+ unsigned xt_wbr15_label_out_0;
+ unsigned xt_wbr15_label_in_0;
+ xt_wbr15_label_in_0 = *valp & 0x7fff;
+ xt_wbr15_label_out_0 = 0x4 + (((int) xt_wbr15_label_in_0 << 17) >> 17);
+ *valp = xt_wbr15_label_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_xt_wbr15_label_encode (uint32 *valp)
+{
+ unsigned xt_wbr15_label_in_0;
+ unsigned xt_wbr15_label_out_0;
+ xt_wbr15_label_out_0 = *valp;
+ xt_wbr15_label_in_0 = (xt_wbr15_label_out_0 - 0x4) & 0x7fff;
+ *valp = xt_wbr15_label_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_xt_wbr18_label_decode (uint32 *valp)
+{
+ unsigned xt_wbr18_label_out_0;
+ unsigned xt_wbr18_label_in_0;
+ xt_wbr18_label_in_0 = *valp & 0x3ffff;
+ xt_wbr18_label_out_0 = 0x4 + (((int) xt_wbr18_label_in_0 << 14) >> 14);
+ *valp = xt_wbr18_label_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_xt_wbr18_label_encode (uint32 *valp)
+{
+ unsigned xt_wbr18_label_in_0;
+ unsigned xt_wbr18_label_out_0;
+ xt_wbr18_label_out_0 = *valp;
+ xt_wbr18_label_in_0 = (xt_wbr18_label_out_0 - 0x4) & 0x3ffff;
+ *valp = xt_wbr18_label_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_bitindex_decode (uint32 *valp)
+{
+ unsigned bitindex_out_0;
+ unsigned bitindex_in_0;
+ bitindex_in_0 = *valp & 0x1f;
+ bitindex_out_0 = (0 << 5) | bitindex_in_0;
+ *valp = bitindex_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_bitindex_encode (uint32 *valp)
+{
+ unsigned bitindex_in_0;
+ unsigned bitindex_out_0;
+ bitindex_out_0 = *valp;
+ bitindex_in_0 = (bitindex_out_0 & 0x1f);
+ *valp = bitindex_in_0;
+ return 0;
+}
+
+static int
+Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= (pc & ~0x3);
+ return 0;
+}
+
+static int
+Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += (pc & ~0x3);
+ return 0;
+}
+
+static int
+Operand_uimm6_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static int
+Operand_label8_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_label8_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static int
+Operand_ulabel8_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_ulabel8_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static int
+Operand_label12_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_label12_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static int
+Operand_soffset_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_soffset_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static int
+Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= ((pc + 3) & ~0x3);
+ return 0;
+}
+
+static int
+Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += ((pc + 3) & ~0x3);
+ return 0;
+}
+
+static int
+Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static int
+Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static xtensa_operand_internal operands[] = {
+ { "soffsetx4", FIELD_offset, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_soffsetx4_encode, OperandSem_opnd_sem_soffsetx4_decode,
+ Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
+ { "uimm12x8", FIELD_imm12, -1, 0,
+ 0,
+ OperandSem_opnd_sem_uimm12x8_encode, OperandSem_opnd_sem_uimm12x8_decode,
+ 0, 0 },
+ { "simm4", FIELD_mn, -1, 0,
+ 0,
+ OperandSem_opnd_sem_simm4_encode, OperandSem_opnd_sem_simm4_decode,
+ 0, 0 },
+ { "arr", FIELD_r, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+ 0, 0 },
+ { "ars", FIELD_s, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+ 0, 0 },
+ { "*ars_invisible", FIELD_s, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+ 0, 0 },
+ { "art", FIELD_t, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+ 0, 0 },
+ { "ar0", FIELD__ar0, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ OperandSem_opnd_sem_AR_0_encode, OperandSem_opnd_sem_AR_0_decode,
+ 0, 0 },
+ { "ar4", FIELD__ar4, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ OperandSem_opnd_sem_AR_1_encode, OperandSem_opnd_sem_AR_1_decode,
+ 0, 0 },
+ { "ar8", FIELD__ar8, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ OperandSem_opnd_sem_AR_2_encode, OperandSem_opnd_sem_AR_2_decode,
+ 0, 0 },
+ { "ar12", FIELD__ar12, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ OperandSem_opnd_sem_AR_3_encode, OperandSem_opnd_sem_AR_3_decode,
+ 0, 0 },
+ { "ars_entry", FIELD_s, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_AR_4_encode, OperandSem_opnd_sem_AR_4_decode,
+ 0, 0 },
+ { "immrx4", FIELD_r, -1, 0,
+ 0,
+ OperandSem_opnd_sem_immrx4_encode, OperandSem_opnd_sem_immrx4_decode,
+ 0, 0 },
+ { "lsi4x4", FIELD_r, -1, 0,
+ 0,
+ OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode,
+ 0, 0 },
+ { "simm7", FIELD_imm7, -1, 0,
+ 0,
+ OperandSem_opnd_sem_simm7_encode, OperandSem_opnd_sem_simm7_decode,
+ 0, 0 },
+ { "uimm6", FIELD_imm6, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_uimm6_encode, OperandSem_opnd_sem_uimm6_decode,
+ Operand_uimm6_ator, Operand_uimm6_rtoa },
+ { "ai4const", FIELD_t, -1, 0,
+ 0,
+ OperandSem_opnd_sem_ai4const_encode, OperandSem_opnd_sem_ai4const_decode,
+ 0, 0 },
+ { "b4const", FIELD_r, -1, 0,
+ 0,
+ OperandSem_opnd_sem_b4const_encode, OperandSem_opnd_sem_b4const_decode,
+ 0, 0 },
+ { "b4constu", FIELD_r, -1, 0,
+ 0,
+ OperandSem_opnd_sem_b4constu_encode, OperandSem_opnd_sem_b4constu_decode,
+ 0, 0 },
+ { "uimm8", FIELD_imm8, -1, 0,
+ 0,
+ OperandSem_opnd_sem_uimm8_encode, OperandSem_opnd_sem_uimm8_decode,
+ 0, 0 },
+ { "uimm8x2", FIELD_imm8, -1, 0,
+ 0,
+ OperandSem_opnd_sem_uimm8x2_encode, OperandSem_opnd_sem_uimm8x2_decode,
+ 0, 0 },
+ { "uimm8x4", FIELD_imm8, -1, 0,
+ 0,
+ OperandSem_opnd_sem_uimm8x4_encode, OperandSem_opnd_sem_uimm8x4_decode,
+ 0, 0 },
+ { "uimm4x16", FIELD_op2, -1, 0,
+ 0,
+ OperandSem_opnd_sem_uimm4x16_encode, OperandSem_opnd_sem_uimm4x16_decode,
+ 0, 0 },
+ { "uimmrx4", FIELD_r, -1, 0,
+ 0,
+ OperandSem_opnd_sem_uimmrx4_encode, OperandSem_opnd_sem_uimmrx4_decode,
+ 0, 0 },
+ { "simm8", FIELD_imm8, -1, 0,
+ 0,
+ OperandSem_opnd_sem_simm8_encode, OperandSem_opnd_sem_simm8_decode,
+ 0, 0 },
+ { "simm8x256", FIELD_imm8, -1, 0,
+ 0,
+ OperandSem_opnd_sem_simm8x256_encode, OperandSem_opnd_sem_simm8x256_decode,
+ 0, 0 },
+ { "simm12b", FIELD_imm12b, -1, 0,
+ 0,
+ OperandSem_opnd_sem_simm12b_encode, OperandSem_opnd_sem_simm12b_decode,
+ 0, 0 },
+ { "msalp32", FIELD_sal, -1, 0,
+ 0,
+ OperandSem_opnd_sem_msalp32_encode, OperandSem_opnd_sem_msalp32_decode,
+ 0, 0 },
+ { "op2p1", FIELD_op2, -1, 0,
+ 0,
+ OperandSem_opnd_sem_op2p1_encode, OperandSem_opnd_sem_op2p1_decode,
+ 0, 0 },
+ { "label8", FIELD_imm8, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_label8_encode, OperandSem_opnd_sem_label8_decode,
+ Operand_label8_ator, Operand_label8_rtoa },
+ { "ulabel8", FIELD_imm8, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_ulabel8_encode, OperandSem_opnd_sem_ulabel8_decode,
+ Operand_ulabel8_ator, Operand_ulabel8_rtoa },
+ { "label12", FIELD_imm12, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_label12_encode, OperandSem_opnd_sem_label12_decode,
+ Operand_label12_ator, Operand_label12_rtoa },
+ { "soffset", FIELD_offset, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode,
+ Operand_soffset_ator, Operand_soffset_rtoa },
+ { "uimm16x4", FIELD_imm16, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_uimm16x4_encode, OperandSem_opnd_sem_uimm16x4_decode,
+ Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
+ { "bbi", FIELD_bbi, -1, 0,
+ 0,
+ OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
+ 0, 0 },
+ { "sae", FIELD_sae, -1, 0,
+ 0,
+ OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
+ 0, 0 },
+ { "sas", FIELD_sas, -1, 0,
+ 0,
+ OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
+ 0, 0 },
+ { "sargt", FIELD_sargt, -1, 0,
+ 0,
+ OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
+ 0, 0 },
+ { "s", FIELD_s, -1, 0,
+ 0,
+ OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode,
+ 0, 0 },
+ { "mx", FIELD_x, REGFILE_MR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
+ OperandSem_opnd_sem_MR_encode, OperandSem_opnd_sem_MR_decode,
+ 0, 0 },
+ { "my", FIELD_y, REGFILE_MR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
+ OperandSem_opnd_sem_MR_0_encode, OperandSem_opnd_sem_MR_0_decode,
+ 0, 0 },
+ { "mw", FIELD_w, REGFILE_MR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_MR_1_encode, OperandSem_opnd_sem_MR_1_decode,
+ 0, 0 },
+ { "mr0", FIELD__mr0, REGFILE_MR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ OperandSem_opnd_sem_MR_2_encode, OperandSem_opnd_sem_MR_2_decode,
+ 0, 0 },
+ { "mr1", FIELD__mr1, REGFILE_MR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ OperandSem_opnd_sem_MR_3_encode, OperandSem_opnd_sem_MR_3_decode,
+ 0, 0 },
+ { "mr2", FIELD__mr2, REGFILE_MR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ OperandSem_opnd_sem_MR_4_encode, OperandSem_opnd_sem_MR_4_decode,
+ 0, 0 },
+ { "mr3", FIELD__mr3, REGFILE_MR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ OperandSem_opnd_sem_MR_5_encode, OperandSem_opnd_sem_MR_5_decode,
+ 0, 0 },
+ { "immt", FIELD_t, -1, 0,
+ 0,
+ OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode,
+ 0, 0 },
+ { "imms", FIELD_s, -1, 0,
+ 0,
+ OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode,
+ 0, 0 },
+ { "tp7", FIELD_t, -1, 0,
+ 0,
+ OperandSem_opnd_sem_tp7_encode, OperandSem_opnd_sem_tp7_decode,
+ 0, 0 },
+ { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_xt_wbr15_label_encode, OperandSem_opnd_sem_xt_wbr15_label_decode,
+ Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa },
+ { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_xt_wbr18_label_encode, OperandSem_opnd_sem_xt_wbr18_label_decode,
+ Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa },
+ { "bitindex", FIELD_bitindex, -1, 0,
+ 0,
+ OperandSem_opnd_sem_bitindex_encode, OperandSem_opnd_sem_bitindex_decode,
+ 0, 0 },
+ { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 },
+ { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 },
+ { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 },
+ { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 },
+ { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 },
+ { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 },
+ { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 },
+ { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 },
+ { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 },
+ { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 },
+ { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 },
+ { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 },
+ { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 },
+ { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 },
+ { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 },
+ { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 },
+ { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 },
+ { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 },
+ { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 },
+ { "r3", FIELD_r3, -1, 0, 0, 0, 0, 0, 0 },
+ { "rbit2", FIELD_rbit2, -1, 0, 0, 0, 0, 0, 0 },
+ { "rhi", FIELD_rhi, -1, 0, 0, 0, 0, 0, 0 },
+ { "t3", FIELD_t3, -1, 0, 0, 0, 0, 0, 0 },
+ { "tbit2", FIELD_tbit2, -1, 0, 0, 0, 0, 0, 0 },
+ { "tlo", FIELD_tlo, -1, 0, 0, 0, 0, 0, 0 },
+ { "w", FIELD_w, -1, 0, 0, 0, 0, 0, 0 },
+ { "y", FIELD_y, -1, 0, 0, 0, 0, 0, 0 },
+ { "x", FIELD_x, -1, 0, 0, 0, 0, 0, 0 },
+ { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 },
+ { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 },
+ { "s3to1", FIELD_s3to1, -1, 0, 0, 0, 0, 0, 0 }
+};
+
+enum xtensa_operand_id {
+ OPERAND_soffsetx4,
+ OPERAND_uimm12x8,
+ OPERAND_simm4,
+ OPERAND_arr,
+ OPERAND_ars,
+ OPERAND__ars_invisible,
+ OPERAND_art,
+ OPERAND_ar0,
+ OPERAND_ar4,
+ OPERAND_ar8,
+ OPERAND_ar12,
+ OPERAND_ars_entry,
+ OPERAND_immrx4,
+ OPERAND_lsi4x4,
+ OPERAND_simm7,
+ OPERAND_uimm6,
+ OPERAND_ai4const,
+ OPERAND_b4const,
+ OPERAND_b4constu,
+ OPERAND_uimm8,
+ OPERAND_uimm8x2,
+ OPERAND_uimm8x4,
+ OPERAND_uimm4x16,
+ OPERAND_uimmrx4,
+ OPERAND_simm8,
+ OPERAND_simm8x256,
+ OPERAND_simm12b,
+ OPERAND_msalp32,
+ OPERAND_op2p1,
+ OPERAND_label8,
+ OPERAND_ulabel8,
+ OPERAND_label12,
+ OPERAND_soffset,
+ OPERAND_uimm16x4,
+ OPERAND_bbi,
+ OPERAND_sae,
+ OPERAND_sas,
+ OPERAND_sargt,
+ OPERAND_s,
+ OPERAND_mx,
+ OPERAND_my,
+ OPERAND_mw,
+ OPERAND_mr0,
+ OPERAND_mr1,
+ OPERAND_mr2,
+ OPERAND_mr3,
+ OPERAND_immt,
+ OPERAND_imms,
+ OPERAND_tp7,
+ OPERAND_xt_wbr15_label,
+ OPERAND_xt_wbr18_label,
+ OPERAND_bitindex,
+ OPERAND_t,
+ OPERAND_bbi4,
+ OPERAND_imm12,
+ OPERAND_imm8,
+ OPERAND_imm12b,
+ OPERAND_imm16,
+ OPERAND_m,
+ OPERAND_n,
+ OPERAND_offset,
+ OPERAND_op0,
+ OPERAND_op1,
+ OPERAND_op2,
+ OPERAND_r,
+ OPERAND_sa4,
+ OPERAND_sae4,
+ OPERAND_sal,
+ OPERAND_sas4,
+ OPERAND_sr,
+ OPERAND_st,
+ OPERAND_thi3,
+ OPERAND_imm4,
+ OPERAND_mn,
+ OPERAND_i,
+ OPERAND_imm6lo,
+ OPERAND_imm6hi,
+ OPERAND_imm7lo,
+ OPERAND_imm7hi,
+ OPERAND_z,
+ OPERAND_imm6,
+ OPERAND_imm7,
+ OPERAND_r3,
+ OPERAND_rbit2,
+ OPERAND_rhi,
+ OPERAND_t3,
+ OPERAND_tbit2,
+ OPERAND_tlo,
+ OPERAND_w,
+ OPERAND_y,
+ OPERAND_x,
+ OPERAND_xt_wbr15_imm,
+ OPERAND_xt_wbr18_imm,
+ OPERAND_s3to1
+};
+
+
+/* Iclass table. */
+
+static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
+ { { STATE_PSEXCM }, 'o' },
+ { { STATE_EPC1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
+ { { STATE_DEPC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
+ { { OPERAND_soffsetx4 }, 'i' },
+ { { OPERAND_ar12 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
+ { { OPERAND_soffsetx4 }, 'i' },
+ { { OPERAND_ar8 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
+ { { OPERAND_soffsetx4 }, 'i' },
+ { { OPERAND_ar4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ar12 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ar8 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ar4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
+ { { OPERAND_ars_entry }, 's' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm12x8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'i' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSWOE }, 'i' },
+ { { STATE_WindowBase }, 'm' },
+ { { STATE_WindowStart }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
+ { { STATE_WindowBase }, 'i' },
+ { { STATE_WindowStart }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
+ { { OPERAND_simm4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
+ { { STATE_WindowBase }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
+ { { OPERAND__ars_invisible }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
+ { { STATE_WindowBase }, 'm' },
+ { { STATE_WindowStart }, 'm' },
+ { { STATE_PSCALLINC }, 'o' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSWOE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
+ { { STATE_EPC1 }, 'i' },
+ { { STATE_PSEXCM }, 'o' },
+ { { STATE_WindowBase }, 'm' },
+ { { STATE_WindowStart }, 'm' },
+ { { STATE_PSOWB }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_immrx4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_immrx4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
+ { { STATE_WindowBase }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
+ { { STATE_WindowBase }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
+ { { STATE_WindowBase }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
+ { { STATE_WindowStart }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
+ { { STATE_WindowStart }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
+ { { STATE_WindowStart }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ai4const }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm6 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_lsi4x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
+ { { OPERAND_ars }, 'o' },
+ { { OPERAND_simm7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
+ { { OPERAND__ars_invisible }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_lsi4x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_simm8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_simm8x256 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_b4const }, 'i' },
+ { { OPERAND_label8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_bbi }, 'i' },
+ { { OPERAND_label8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_b4constu }, 'i' },
+ { { OPERAND_label8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_label8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_label12 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
+ { { OPERAND_soffsetx4 }, 'i' },
+ { { OPERAND_ar0 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ar0 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_sae }, 'i' },
+ { { OPERAND_op2p1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
+ { { OPERAND_soffset }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_uimm16x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ulabel8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = {
+ { { STATE_LBEG }, 'o' },
+ { { STATE_LEND }, 'o' },
+ { { STATE_LCOUNT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ulabel8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = {
+ { { STATE_LBEG }, 'o' },
+ { { STATE_LEND }, 'o' },
+ { { STATE_LCOUNT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_simm12b }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
+ { { OPERAND_arr }, 'm' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
+ { { OPERAND__ars_invisible }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32nb_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimmrx4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
+ { { STATE_SAR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
+ { { OPERAND_sas }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
+ { { STATE_SAR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
+ { { STATE_SAR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
+ { { STATE_SAR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
+ { { STATE_SAR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_msalp32 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_sargt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_s }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
+ { { STATE_XTSYNC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_s }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
+ { { STATE_PSWOE }, 'i' },
+ { { STATE_PSCALLINC }, 'i' },
+ { { STATE_PSOWB }, 'i' },
+ { { STATE_PSUM }, 'i' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSINTLEVEL }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = {
+ { { STATE_LEND }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = {
+ { { STATE_LEND }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = {
+ { { STATE_LEND }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = {
+ { { STATE_LCOUNT }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_LCOUNT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_LCOUNT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = {
+ { { STATE_LBEG }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = {
+ { { STATE_LBEG }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = {
+ { { STATE_LBEG }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
+ { { STATE_SAR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
+ { { STATE_SAR }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
+ { { STATE_SAR }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_memctl_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_memctl_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_memctl_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
+ { { STATE_PSWOE }, 'i' },
+ { { STATE_PSCALLINC }, 'i' },
+ { { STATE_PSOWB }, 'i' },
+ { { STATE_PSUM }, 'i' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSINTLEVEL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
+ { { STATE_PSWOE }, 'o' },
+ { { STATE_PSCALLINC }, 'o' },
+ { { STATE_PSOWB }, 'o' },
+ { { STATE_PSUM }, 'o' },
+ { { STATE_PSEXCM }, 'o' },
+ { { STATE_PSINTLEVEL }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
+ { { STATE_PSWOE }, 'm' },
+ { { STATE_PSCALLINC }, 'm' },
+ { { STATE_PSOWB }, 'm' },
+ { { STATE_PSUM }, 'm' },
+ { { STATE_PSEXCM }, 'm' },
+ { { STATE_PSINTLEVEL }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
+ { { STATE_EPC1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
+ { { STATE_EPC1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
+ { { STATE_EPC1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
+ { { STATE_EXCSAVE1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
+ { { STATE_EXCSAVE1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
+ { { STATE_EXCSAVE1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
+ { { STATE_EPC2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
+ { { STATE_EPC2 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
+ { { STATE_EPC2 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
+ { { STATE_EXCSAVE2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
+ { { STATE_EXCSAVE2 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
+ { { STATE_EXCSAVE2 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = {
+ { { STATE_EPC3 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = {
+ { { STATE_EPC3 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = {
+ { { STATE_EPC3 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = {
+ { { STATE_EXCSAVE3 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = {
+ { { STATE_EXCSAVE3 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = {
+ { { STATE_EXCSAVE3 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = {
+ { { STATE_EPC4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = {
+ { { STATE_EPC4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = {
+ { { STATE_EPC4 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = {
+ { { STATE_EXCSAVE4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = {
+ { { STATE_EXCSAVE4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = {
+ { { STATE_EXCSAVE4 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = {
+ { { STATE_EPC5 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = {
+ { { STATE_EPC5 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = {
+ { { STATE_EPC5 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = {
+ { { STATE_EXCSAVE5 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = {
+ { { STATE_EXCSAVE5 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = {
+ { { STATE_EXCSAVE5 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = {
+ { { STATE_EPC6 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = {
+ { { STATE_EPC6 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = {
+ { { STATE_EPC6 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = {
+ { { STATE_EXCSAVE6 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = {
+ { { STATE_EXCSAVE6 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = {
+ { { STATE_EXCSAVE6 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = {
+ { { STATE_EPC7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = {
+ { { STATE_EPC7 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = {
+ { { STATE_EPC7 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = {
+ { { STATE_EXCSAVE7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = {
+ { { STATE_EXCSAVE7 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = {
+ { { STATE_EXCSAVE7 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
+ { { STATE_EPS2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
+ { { STATE_EPS2 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
+ { { STATE_EPS2 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = {
+ { { STATE_EPS3 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = {
+ { { STATE_EPS3 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = {
+ { { STATE_EPS3 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = {
+ { { STATE_EPS4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = {
+ { { STATE_EPS4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = {
+ { { STATE_EPS4 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = {
+ { { STATE_EPS5 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = {
+ { { STATE_EPS5 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = {
+ { { STATE_EPS5 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = {
+ { { STATE_EPS6 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = {
+ { { STATE_EPS6 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = {
+ { { STATE_EPS6 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = {
+ { { STATE_EPS7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = {
+ { { STATE_EPS7 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = {
+ { { STATE_EPS7 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
+ { { STATE_EXCVADDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
+ { { STATE_EXCVADDR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
+ { { STATE_EXCVADDR }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
+ { { STATE_DEPC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
+ { { STATE_DEPC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
+ { { STATE_DEPC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
+ { { STATE_EXCCAUSE }, 'i' },
+ { { STATE_XTSYNC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
+ { { STATE_EXCCAUSE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
+ { { STATE_EXCCAUSE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
+ { { STATE_MISC0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
+ { { STATE_MISC0 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
+ { { STATE_MISC0 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
+ { { STATE_MISC1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
+ { { STATE_MISC1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
+ { { STATE_MISC1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = {
+ { { STATE_VECBASE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = {
+ { { STATE_VECBASE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = {
+ { { STATE_VECBASE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_mul16_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_mul32_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = {
+ { { STATE_ACC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_my }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = {
+ { { STATE_ACC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = {
+ { { OPERAND_mx }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = {
+ { { STATE_ACC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = {
+ { { OPERAND_mx }, 'i' },
+ { { OPERAND_my }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = {
+ { { STATE_ACC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = {
+ { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_my }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = {
+ { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = {
+ { { OPERAND_mx }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = {
+ { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = {
+ { { OPERAND_mx }, 'i' },
+ { { OPERAND_my }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = {
+ { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = {
+ { { OPERAND_mw }, 'o' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_mx }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = {
+ { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = {
+ { { OPERAND_mw }, 'o' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_mx }, 'i' },
+ { { OPERAND_my }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = {
+ { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = {
+ { { OPERAND_mw }, 'o' },
+ { { OPERAND_ars }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_mr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_mr0 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = {
+ { { OPERAND_art }, 'm' },
+ { { OPERAND_mr0 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_mr1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_mr1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = {
+ { { OPERAND_art }, 'm' },
+ { { OPERAND_mr1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_mr2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_mr2 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = {
+ { { OPERAND_art }, 'm' },
+ { { OPERAND_mr2 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_mr3 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_mr3 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = {
+ { { OPERAND_art }, 'm' },
+ { { OPERAND_mr3 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = {
+ { { STATE_ACC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = {
+ { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = {
+ { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = {
+ { { STATE_ACC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = {
+ { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = {
+ { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
+ { { OPERAND_s }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
+ { { STATE_PSWOE }, 'o' },
+ { { STATE_PSCALLINC }, 'o' },
+ { { STATE_PSOWB }, 'o' },
+ { { STATE_PSUM }, 'o' },
+ { { STATE_PSEXCM }, 'o' },
+ { { STATE_PSINTLEVEL }, 'o' },
+ { { STATE_EPC1 }, 'i' },
+ { { STATE_EPC2 }, 'i' },
+ { { STATE_EPC3 }, 'i' },
+ { { STATE_EPC4 }, 'i' },
+ { { STATE_EPC5 }, 'i' },
+ { { STATE_EPC6 }, 'i' },
+ { { STATE_EPC7 }, 'i' },
+ { { STATE_EPS2 }, 'i' },
+ { { STATE_EPS3 }, 'i' },
+ { { STATE_EPS4 }, 'i' },
+ { { STATE_EPS5 }, 'i' },
+ { { STATE_EPS6 }, 'i' },
+ { { STATE_EPS7 }, 'i' },
+ { { STATE_InOCDMode }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
+ { { OPERAND_s }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
+ { { STATE_PSINTLEVEL }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
+ { { STATE_INTERRUPT }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
+ { { STATE_INTENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
+ { { STATE_INTENABLE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
+ { { STATE_INTENABLE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
+ { { OPERAND_imms }, 'i' },
+ { { OPERAND_immt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSINTLEVEL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
+ { { OPERAND_imms }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSINTLEVEL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = {
+ { { STATE_DBREAKA0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = {
+ { { STATE_DBREAKA0 }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = {
+ { { STATE_DBREAKA0 }, 'm' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = {
+ { { STATE_DBREAKC0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = {
+ { { STATE_DBREAKC0 }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = {
+ { { STATE_DBREAKC0 }, 'm' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = {
+ { { STATE_DBREAKA1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = {
+ { { STATE_DBREAKA1 }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = {
+ { { STATE_DBREAKA1 }, 'm' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = {
+ { { STATE_DBREAKC1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = {
+ { { STATE_DBREAKC1 }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = {
+ { { STATE_DBREAKC1 }, 'm' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = {
+ { { STATE_IBREAKA0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = {
+ { { STATE_IBREAKA0 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = {
+ { { STATE_IBREAKA0 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = {
+ { { STATE_IBREAKA1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = {
+ { { STATE_IBREAKA1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = {
+ { { STATE_IBREAKA1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = {
+ { { STATE_IBREAKENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = {
+ { { STATE_IBREAKENABLE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = {
+ { { STATE_IBREAKENABLE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
+ { { STATE_DEBUGCAUSE }, 'i' },
+ { { STATE_DBNUM }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
+ { { STATE_DEBUGCAUSE }, 'o' },
+ { { STATE_DBNUM }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
+ { { STATE_DEBUGCAUSE }, 'm' },
+ { { STATE_DBNUM }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
+ { { STATE_ICOUNT }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_ICOUNT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_ICOUNT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
+ { { STATE_ICOUNTLEVEL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
+ { { STATE_ICOUNTLEVEL }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
+ { { STATE_ICOUNTLEVEL }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
+ { { STATE_DDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_DDR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_DDR }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_args[] = {
+ { { OPERAND_ars }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_InOCDMode }, 'i' },
+ { { STATE_DDR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_args[] = {
+ { { OPERAND_ars }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_stateArgs[] = {
+ { { STATE_InOCDMode }, 'i' },
+ { { STATE_DDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = {
+ { { OPERAND_imms }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = {
+ { { STATE_InOCDMode }, 'm' },
+ { { STATE_EPC6 }, 'i' },
+ { { STATE_PSWOE }, 'o' },
+ { { STATE_PSCALLINC }, 'o' },
+ { { STATE_PSOWB }, 'o' },
+ { { STATE_PSUM }, 'o' },
+ { { STATE_PSEXCM }, 'o' },
+ { { STATE_PSINTLEVEL }, 'o' },
+ { { STATE_EPS6 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = {
+ { { STATE_InOCDMode }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = {
+ { { STATE_CCOUNT }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_CCOUNT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_CCOUNT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = {
+ { { STATE_CCOMPARE0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = {
+ { { STATE_CCOMPARE0 }, 'o' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = {
+ { { STATE_CCOMPARE0 }, 'm' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = {
+ { { STATE_CCOMPARE1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = {
+ { { STATE_CCOMPARE1 }, 'o' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = {
+ { { STATE_CCOMPARE1 }, 'm' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = {
+ { { STATE_CCOMPARE2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = {
+ { { STATE_CCOMPARE2 }, 'o' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = {
+ { { STATE_CCOMPARE2 }, 'm' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm4x16 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_dcache_dyn_args[] = {
+ { { OPERAND_ars }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm4x16 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm4x16 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_tp7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_tp7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = {
+ { { OPERAND_art }, 'm' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = {
+ { { STATE_SCOMPARE1 }, 'i' },
+ { { STATE_XTSYNC }, 'i' },
+ { { STATE_SCOMPARE1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = {
+ { { STATE_SCOMPARE1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = {
+ { { STATE_SCOMPARE1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = {
+ { { STATE_SCOMPARE1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = {
+ { { STATE_ATOMCTL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = {
+ { { STATE_ATOMCTL }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = {
+ { { STATE_ATOMCTL }, 'm' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_div_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rer_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rer_stateArgs[] = {
+ { { STATE_ERI_RAW_INTERLOCK }, 'i' }
+};
+
+static xtensa_interface Iclass_xt_iclass_rer_intfArgs[] = {
+ INTERFACE_ERI_RD_In,
+ INTERFACE_ERI_RD_Out
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wer_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wer_stateArgs[] = {
+ { { STATE_ERI_RAW_INTERLOCK }, 'o' }
+};
+
+static xtensa_interface Iclass_xt_iclass_wer_intfArgs[] = {
+ INTERFACE_ERI_WR_In,
+ INTERFACE_ERI_WR_Out
+};
+
+static xtensa_arg_internal Iclass_rur_expstate_args[] = {
+ { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_expstate_stateArgs[] = {
+ { { STATE_EXPSTATE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_expstate_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_expstate_stateArgs[] = {
+ { { STATE_EXPSTATE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_interface Iclass_iclass_READ_IMPWIRE_intfArgs[] = {
+ INTERFACE_IMPWIRE
+};
+
+static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_args[] = {
+ { { OPERAND_bitindex }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_stateArgs[] = {
+ { { STATE_EXPSTATE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_args[] = {
+ { { OPERAND_bitindex }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_stateArgs[] = {
+ { { STATE_EXPSTATE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_stateArgs[] = {
+ { { STATE_EXPSTATE }, 'm' }
+};
+
+static xtensa_iclass_internal iclasses[] = {
+ { 0, 0 /* xt_iclass_excw */,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_rfe */,
+ 2, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_rfde */,
+ 1, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_syscall */,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_call12_args,
+ 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_call8_args,
+ 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_call4_args,
+ 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_callx12_args,
+ 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_callx8_args,
+ 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_callx4_args,
+ 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_entry_args,
+ 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_movsp_args,
+ 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rotw_args,
+ 1, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_retw_args,
+ 5, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_rfwou */,
+ 5, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_l32e_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s32e_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_windowbase_args,
+ 1, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_windowbase_args,
+ 1, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_windowbase_args,
+ 1, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_windowstart_args,
+ 1, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_windowstart_args,
+ 1, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_windowstart_args,
+ 1, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_add_n_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_addi_n_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_bz6_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_ill_n */,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_loadi4_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_mov_n_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_movi_n_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_nopn */,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_retn_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_storei4_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_addi_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_addmi_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_addsub_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bit_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bsi8_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bsi8b_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bsi8u_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bst8_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_bsz12_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_call0_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_callx0_args,
+ 0, 0, 0, 0 },
+ { 4, Iclass_xt_iclass_exti_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_ill */,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_jump_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_jumpx_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_l16ui_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_l16si_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_l32i_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_l32r_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_l8i_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_loop_args,
+ 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_loopz_args,
+ 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_movi_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_movz_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_neg_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_nop */,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_return_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_simcall */,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s16i_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s32i_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s32nb_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s8i_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_sar_args,
+ 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_sari_args,
+ 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_shifts_args,
+ 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_shiftst_args,
+ 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_shiftt_args,
+ 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_slli_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_srai_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_srli_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_memw */,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_extw */,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_isync */,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_sync */,
+ 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_rsil_args,
+ 6, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_lend_args,
+ 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_lend_args,
+ 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_lend_args,
+ 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_lcount_args,
+ 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_lcount_args,
+ 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_lcount_args,
+ 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_lbeg_args,
+ 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_lbeg_args,
+ 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_lbeg_args,
+ 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_sar_args,
+ 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_sar_args,
+ 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_sar_args,
+ 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_memctl_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_memctl_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_memctl_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_litbase_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_litbase_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_litbase_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_configid0_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_configid0_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_configid1_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ps_args,
+ 6, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ps_args,
+ 6, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ps_args,
+ 6, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc1_args,
+ 1, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc1_args,
+ 1, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc1_args,
+ 1, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave1_args,
+ 1, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave1_args,
+ 1, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave1_args,
+ 1, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc2_args,
+ 1, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc2_args,
+ 1, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc2_args,
+ 1, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave2_args,
+ 1, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave2_args,
+ 1, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave2_args,
+ 1, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc3_args,
+ 1, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc3_args,
+ 1, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc3_args,
+ 1, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave3_args,
+ 1, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave3_args,
+ 1, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave3_args,
+ 1, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc4_args,
+ 1, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc4_args,
+ 1, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc4_args,
+ 1, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave4_args,
+ 1, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave4_args,
+ 1, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave4_args,
+ 1, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc5_args,
+ 1, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc5_args,
+ 1, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc5_args,
+ 1, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave5_args,
+ 1, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave5_args,
+ 1, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave5_args,
+ 1, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc6_args,
+ 1, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc6_args,
+ 1, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc6_args,
+ 1, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave6_args,
+ 1, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave6_args,
+ 1, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave6_args,
+ 1, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc7_args,
+ 1, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc7_args,
+ 1, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc7_args,
+ 1, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave7_args,
+ 1, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave7_args,
+ 1, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave7_args,
+ 1, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps2_args,
+ 1, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps2_args,
+ 1, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps2_args,
+ 1, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps3_args,
+ 1, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps3_args,
+ 1, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps3_args,
+ 1, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps4_args,
+ 1, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps4_args,
+ 1, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps4_args,
+ 1, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps5_args,
+ 1, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps5_args,
+ 1, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps5_args,
+ 1, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps6_args,
+ 1, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps6_args,
+ 1, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps6_args,
+ 1, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps7_args,
+ 1, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps7_args,
+ 1, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps7_args,
+ 1, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excvaddr_args,
+ 1, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excvaddr_args,
+ 1, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excvaddr_args,
+ 1, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_depc_args,
+ 1, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_depc_args,
+ 1, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_depc_args,
+ 1, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_exccause_args,
+ 2, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_exccause_args,
+ 1, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_exccause_args,
+ 1, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_misc0_args,
+ 1, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_misc0_args,
+ 1, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_misc0_args,
+ 1, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_misc1_args,
+ 1, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_misc1_args,
+ 1, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_misc1_args,
+ 1, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_prid_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_vecbase_args,
+ 1, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_vecbase_args,
+ 1, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_vecbase_args,
+ 1, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 },
+ { 3, Iclass_xt_mul16_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_mul32_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16_aa_args,
+ 1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16_ad_args,
+ 1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16_da_args,
+ 1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16_dd_args,
+ 1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16a_aa_args,
+ 1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16a_ad_args,
+ 1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16a_da_args,
+ 1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16a_dd_args,
+ 1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 },
+ { 4, Iclass_xt_iclass_mac16al_da_args,
+ 1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 },
+ { 4, Iclass_xt_iclass_mac16al_dd_args,
+ 1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16_l_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_rsr_m0_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_wsr_m0_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_xsr_m0_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_rsr_m1_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_wsr_m1_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_xsr_m1_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_rsr_m2_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_wsr_m2_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_xsr_m2_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_rsr_m3_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_wsr_m3_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_xsr_m3_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_acclo_args,
+ 1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_acclo_args,
+ 1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_acclo_args,
+ 1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_acchi_args,
+ 1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_acchi_args,
+ 1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_acchi_args,
+ 1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rfi_args,
+ 20, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wait_args,
+ 1, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_interrupt_args,
+ 1, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_intset_args,
+ 2, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_intclear_args,
+ 2, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_intenable_args,
+ 1, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_intenable_args,
+ 1, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_intenable_args,
+ 1, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_break_args,
+ 2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_break_n_args,
+ 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_dbreaka0_args,
+ 1, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_dbreaka0_args,
+ 2, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_dbreaka0_args,
+ 2, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_dbreakc0_args,
+ 1, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_dbreakc0_args,
+ 2, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_dbreakc0_args,
+ 2, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_dbreaka1_args,
+ 1, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_dbreaka1_args,
+ 2, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_dbreaka1_args,
+ 2, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_dbreakc1_args,
+ 1, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_dbreakc1_args,
+ 2, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_dbreakc1_args,
+ 2, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ibreaka0_args,
+ 1, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ibreaka0_args,
+ 1, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ibreaka0_args,
+ 1, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ibreaka1_args,
+ 1, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ibreaka1_args,
+ 1, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ibreaka1_args,
+ 1, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ibreakenable_args,
+ 1, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ibreakenable_args,
+ 1, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ibreakenable_args,
+ 1, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_debugcause_args,
+ 2, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_debugcause_args,
+ 2, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_debugcause_args,
+ 2, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_icount_args,
+ 1, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_icount_args,
+ 2, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_icount_args,
+ 2, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_icountlevel_args,
+ 1, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_icountlevel_args,
+ 1, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_icountlevel_args,
+ 1, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ddr_args,
+ 1, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ddr_args,
+ 2, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ddr_args,
+ 2, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_lddr32_p_args,
+ 3, Iclass_xt_iclass_lddr32_p_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_sddr32_p_args,
+ 2, Iclass_xt_iclass_sddr32_p_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rfdo_args,
+ 9, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_rfdd */,
+ 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_mmid_args,
+ 1, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ccount_args,
+ 1, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ccount_args,
+ 2, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ccount_args,
+ 2, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ccompare0_args,
+ 1, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ccompare0_args,
+ 2, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ccompare0_args,
+ 2, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ccompare1_args,
+ 1, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ccompare1_args,
+ 2, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ccompare1_args,
+ 2, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ccompare2_args,
+ 1, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ccompare2_args,
+ 2, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ccompare2_args,
+ 2, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_icache_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_icache_lock_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_icache_inv_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_licx_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_sicx_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_dcache_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_dcache_dyn_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_dcache_ind_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_dcache_inv_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_dpf_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_dcache_lock_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_sdct_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_ldct_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_idtlb_args,
+ 1, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_rdtlb_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_wdtlb_args,
+ 1, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_iitlb_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_ritlb_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_witlb_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_clamp_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_minmax_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_nsa_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_sx_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_l32ai_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s32ri_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s32c1i_args,
+ 3, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_scompare1_args,
+ 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_scompare1_args,
+ 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_scompare1_args,
+ 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_atomctl_args,
+ 1, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_atomctl_args,
+ 2, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_atomctl_args,
+ 2, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_div_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_rer_args,
+ 1, Iclass_xt_iclass_rer_stateArgs, 2, Iclass_xt_iclass_rer_intfArgs },
+ { 2, Iclass_xt_iclass_wer_args,
+ 1, Iclass_xt_iclass_wer_stateArgs, 2, Iclass_xt_iclass_wer_intfArgs },
+ { 1, Iclass_rur_expstate_args,
+ 1, Iclass_rur_expstate_stateArgs, 0, 0 },
+ { 1, Iclass_wur_expstate_args,
+ 1, Iclass_wur_expstate_stateArgs, 0, 0 },
+ { 1, Iclass_iclass_READ_IMPWIRE_args,
+ 0, 0, 1, Iclass_iclass_READ_IMPWIRE_intfArgs },
+ { 1, Iclass_iclass_SETB_EXPSTATE_args,
+ 1, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 },
+ { 1, Iclass_iclass_CLRB_EXPSTATE_args,
+ 1, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 },
+ { 2, Iclass_iclass_WRMSK_EXPSTATE_args,
+ 1, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 }
+};
+
+enum xtensa_iclass_id {
+ ICLASS_xt_iclass_excw,
+ ICLASS_xt_iclass_rfe,
+ ICLASS_xt_iclass_rfde,
+ ICLASS_xt_iclass_syscall,
+ ICLASS_xt_iclass_call12,
+ ICLASS_xt_iclass_call8,
+ ICLASS_xt_iclass_call4,
+ ICLASS_xt_iclass_callx12,
+ ICLASS_xt_iclass_callx8,
+ ICLASS_xt_iclass_callx4,
+ ICLASS_xt_iclass_entry,
+ ICLASS_xt_iclass_movsp,
+ ICLASS_xt_iclass_rotw,
+ ICLASS_xt_iclass_retw,
+ ICLASS_xt_iclass_rfwou,
+ ICLASS_xt_iclass_l32e,
+ ICLASS_xt_iclass_s32e,
+ ICLASS_xt_iclass_rsr_windowbase,
+ ICLASS_xt_iclass_wsr_windowbase,
+ ICLASS_xt_iclass_xsr_windowbase,
+ ICLASS_xt_iclass_rsr_windowstart,
+ ICLASS_xt_iclass_wsr_windowstart,
+ ICLASS_xt_iclass_xsr_windowstart,
+ ICLASS_xt_iclass_add_n,
+ ICLASS_xt_iclass_addi_n,
+ ICLASS_xt_iclass_bz6,
+ ICLASS_xt_iclass_ill_n,
+ ICLASS_xt_iclass_loadi4,
+ ICLASS_xt_iclass_mov_n,
+ ICLASS_xt_iclass_movi_n,
+ ICLASS_xt_iclass_nopn,
+ ICLASS_xt_iclass_retn,
+ ICLASS_xt_iclass_storei4,
+ ICLASS_xt_iclass_addi,
+ ICLASS_xt_iclass_addmi,
+ ICLASS_xt_iclass_addsub,
+ ICLASS_xt_iclass_bit,
+ ICLASS_xt_iclass_bsi8,
+ ICLASS_xt_iclass_bsi8b,
+ ICLASS_xt_iclass_bsi8u,
+ ICLASS_xt_iclass_bst8,
+ ICLASS_xt_iclass_bsz12,
+ ICLASS_xt_iclass_call0,
+ ICLASS_xt_iclass_callx0,
+ ICLASS_xt_iclass_exti,
+ ICLASS_xt_iclass_ill,
+ ICLASS_xt_iclass_jump,
+ ICLASS_xt_iclass_jumpx,
+ ICLASS_xt_iclass_l16ui,
+ ICLASS_xt_iclass_l16si,
+ ICLASS_xt_iclass_l32i,
+ ICLASS_xt_iclass_l32r,
+ ICLASS_xt_iclass_l8i,
+ ICLASS_xt_iclass_loop,
+ ICLASS_xt_iclass_loopz,
+ ICLASS_xt_iclass_movi,
+ ICLASS_xt_iclass_movz,
+ ICLASS_xt_iclass_neg,
+ ICLASS_xt_iclass_nop,
+ ICLASS_xt_iclass_return,
+ ICLASS_xt_iclass_simcall,
+ ICLASS_xt_iclass_s16i,
+ ICLASS_xt_iclass_s32i,
+ ICLASS_xt_iclass_s32nb,
+ ICLASS_xt_iclass_s8i,
+ ICLASS_xt_iclass_sar,
+ ICLASS_xt_iclass_sari,
+ ICLASS_xt_iclass_shifts,
+ ICLASS_xt_iclass_shiftst,
+ ICLASS_xt_iclass_shiftt,
+ ICLASS_xt_iclass_slli,
+ ICLASS_xt_iclass_srai,
+ ICLASS_xt_iclass_srli,
+ ICLASS_xt_iclass_memw,
+ ICLASS_xt_iclass_extw,
+ ICLASS_xt_iclass_isync,
+ ICLASS_xt_iclass_sync,
+ ICLASS_xt_iclass_rsil,
+ ICLASS_xt_iclass_rsr_lend,
+ ICLASS_xt_iclass_wsr_lend,
+ ICLASS_xt_iclass_xsr_lend,
+ ICLASS_xt_iclass_rsr_lcount,
+ ICLASS_xt_iclass_wsr_lcount,
+ ICLASS_xt_iclass_xsr_lcount,
+ ICLASS_xt_iclass_rsr_lbeg,
+ ICLASS_xt_iclass_wsr_lbeg,
+ ICLASS_xt_iclass_xsr_lbeg,
+ ICLASS_xt_iclass_rsr_sar,
+ ICLASS_xt_iclass_wsr_sar,
+ ICLASS_xt_iclass_xsr_sar,
+ ICLASS_xt_iclass_rsr_memctl,
+ ICLASS_xt_iclass_wsr_memctl,
+ ICLASS_xt_iclass_xsr_memctl,
+ ICLASS_xt_iclass_rsr_litbase,
+ ICLASS_xt_iclass_wsr_litbase,
+ ICLASS_xt_iclass_xsr_litbase,
+ ICLASS_xt_iclass_rsr_configid0,
+ ICLASS_xt_iclass_wsr_configid0,
+ ICLASS_xt_iclass_rsr_configid1,
+ ICLASS_xt_iclass_rsr_ps,
+ ICLASS_xt_iclass_wsr_ps,
+ ICLASS_xt_iclass_xsr_ps,
+ ICLASS_xt_iclass_rsr_epc1,
+ ICLASS_xt_iclass_wsr_epc1,
+ ICLASS_xt_iclass_xsr_epc1,
+ ICLASS_xt_iclass_rsr_excsave1,
+ ICLASS_xt_iclass_wsr_excsave1,
+ ICLASS_xt_iclass_xsr_excsave1,
+ ICLASS_xt_iclass_rsr_epc2,
+ ICLASS_xt_iclass_wsr_epc2,
+ ICLASS_xt_iclass_xsr_epc2,
+ ICLASS_xt_iclass_rsr_excsave2,
+ ICLASS_xt_iclass_wsr_excsave2,
+ ICLASS_xt_iclass_xsr_excsave2,
+ ICLASS_xt_iclass_rsr_epc3,
+ ICLASS_xt_iclass_wsr_epc3,
+ ICLASS_xt_iclass_xsr_epc3,
+ ICLASS_xt_iclass_rsr_excsave3,
+ ICLASS_xt_iclass_wsr_excsave3,
+ ICLASS_xt_iclass_xsr_excsave3,
+ ICLASS_xt_iclass_rsr_epc4,
+ ICLASS_xt_iclass_wsr_epc4,
+ ICLASS_xt_iclass_xsr_epc4,
+ ICLASS_xt_iclass_rsr_excsave4,
+ ICLASS_xt_iclass_wsr_excsave4,
+ ICLASS_xt_iclass_xsr_excsave4,
+ ICLASS_xt_iclass_rsr_epc5,
+ ICLASS_xt_iclass_wsr_epc5,
+ ICLASS_xt_iclass_xsr_epc5,
+ ICLASS_xt_iclass_rsr_excsave5,
+ ICLASS_xt_iclass_wsr_excsave5,
+ ICLASS_xt_iclass_xsr_excsave5,
+ ICLASS_xt_iclass_rsr_epc6,
+ ICLASS_xt_iclass_wsr_epc6,
+ ICLASS_xt_iclass_xsr_epc6,
+ ICLASS_xt_iclass_rsr_excsave6,
+ ICLASS_xt_iclass_wsr_excsave6,
+ ICLASS_xt_iclass_xsr_excsave6,
+ ICLASS_xt_iclass_rsr_epc7,
+ ICLASS_xt_iclass_wsr_epc7,
+ ICLASS_xt_iclass_xsr_epc7,
+ ICLASS_xt_iclass_rsr_excsave7,
+ ICLASS_xt_iclass_wsr_excsave7,
+ ICLASS_xt_iclass_xsr_excsave7,
+ ICLASS_xt_iclass_rsr_eps2,
+ ICLASS_xt_iclass_wsr_eps2,
+ ICLASS_xt_iclass_xsr_eps2,
+ ICLASS_xt_iclass_rsr_eps3,
+ ICLASS_xt_iclass_wsr_eps3,
+ ICLASS_xt_iclass_xsr_eps3,
+ ICLASS_xt_iclass_rsr_eps4,
+ ICLASS_xt_iclass_wsr_eps4,
+ ICLASS_xt_iclass_xsr_eps4,
+ ICLASS_xt_iclass_rsr_eps5,
+ ICLASS_xt_iclass_wsr_eps5,
+ ICLASS_xt_iclass_xsr_eps5,
+ ICLASS_xt_iclass_rsr_eps6,
+ ICLASS_xt_iclass_wsr_eps6,
+ ICLASS_xt_iclass_xsr_eps6,
+ ICLASS_xt_iclass_rsr_eps7,
+ ICLASS_xt_iclass_wsr_eps7,
+ ICLASS_xt_iclass_xsr_eps7,
+ ICLASS_xt_iclass_rsr_excvaddr,
+ ICLASS_xt_iclass_wsr_excvaddr,
+ ICLASS_xt_iclass_xsr_excvaddr,
+ ICLASS_xt_iclass_rsr_depc,
+ ICLASS_xt_iclass_wsr_depc,
+ ICLASS_xt_iclass_xsr_depc,
+ ICLASS_xt_iclass_rsr_exccause,
+ ICLASS_xt_iclass_wsr_exccause,
+ ICLASS_xt_iclass_xsr_exccause,
+ ICLASS_xt_iclass_rsr_misc0,
+ ICLASS_xt_iclass_wsr_misc0,
+ ICLASS_xt_iclass_xsr_misc0,
+ ICLASS_xt_iclass_rsr_misc1,
+ ICLASS_xt_iclass_wsr_misc1,
+ ICLASS_xt_iclass_xsr_misc1,
+ ICLASS_xt_iclass_rsr_prid,
+ ICLASS_xt_iclass_rsr_vecbase,
+ ICLASS_xt_iclass_wsr_vecbase,
+ ICLASS_xt_iclass_xsr_vecbase,
+ ICLASS_xt_mul16,
+ ICLASS_xt_mul32,
+ ICLASS_xt_iclass_mac16_aa,
+ ICLASS_xt_iclass_mac16_ad,
+ ICLASS_xt_iclass_mac16_da,
+ ICLASS_xt_iclass_mac16_dd,
+ ICLASS_xt_iclass_mac16a_aa,
+ ICLASS_xt_iclass_mac16a_ad,
+ ICLASS_xt_iclass_mac16a_da,
+ ICLASS_xt_iclass_mac16a_dd,
+ ICLASS_xt_iclass_mac16al_da,
+ ICLASS_xt_iclass_mac16al_dd,
+ ICLASS_xt_iclass_mac16_l,
+ ICLASS_xt_iclass_rsr_m0,
+ ICLASS_xt_iclass_wsr_m0,
+ ICLASS_xt_iclass_xsr_m0,
+ ICLASS_xt_iclass_rsr_m1,
+ ICLASS_xt_iclass_wsr_m1,
+ ICLASS_xt_iclass_xsr_m1,
+ ICLASS_xt_iclass_rsr_m2,
+ ICLASS_xt_iclass_wsr_m2,
+ ICLASS_xt_iclass_xsr_m2,
+ ICLASS_xt_iclass_rsr_m3,
+ ICLASS_xt_iclass_wsr_m3,
+ ICLASS_xt_iclass_xsr_m3,
+ ICLASS_xt_iclass_rsr_acclo,
+ ICLASS_xt_iclass_wsr_acclo,
+ ICLASS_xt_iclass_xsr_acclo,
+ ICLASS_xt_iclass_rsr_acchi,
+ ICLASS_xt_iclass_wsr_acchi,
+ ICLASS_xt_iclass_xsr_acchi,
+ ICLASS_xt_iclass_rfi,
+ ICLASS_xt_iclass_wait,
+ ICLASS_xt_iclass_rsr_interrupt,
+ ICLASS_xt_iclass_wsr_intset,
+ ICLASS_xt_iclass_wsr_intclear,
+ ICLASS_xt_iclass_rsr_intenable,
+ ICLASS_xt_iclass_wsr_intenable,
+ ICLASS_xt_iclass_xsr_intenable,
+ ICLASS_xt_iclass_break,
+ ICLASS_xt_iclass_break_n,
+ ICLASS_xt_iclass_rsr_dbreaka0,
+ ICLASS_xt_iclass_wsr_dbreaka0,
+ ICLASS_xt_iclass_xsr_dbreaka0,
+ ICLASS_xt_iclass_rsr_dbreakc0,
+ ICLASS_xt_iclass_wsr_dbreakc0,
+ ICLASS_xt_iclass_xsr_dbreakc0,
+ ICLASS_xt_iclass_rsr_dbreaka1,
+ ICLASS_xt_iclass_wsr_dbreaka1,
+ ICLASS_xt_iclass_xsr_dbreaka1,
+ ICLASS_xt_iclass_rsr_dbreakc1,
+ ICLASS_xt_iclass_wsr_dbreakc1,
+ ICLASS_xt_iclass_xsr_dbreakc1,
+ ICLASS_xt_iclass_rsr_ibreaka0,
+ ICLASS_xt_iclass_wsr_ibreaka0,
+ ICLASS_xt_iclass_xsr_ibreaka0,
+ ICLASS_xt_iclass_rsr_ibreaka1,
+ ICLASS_xt_iclass_wsr_ibreaka1,
+ ICLASS_xt_iclass_xsr_ibreaka1,
+ ICLASS_xt_iclass_rsr_ibreakenable,
+ ICLASS_xt_iclass_wsr_ibreakenable,
+ ICLASS_xt_iclass_xsr_ibreakenable,
+ ICLASS_xt_iclass_rsr_debugcause,
+ ICLASS_xt_iclass_wsr_debugcause,
+ ICLASS_xt_iclass_xsr_debugcause,
+ ICLASS_xt_iclass_rsr_icount,
+ ICLASS_xt_iclass_wsr_icount,
+ ICLASS_xt_iclass_xsr_icount,
+ ICLASS_xt_iclass_rsr_icountlevel,
+ ICLASS_xt_iclass_wsr_icountlevel,
+ ICLASS_xt_iclass_xsr_icountlevel,
+ ICLASS_xt_iclass_rsr_ddr,
+ ICLASS_xt_iclass_wsr_ddr,
+ ICLASS_xt_iclass_xsr_ddr,
+ ICLASS_xt_iclass_lddr32_p,
+ ICLASS_xt_iclass_sddr32_p,
+ ICLASS_xt_iclass_rfdo,
+ ICLASS_xt_iclass_rfdd,
+ ICLASS_xt_iclass_wsr_mmid,
+ ICLASS_xt_iclass_rsr_ccount,
+ ICLASS_xt_iclass_wsr_ccount,
+ ICLASS_xt_iclass_xsr_ccount,
+ ICLASS_xt_iclass_rsr_ccompare0,
+ ICLASS_xt_iclass_wsr_ccompare0,
+ ICLASS_xt_iclass_xsr_ccompare0,
+ ICLASS_xt_iclass_rsr_ccompare1,
+ ICLASS_xt_iclass_wsr_ccompare1,
+ ICLASS_xt_iclass_xsr_ccompare1,
+ ICLASS_xt_iclass_rsr_ccompare2,
+ ICLASS_xt_iclass_wsr_ccompare2,
+ ICLASS_xt_iclass_xsr_ccompare2,
+ ICLASS_xt_iclass_icache,
+ ICLASS_xt_iclass_icache_lock,
+ ICLASS_xt_iclass_icache_inv,
+ ICLASS_xt_iclass_licx,
+ ICLASS_xt_iclass_sicx,
+ ICLASS_xt_iclass_dcache,
+ ICLASS_xt_iclass_dcache_dyn,
+ ICLASS_xt_iclass_dcache_ind,
+ ICLASS_xt_iclass_dcache_inv,
+ ICLASS_xt_iclass_dpf,
+ ICLASS_xt_iclass_dcache_lock,
+ ICLASS_xt_iclass_sdct,
+ ICLASS_xt_iclass_ldct,
+ ICLASS_xt_iclass_idtlb,
+ ICLASS_xt_iclass_rdtlb,
+ ICLASS_xt_iclass_wdtlb,
+ ICLASS_xt_iclass_iitlb,
+ ICLASS_xt_iclass_ritlb,
+ ICLASS_xt_iclass_witlb,
+ ICLASS_xt_iclass_clamp,
+ ICLASS_xt_iclass_minmax,
+ ICLASS_xt_iclass_nsa,
+ ICLASS_xt_iclass_sx,
+ ICLASS_xt_iclass_l32ai,
+ ICLASS_xt_iclass_s32ri,
+ ICLASS_xt_iclass_s32c1i,
+ ICLASS_xt_iclass_rsr_scompare1,
+ ICLASS_xt_iclass_wsr_scompare1,
+ ICLASS_xt_iclass_xsr_scompare1,
+ ICLASS_xt_iclass_rsr_atomctl,
+ ICLASS_xt_iclass_wsr_atomctl,
+ ICLASS_xt_iclass_xsr_atomctl,
+ ICLASS_xt_iclass_div,
+ ICLASS_xt_iclass_rer,
+ ICLASS_xt_iclass_wer,
+ ICLASS_rur_expstate,
+ ICLASS_wur_expstate,
+ ICLASS_iclass_READ_IMPWIRE,
+ ICLASS_iclass_SETB_EXPSTATE,
+ ICLASS_iclass_CLRB_EXPSTATE,
+ ICLASS_iclass_WRMSK_EXPSTATE
+};
+
+
+/* Opcode encodings. */
+
+static void
+Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2080;
+}
+
+static void
+Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3000;
+}
+
+static void
+Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3200;
+}
+
+static void
+Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5000;
+}
+
+static void
+Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x35;
+}
+
+static void
+Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x25;
+}
+
+static void
+Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x15;
+}
+
+static void
+Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf0;
+}
+
+static void
+Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe0;
+}
+
+static void
+Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd0;
+}
+
+static void
+Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x36;
+}
+
+static void
+Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1000;
+}
+
+static void
+Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x408000;
+}
+
+static void
+Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x90;
+}
+
+static void
+Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf01d;
+}
+
+static void
+Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3400;
+}
+
+static void
+Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3500;
+}
+
+static void
+Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x90000;
+}
+
+static void
+Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x490000;
+}
+
+static void
+Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x34800;
+}
+
+static void
+Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x134800;
+}
+
+static void
+Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x614800;
+}
+
+static void
+Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x34900;
+}
+
+static void
+Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x134900;
+}
+
+static void
+Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x614900;
+}
+
+static void
+Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa;
+}
+
+static void
+Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb;
+}
+
+static void
+Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8c;
+}
+
+static void
+Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xcc;
+}
+
+static void
+Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf06d;
+}
+
+static void
+Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8;
+}
+
+static void
+Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd;
+}
+
+static void
+Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc;
+}
+
+static void
+Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf03d;
+}
+
+static void
+Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf00d;
+}
+
+static void
+Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9;
+}
+
+static void
+Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc002;
+}
+
+static void
+Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd002;
+}
+
+static void
+Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x800000;
+}
+
+static void
+Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc00000;
+}
+
+static void
+Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x900000;
+}
+
+static void
+Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa00000;
+}
+
+static void
+Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb00000;
+}
+
+static void
+Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd00000;
+}
+
+static void
+Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe00000;
+}
+
+static void
+Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf00000;
+}
+
+static void
+Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x100000;
+}
+
+static void
+Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200000;
+}
+
+static void
+Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x300000;
+}
+
+static void
+Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x26;
+}
+
+static void
+Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x66;
+}
+
+static void
+Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe6;
+}
+
+static void
+Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa6;
+}
+
+static void
+Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6007;
+}
+
+static void
+Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe007;
+}
+
+static void
+Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf6;
+}
+
+static void
+Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb6;
+}
+
+static void
+Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1007;
+}
+
+static void
+Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9007;
+}
+
+static void
+Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa007;
+}
+
+static void
+Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2007;
+}
+
+static void
+Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb007;
+}
+
+static void
+Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3007;
+}
+
+static void
+Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8007;
+}
+
+static void
+Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7;
+}
+
+static void
+Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4007;
+}
+
+static void
+Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc007;
+}
+
+static void
+Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5007;
+}
+
+static void
+Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd007;
+}
+
+static void
+Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x16;
+}
+
+static void
+Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x56;
+}
+
+static void
+Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd6;
+}
+
+static void
+Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x96;
+}
+
+static void
+Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5;
+}
+
+static void
+Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc0;
+}
+
+static void
+Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40000;
+}
+
+static void
+Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0;
+}
+
+static void
+Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6;
+}
+
+static void
+Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa0;
+}
+
+static void
+Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1002;
+}
+
+static void
+Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9002;
+}
+
+static void
+Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2002;
+}
+
+static void
+Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1;
+}
+
+static void
+Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2;
+}
+
+static void
+Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8076;
+}
+
+static void
+Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9076;
+}
+
+static void
+Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa076;
+}
+
+static void
+Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa002;
+}
+
+static void
+Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x830000;
+}
+
+static void
+Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x930000;
+}
+
+static void
+Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa30000;
+}
+
+static void
+Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb30000;
+}
+
+static void
+Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x600000;
+}
+
+static void
+Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x600100;
+}
+
+static void
+Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x20f0;
+}
+
+static void
+Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x80;
+}
+
+static void
+Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5100;
+}
+
+static void
+Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5002;
+}
+
+static void
+Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6002;
+}
+
+static void
+Opcode_s32nb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x590000;
+}
+
+static void
+Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4002;
+}
+
+static void
+Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400000;
+}
+
+static void
+Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x401000;
+}
+
+static void
+Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x402000;
+}
+
+static void
+Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x403000;
+}
+
+static void
+Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x404000;
+}
+
+static void
+Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa10000;
+}
+
+static void
+Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x810000;
+}
+
+static void
+Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x910000;
+}
+
+static void
+Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb10000;
+}
+
+static void
+Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x10000;
+}
+
+static void
+Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x210000;
+}
+
+static void
+Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x410000;
+}
+
+static void
+Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x20c0;
+}
+
+static void
+Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x20d0;
+}
+
+static void
+Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2000;
+}
+
+static void
+Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2010;
+}
+
+static void
+Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2020;
+}
+
+static void
+Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2030;
+}
+
+static void
+Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6000;
+}
+
+static void
+Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30100;
+}
+
+static void
+Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x130100;
+}
+
+static void
+Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x610100;
+}
+
+static void
+Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30200;
+}
+
+static void
+Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x130200;
+}
+
+static void
+Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x610200;
+}
+
+static void
+Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30000;
+}
+
+static void
+Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x130000;
+}
+
+static void
+Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x610000;
+}
+
+static void
+Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30300;
+}
+
+static void
+Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x130300;
+}
+
+static void
+Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x610300;
+}
+
+static void
+Opcode_rsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x36100;
+}
+
+static void
+Opcode_wsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x136100;
+}
+
+static void
+Opcode_xsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x616100;
+}
+
+static void
+Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30500;
+}
+
+static void
+Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x130500;
+}
+
+static void
+Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x610500;
+}
+
+static void
+Opcode_rsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b000;
+}
+
+static void
+Opcode_wsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b000;
+}
+
+static void
+Opcode_rsr_configid1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d000;
+}
+
+static void
+Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e600;
+}
+
+static void
+Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e600;
+}
+
+static void
+Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61e600;
+}
+
+static void
+Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b100;
+}
+
+static void
+Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b100;
+}
+
+static void
+Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61b100;
+}
+
+static void
+Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d100;
+}
+
+static void
+Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13d100;
+}
+
+static void
+Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61d100;
+}
+
+static void
+Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b200;
+}
+
+static void
+Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b200;
+}
+
+static void
+Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61b200;
+}
+
+static void
+Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d200;
+}
+
+static void
+Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13d200;
+}
+
+static void
+Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61d200;
+}
+
+static void
+Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b300;
+}
+
+static void
+Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b300;
+}
+
+static void
+Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61b300;
+}
+
+static void
+Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d300;
+}
+
+static void
+Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13d300;
+}
+
+static void
+Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61d300;
+}
+
+static void
+Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b400;
+}
+
+static void
+Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b400;
+}
+
+static void
+Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61b400;
+}
+
+static void
+Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d400;
+}
+
+static void
+Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13d400;
+}
+
+static void
+Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61d400;
+}
+
+static void
+Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b500;
+}
+
+static void
+Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b500;
+}
+
+static void
+Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61b500;
+}
+
+static void
+Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d500;
+}
+
+static void
+Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13d500;
+}
+
+static void
+Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61d500;
+}
+
+static void
+Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b600;
+}
+
+static void
+Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b600;
+}
+
+static void
+Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61b600;
+}
+
+static void
+Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d600;
+}
+
+static void
+Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13d600;
+}
+
+static void
+Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61d600;
+}
+
+static void
+Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b700;
+}
+
+static void
+Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b700;
+}
+
+static void
+Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61b700;
+}
+
+static void
+Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d700;
+}
+
+static void
+Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13d700;
+}
+
+static void
+Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61d700;
+}
+
+static void
+Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c200;
+}
+
+static void
+Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13c200;
+}
+
+static void
+Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61c200;
+}
+
+static void
+Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c300;
+}
+
+static void
+Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13c300;
+}
+
+static void
+Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61c300;
+}
+
+static void
+Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c400;
+}
+
+static void
+Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13c400;
+}
+
+static void
+Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61c400;
+}
+
+static void
+Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c500;
+}
+
+static void
+Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13c500;
+}
+
+static void
+Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61c500;
+}
+
+static void
+Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c600;
+}
+
+static void
+Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13c600;
+}
+
+static void
+Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61c600;
+}
+
+static void
+Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c700;
+}
+
+static void
+Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13c700;
+}
+
+static void
+Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61c700;
+}
+
+static void
+Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3ee00;
+}
+
+static void
+Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13ee00;
+}
+
+static void
+Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61ee00;
+}
+
+static void
+Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c000;
+}
+
+static void
+Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13c000;
+}
+
+static void
+Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61c000;
+}
+
+static void
+Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e800;
+}
+
+static void
+Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e800;
+}
+
+static void
+Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61e800;
+}
+
+static void
+Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3f400;
+}
+
+static void
+Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13f400;
+}
+
+static void
+Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61f400;
+}
+
+static void
+Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3f500;
+}
+
+static void
+Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13f500;
+}
+
+static void
+Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61f500;
+}
+
+static void
+Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3eb00;
+}
+
+static void
+Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e700;
+}
+
+static void
+Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e700;
+}
+
+static void
+Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61e700;
+}
+
+static void
+Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc10000;
+}
+
+static void
+Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd10000;
+}
+
+static void
+Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x820000;
+}
+
+static void
+Opcode_mul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x740004;
+}
+
+static void
+Opcode_mul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x750004;
+}
+
+static void
+Opcode_mul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x760004;
+}
+
+static void
+Opcode_mul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x770004;
+}
+
+static void
+Opcode_umul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x700004;
+}
+
+static void
+Opcode_umul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x710004;
+}
+
+static void
+Opcode_umul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x720004;
+}
+
+static void
+Opcode_umul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x730004;
+}
+
+static void
+Opcode_mul_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x340004;
+}
+
+static void
+Opcode_mul_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x350004;
+}
+
+static void
+Opcode_mul_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x360004;
+}
+
+static void
+Opcode_mul_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x370004;
+}
+
+static void
+Opcode_mul_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x640004;
+}
+
+static void
+Opcode_mul_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x650004;
+}
+
+static void
+Opcode_mul_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x660004;
+}
+
+static void
+Opcode_mul_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x670004;
+}
+
+static void
+Opcode_mul_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x240004;
+}
+
+static void
+Opcode_mul_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x250004;
+}
+
+static void
+Opcode_mul_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x260004;
+}
+
+static void
+Opcode_mul_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x270004;
+}
+
+static void
+Opcode_mula_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x780004;
+}
+
+static void
+Opcode_mula_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x790004;
+}
+
+static void
+Opcode_mula_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7a0004;
+}
+
+static void
+Opcode_mula_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7b0004;
+}
+
+static void
+Opcode_muls_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7c0004;
+}
+
+static void
+Opcode_muls_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7d0004;
+}
+
+static void
+Opcode_muls_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7e0004;
+}
+
+static void
+Opcode_muls_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7f0004;
+}
+
+static void
+Opcode_mula_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x380004;
+}
+
+static void
+Opcode_mula_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x390004;
+}
+
+static void
+Opcode_mula_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3a0004;
+}
+
+static void
+Opcode_mula_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b0004;
+}
+
+static void
+Opcode_muls_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c0004;
+}
+
+static void
+Opcode_muls_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d0004;
+}
+
+static void
+Opcode_muls_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e0004;
+}
+
+static void
+Opcode_muls_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3f0004;
+}
+
+static void
+Opcode_mula_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x680004;
+}
+
+static void
+Opcode_mula_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x690004;
+}
+
+static void
+Opcode_mula_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6a0004;
+}
+
+static void
+Opcode_mula_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6b0004;
+}
+
+static void
+Opcode_muls_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6c0004;
+}
+
+static void
+Opcode_muls_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6d0004;
+}
+
+static void
+Opcode_muls_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6e0004;
+}
+
+static void
+Opcode_muls_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6f0004;
+}
+
+static void
+Opcode_mula_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x280004;
+}
+
+static void
+Opcode_mula_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x290004;
+}
+
+static void
+Opcode_mula_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2a0004;
+}
+
+static void
+Opcode_mula_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2b0004;
+}
+
+static void
+Opcode_muls_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2c0004;
+}
+
+static void
+Opcode_muls_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2d0004;
+}
+
+static void
+Opcode_muls_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2e0004;
+}
+
+static void
+Opcode_muls_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2f0004;
+}
+
+static void
+Opcode_mula_da_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x580004;
+}
+
+static void
+Opcode_mula_da_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x480004;
+}
+
+static void
+Opcode_mula_da_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x590004;
+}
+
+static void
+Opcode_mula_da_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x490004;
+}
+
+static void
+Opcode_mula_da_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5a0004;
+}
+
+static void
+Opcode_mula_da_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4a0004;
+}
+
+static void
+Opcode_mula_da_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5b0004;
+}
+
+static void
+Opcode_mula_da_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4b0004;
+}
+
+static void
+Opcode_mula_dd_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x180004;
+}
+
+static void
+Opcode_mula_dd_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x80004;
+}
+
+static void
+Opcode_mula_dd_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x190004;
+}
+
+static void
+Opcode_mula_dd_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x90004;
+}
+
+static void
+Opcode_mula_dd_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1a0004;
+}
+
+static void
+Opcode_mula_dd_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa0004;
+}
+
+static void
+Opcode_mula_dd_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1b0004;
+}
+
+static void
+Opcode_mula_dd_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb0004;
+}
+
+static void
+Opcode_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x900004;
+}
+
+static void
+Opcode_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x800004;
+}
+
+static void
+Opcode_rsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x32000;
+}
+
+static void
+Opcode_wsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x132000;
+}
+
+static void
+Opcode_xsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x612000;
+}
+
+static void
+Opcode_rsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x32100;
+}
+
+static void
+Opcode_wsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x132100;
+}
+
+static void
+Opcode_xsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x612100;
+}
+
+static void
+Opcode_rsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x32200;
+}
+
+static void
+Opcode_wsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x132200;
+}
+
+static void
+Opcode_xsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x612200;
+}
+
+static void
+Opcode_rsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x32300;
+}
+
+static void
+Opcode_wsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x132300;
+}
+
+static void
+Opcode_xsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x612300;
+}
+
+static void
+Opcode_rsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x31000;
+}
+
+static void
+Opcode_wsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x131000;
+}
+
+static void
+Opcode_xsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x611000;
+}
+
+static void
+Opcode_rsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x31100;
+}
+
+static void
+Opcode_wsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x131100;
+}
+
+static void
+Opcode_xsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x611100;
+}
+
+static void
+Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3010;
+}
+
+static void
+Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7000;
+}
+
+static void
+Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e200;
+}
+
+static void
+Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e200;
+}
+
+static void
+Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e300;
+}
+
+static void
+Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e400;
+}
+
+static void
+Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e400;
+}
+
+static void
+Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61e400;
+}
+
+static void
+Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000;
+}
+
+static void
+Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf02d;
+}
+
+static void
+Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x39000;
+}
+
+static void
+Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x139000;
+}
+
+static void
+Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x619000;
+}
+
+static void
+Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3a000;
+}
+
+static void
+Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13a000;
+}
+
+static void
+Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61a000;
+}
+
+static void
+Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x39100;
+}
+
+static void
+Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x139100;
+}
+
+static void
+Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x619100;
+}
+
+static void
+Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3a100;
+}
+
+static void
+Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13a100;
+}
+
+static void
+Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61a100;
+}
+
+static void
+Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x38000;
+}
+
+static void
+Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x138000;
+}
+
+static void
+Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x618000;
+}
+
+static void
+Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x38100;
+}
+
+static void
+Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x138100;
+}
+
+static void
+Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x618100;
+}
+
+static void
+Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x36000;
+}
+
+static void
+Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x136000;
+}
+
+static void
+Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x616000;
+}
+
+static void
+Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e900;
+}
+
+static void
+Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e900;
+}
+
+static void
+Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61e900;
+}
+
+static void
+Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3ec00;
+}
+
+static void
+Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13ec00;
+}
+
+static void
+Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61ec00;
+}
+
+static void
+Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3ed00;
+}
+
+static void
+Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13ed00;
+}
+
+static void
+Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61ed00;
+}
+
+static void
+Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x36800;
+}
+
+static void
+Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x136800;
+}
+
+static void
+Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x616800;
+}
+
+static void
+Opcode_lddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x70e0;
+}
+
+static void
+Opcode_sddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x70f0;
+}
+
+static void
+Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf1e000;
+}
+
+static void
+Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf1e010;
+}
+
+static void
+Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x135900;
+}
+
+static void
+Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3ea00;
+}
+
+static void
+Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13ea00;
+}
+
+static void
+Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61ea00;
+}
+
+static void
+Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3f000;
+}
+
+static void
+Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13f000;
+}
+
+static void
+Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61f000;
+}
+
+static void
+Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3f100;
+}
+
+static void
+Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13f100;
+}
+
+static void
+Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61f100;
+}
+
+static void
+Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3f200;
+}
+
+static void
+Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13f200;
+}
+
+static void
+Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61f200;
+}
+
+static void
+Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x70c2;
+}
+
+static void
+Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x70e2;
+}
+
+static void
+Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x70d2;
+}
+
+static void
+Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x270d2;
+}
+
+static void
+Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x370d2;
+}
+
+static void
+Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x70f2;
+}
+
+static void
+Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf10000;
+}
+
+static void
+Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf12000;
+}
+
+static void
+Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf11000;
+}
+
+static void
+Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf13000;
+}
+
+static void
+Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7042;
+}
+
+static void
+Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7052;
+}
+
+static void
+Opcode_diwbui_p_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf7082;
+}
+
+static void
+Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x47082;
+}
+
+static void
+Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x57082;
+}
+
+static void
+Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7062;
+}
+
+static void
+Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7072;
+}
+
+static void
+Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7002;
+}
+
+static void
+Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7012;
+}
+
+static void
+Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7022;
+}
+
+static void
+Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7032;
+}
+
+static void
+Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7082;
+}
+
+static void
+Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x27082;
+}
+
+static void
+Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x37082;
+}
+
+static void
+Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf19000;
+}
+
+static void
+Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf18000;
+}
+
+static void
+Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50c000;
+}
+
+static void
+Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50d000;
+}
+
+static void
+Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50b000;
+}
+
+static void
+Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50f000;
+}
+
+static void
+Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50e000;
+}
+
+static void
+Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x504000;
+}
+
+static void
+Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x505000;
+}
+
+static void
+Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x503000;
+}
+
+static void
+Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x507000;
+}
+
+static void
+Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x506000;
+}
+
+static void
+Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x330000;
+}
+
+static void
+Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x430000;
+}
+
+static void
+Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x530000;
+}
+
+static void
+Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x630000;
+}
+
+static void
+Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x730000;
+}
+
+static void
+Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40e000;
+}
+
+static void
+Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40f000;
+}
+
+static void
+Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x230000;
+}
+
+static void
+Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb002;
+}
+
+static void
+Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf002;
+}
+
+static void
+Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe002;
+}
+
+static void
+Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30c00;
+}
+
+static void
+Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x130c00;
+}
+
+static void
+Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x610c00;
+}
+
+static void
+Opcode_rsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x36300;
+}
+
+static void
+Opcode_wsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x136300;
+}
+
+static void
+Opcode_xsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x616300;
+}
+
+static void
+Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc20000;
+}
+
+static void
+Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd20000;
+}
+
+static void
+Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe20000;
+}
+
+static void
+Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf20000;
+}
+
+static void
+Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x406000;
+}
+
+static void
+Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x407000;
+}
+
+static void
+Opcode_rur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe30e60;
+}
+
+static void
+Opcode_wur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf3e600;
+}
+
+static void
+Opcode_read_impwire_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe0000;
+}
+
+static void
+Opcode_setb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe1000;
+}
+
+static void
+Opcode_clrb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe1200;
+}
+
+static void
+Opcode_wrmsk_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe2000;
+}
+
+static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = {
+ Opcode_excw_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = {
+ Opcode_rfe_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = {
+ Opcode_rfde_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = {
+ Opcode_syscall_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = {
+ Opcode_call12_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = {
+ Opcode_call8_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = {
+ Opcode_call4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = {
+ Opcode_callx12_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = {
+ Opcode_callx8_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = {
+ Opcode_callx4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = {
+ Opcode_entry_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = {
+ Opcode_movsp_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = {
+ Opcode_rotw_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = {
+ Opcode_retw_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = {
+ 0, 0, Opcode_retw_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = {
+ Opcode_rfwo_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = {
+ Opcode_rfwu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = {
+ Opcode_l32e_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = {
+ Opcode_s32e_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = {
+ Opcode_rsr_windowbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = {
+ Opcode_wsr_windowbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = {
+ Opcode_xsr_windowbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = {
+ Opcode_rsr_windowstart_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = {
+ Opcode_wsr_windowstart_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = {
+ Opcode_xsr_windowstart_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = {
+ 0, Opcode_add_n_Slot_inst16a_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = {
+ 0, Opcode_addi_n_Slot_inst16a_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = {
+ 0, 0, Opcode_beqz_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = {
+ 0, 0, Opcode_bnez_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = {
+ 0, 0, Opcode_ill_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = {
+ 0, Opcode_l32i_n_Slot_inst16a_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = {
+ 0, 0, Opcode_mov_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = {
+ 0, 0, Opcode_movi_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = {
+ 0, 0, Opcode_nop_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = {
+ 0, 0, Opcode_ret_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = {
+ 0, Opcode_s32i_n_Slot_inst16a_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = {
+ Opcode_addi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = {
+ Opcode_addmi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = {
+ Opcode_add_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = {
+ Opcode_sub_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = {
+ Opcode_addx2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = {
+ Opcode_addx4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = {
+ Opcode_addx8_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = {
+ Opcode_subx2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = {
+ Opcode_subx4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = {
+ Opcode_subx8_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = {
+ Opcode_and_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = {
+ Opcode_or_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = {
+ Opcode_xor_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = {
+ Opcode_beqi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = {
+ Opcode_bnei_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = {
+ Opcode_bgei_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = {
+ Opcode_blti_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = {
+ Opcode_bbci_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = {
+ Opcode_bbsi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = {
+ Opcode_bgeui_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = {
+ Opcode_bltui_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = {
+ Opcode_beq_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = {
+ Opcode_bne_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = {
+ Opcode_bge_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = {
+ Opcode_blt_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = {
+ Opcode_bgeu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = {
+ Opcode_bltu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = {
+ Opcode_bany_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = {
+ Opcode_bnone_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = {
+ Opcode_ball_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = {
+ Opcode_bnall_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = {
+ Opcode_bbc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = {
+ Opcode_bbs_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = {
+ Opcode_beqz_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = {
+ Opcode_bnez_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = {
+ Opcode_bgez_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = {
+ Opcode_bltz_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = {
+ Opcode_call0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = {
+ Opcode_callx0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = {
+ Opcode_extui_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = {
+ Opcode_ill_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = {
+ Opcode_j_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = {
+ Opcode_jx_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = {
+ Opcode_l16ui_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = {
+ Opcode_l16si_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = {
+ Opcode_l32i_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = {
+ Opcode_l32r_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = {
+ Opcode_l8ui_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = {
+ Opcode_loop_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = {
+ Opcode_loopnez_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = {
+ Opcode_loopgtz_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = {
+ Opcode_movi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = {
+ Opcode_moveqz_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = {
+ Opcode_movnez_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = {
+ Opcode_movltz_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = {
+ Opcode_movgez_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = {
+ Opcode_neg_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = {
+ Opcode_abs_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = {
+ Opcode_nop_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = {
+ Opcode_ret_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = {
+ Opcode_simcall_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = {
+ Opcode_s16i_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = {
+ Opcode_s32i_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s32nb_encode_fns[] = {
+ Opcode_s32nb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = {
+ Opcode_s8i_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = {
+ Opcode_ssr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = {
+ Opcode_ssl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = {
+ Opcode_ssa8l_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = {
+ Opcode_ssa8b_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = {
+ Opcode_ssai_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = {
+ Opcode_sll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = {
+ Opcode_src_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = {
+ Opcode_srl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = {
+ Opcode_sra_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = {
+ Opcode_slli_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = {
+ Opcode_srai_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = {
+ Opcode_srli_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = {
+ Opcode_memw_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = {
+ Opcode_extw_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = {
+ Opcode_isync_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = {
+ Opcode_rsync_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = {
+ Opcode_esync_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = {
+ Opcode_dsync_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = {
+ Opcode_rsil_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = {
+ Opcode_rsr_lend_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = {
+ Opcode_wsr_lend_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = {
+ Opcode_xsr_lend_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = {
+ Opcode_rsr_lcount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = {
+ Opcode_wsr_lcount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = {
+ Opcode_xsr_lcount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = {
+ Opcode_rsr_lbeg_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = {
+ Opcode_wsr_lbeg_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = {
+ Opcode_xsr_lbeg_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = {
+ Opcode_rsr_sar_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = {
+ Opcode_wsr_sar_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = {
+ Opcode_xsr_sar_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_memctl_encode_fns[] = {
+ Opcode_rsr_memctl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_memctl_encode_fns[] = {
+ Opcode_wsr_memctl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_memctl_encode_fns[] = {
+ Opcode_xsr_memctl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = {
+ Opcode_rsr_litbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = {
+ Opcode_wsr_litbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = {
+ Opcode_xsr_litbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_configid0_encode_fns[] = {
+ Opcode_rsr_configid0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_configid0_encode_fns[] = {
+ Opcode_wsr_configid0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_configid1_encode_fns[] = {
+ Opcode_rsr_configid1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = {
+ Opcode_rsr_ps_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = {
+ Opcode_wsr_ps_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = {
+ Opcode_xsr_ps_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = {
+ Opcode_rsr_epc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = {
+ Opcode_wsr_epc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = {
+ Opcode_xsr_epc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = {
+ Opcode_rsr_excsave1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = {
+ Opcode_wsr_excsave1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = {
+ Opcode_xsr_excsave1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = {
+ Opcode_rsr_epc2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = {
+ Opcode_wsr_epc2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = {
+ Opcode_xsr_epc2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = {
+ Opcode_rsr_excsave2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = {
+ Opcode_wsr_excsave2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = {
+ Opcode_xsr_excsave2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = {
+ Opcode_rsr_epc3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = {
+ Opcode_wsr_epc3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = {
+ Opcode_xsr_epc3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = {
+ Opcode_rsr_excsave3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = {
+ Opcode_wsr_excsave3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = {
+ Opcode_xsr_excsave3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = {
+ Opcode_rsr_epc4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = {
+ Opcode_wsr_epc4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = {
+ Opcode_xsr_epc4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = {
+ Opcode_rsr_excsave4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = {
+ Opcode_wsr_excsave4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = {
+ Opcode_xsr_excsave4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = {
+ Opcode_rsr_epc5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = {
+ Opcode_wsr_epc5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = {
+ Opcode_xsr_epc5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = {
+ Opcode_rsr_excsave5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = {
+ Opcode_wsr_excsave5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = {
+ Opcode_xsr_excsave5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = {
+ Opcode_rsr_epc6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = {
+ Opcode_wsr_epc6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = {
+ Opcode_xsr_epc6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = {
+ Opcode_rsr_excsave6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = {
+ Opcode_wsr_excsave6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = {
+ Opcode_xsr_excsave6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = {
+ Opcode_rsr_epc7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = {
+ Opcode_wsr_epc7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = {
+ Opcode_xsr_epc7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = {
+ Opcode_rsr_excsave7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = {
+ Opcode_wsr_excsave7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = {
+ Opcode_xsr_excsave7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = {
+ Opcode_rsr_eps2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = {
+ Opcode_wsr_eps2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = {
+ Opcode_xsr_eps2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = {
+ Opcode_rsr_eps3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = {
+ Opcode_wsr_eps3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = {
+ Opcode_xsr_eps3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = {
+ Opcode_rsr_eps4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = {
+ Opcode_wsr_eps4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = {
+ Opcode_xsr_eps4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = {
+ Opcode_rsr_eps5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = {
+ Opcode_wsr_eps5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = {
+ Opcode_xsr_eps5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = {
+ Opcode_rsr_eps6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = {
+ Opcode_wsr_eps6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = {
+ Opcode_xsr_eps6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = {
+ Opcode_rsr_eps7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = {
+ Opcode_wsr_eps7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = {
+ Opcode_xsr_eps7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = {
+ Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = {
+ Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = {
+ Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = {
+ Opcode_rsr_depc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = {
+ Opcode_wsr_depc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = {
+ Opcode_xsr_depc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = {
+ Opcode_rsr_exccause_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = {
+ Opcode_wsr_exccause_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = {
+ Opcode_xsr_exccause_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = {
+ Opcode_rsr_misc0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = {
+ Opcode_wsr_misc0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = {
+ Opcode_xsr_misc0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = {
+ Opcode_rsr_misc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = {
+ Opcode_wsr_misc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = {
+ Opcode_xsr_misc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = {
+ Opcode_rsr_prid_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = {
+ Opcode_rsr_vecbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = {
+ Opcode_wsr_vecbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = {
+ Opcode_xsr_vecbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = {
+ Opcode_mul16u_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = {
+ Opcode_mul16s_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = {
+ Opcode_mull_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_aa_ll_encode_fns[] = {
+ Opcode_mul_aa_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_aa_hl_encode_fns[] = {
+ Opcode_mul_aa_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_aa_lh_encode_fns[] = {
+ Opcode_mul_aa_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_aa_hh_encode_fns[] = {
+ Opcode_mul_aa_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_umul_aa_ll_encode_fns[] = {
+ Opcode_umul_aa_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_umul_aa_hl_encode_fns[] = {
+ Opcode_umul_aa_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_umul_aa_lh_encode_fns[] = {
+ Opcode_umul_aa_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_umul_aa_hh_encode_fns[] = {
+ Opcode_umul_aa_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_ad_ll_encode_fns[] = {
+ Opcode_mul_ad_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_ad_hl_encode_fns[] = {
+ Opcode_mul_ad_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_ad_lh_encode_fns[] = {
+ Opcode_mul_ad_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_ad_hh_encode_fns[] = {
+ Opcode_mul_ad_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_da_ll_encode_fns[] = {
+ Opcode_mul_da_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_da_hl_encode_fns[] = {
+ Opcode_mul_da_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_da_lh_encode_fns[] = {
+ Opcode_mul_da_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_da_hh_encode_fns[] = {
+ Opcode_mul_da_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_dd_ll_encode_fns[] = {
+ Opcode_mul_dd_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_dd_hl_encode_fns[] = {
+ Opcode_mul_dd_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_dd_lh_encode_fns[] = {
+ Opcode_mul_dd_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_dd_hh_encode_fns[] = {
+ Opcode_mul_dd_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_aa_ll_encode_fns[] = {
+ Opcode_mula_aa_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_aa_hl_encode_fns[] = {
+ Opcode_mula_aa_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_aa_lh_encode_fns[] = {
+ Opcode_mula_aa_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_aa_hh_encode_fns[] = {
+ Opcode_mula_aa_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_aa_ll_encode_fns[] = {
+ Opcode_muls_aa_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_aa_hl_encode_fns[] = {
+ Opcode_muls_aa_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_aa_lh_encode_fns[] = {
+ Opcode_muls_aa_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_aa_hh_encode_fns[] = {
+ Opcode_muls_aa_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_ad_ll_encode_fns[] = {
+ Opcode_mula_ad_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_ad_hl_encode_fns[] = {
+ Opcode_mula_ad_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_ad_lh_encode_fns[] = {
+ Opcode_mula_ad_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_ad_hh_encode_fns[] = {
+ Opcode_mula_ad_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_ad_ll_encode_fns[] = {
+ Opcode_muls_ad_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_ad_hl_encode_fns[] = {
+ Opcode_muls_ad_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_ad_lh_encode_fns[] = {
+ Opcode_muls_ad_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_ad_hh_encode_fns[] = {
+ Opcode_muls_ad_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_ll_encode_fns[] = {
+ Opcode_mula_da_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_hl_encode_fns[] = {
+ Opcode_mula_da_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_lh_encode_fns[] = {
+ Opcode_mula_da_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_hh_encode_fns[] = {
+ Opcode_mula_da_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_da_ll_encode_fns[] = {
+ Opcode_muls_da_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_da_hl_encode_fns[] = {
+ Opcode_muls_da_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_da_lh_encode_fns[] = {
+ Opcode_muls_da_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_da_hh_encode_fns[] = {
+ Opcode_muls_da_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_ll_encode_fns[] = {
+ Opcode_mula_dd_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_hl_encode_fns[] = {
+ Opcode_mula_dd_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_lh_encode_fns[] = {
+ Opcode_mula_dd_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_hh_encode_fns[] = {
+ Opcode_mula_dd_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_dd_ll_encode_fns[] = {
+ Opcode_muls_dd_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_dd_hl_encode_fns[] = {
+ Opcode_muls_dd_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_dd_lh_encode_fns[] = {
+ Opcode_muls_dd_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_dd_hh_encode_fns[] = {
+ Opcode_muls_dd_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_ll_lddec_encode_fns[] = {
+ Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_ll_ldinc_encode_fns[] = {
+ Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_hl_lddec_encode_fns[] = {
+ Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_hl_ldinc_encode_fns[] = {
+ Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_lh_lddec_encode_fns[] = {
+ Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_lh_ldinc_encode_fns[] = {
+ Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_hh_lddec_encode_fns[] = {
+ Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_hh_ldinc_encode_fns[] = {
+ Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_ll_lddec_encode_fns[] = {
+ Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_ll_ldinc_encode_fns[] = {
+ Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_hl_lddec_encode_fns[] = {
+ Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_hl_ldinc_encode_fns[] = {
+ Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_lh_lddec_encode_fns[] = {
+ Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_lh_ldinc_encode_fns[] = {
+ Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_hh_lddec_encode_fns[] = {
+ Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_hh_ldinc_encode_fns[] = {
+ Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_lddec_encode_fns[] = {
+ Opcode_lddec_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ldinc_encode_fns[] = {
+ Opcode_ldinc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_m0_encode_fns[] = {
+ Opcode_rsr_m0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_m0_encode_fns[] = {
+ Opcode_wsr_m0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_m0_encode_fns[] = {
+ Opcode_xsr_m0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_m1_encode_fns[] = {
+ Opcode_rsr_m1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_m1_encode_fns[] = {
+ Opcode_wsr_m1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_m1_encode_fns[] = {
+ Opcode_xsr_m1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_m2_encode_fns[] = {
+ Opcode_rsr_m2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_m2_encode_fns[] = {
+ Opcode_wsr_m2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_m2_encode_fns[] = {
+ Opcode_xsr_m2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_m3_encode_fns[] = {
+ Opcode_rsr_m3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_m3_encode_fns[] = {
+ Opcode_wsr_m3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_m3_encode_fns[] = {
+ Opcode_xsr_m3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = {
+ Opcode_rsr_acclo_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = {
+ Opcode_wsr_acclo_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = {
+ Opcode_xsr_acclo_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = {
+ Opcode_rsr_acchi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = {
+ Opcode_wsr_acchi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = {
+ Opcode_xsr_acchi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = {
+ Opcode_rfi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = {
+ Opcode_waiti_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = {
+ Opcode_rsr_interrupt_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = {
+ Opcode_wsr_intset_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = {
+ Opcode_wsr_intclear_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = {
+ Opcode_rsr_intenable_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = {
+ Opcode_wsr_intenable_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = {
+ Opcode_xsr_intenable_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = {
+ Opcode_break_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = {
+ 0, 0, Opcode_break_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = {
+ Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = {
+ Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = {
+ Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = {
+ Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = {
+ Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = {
+ Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = {
+ Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = {
+ Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = {
+ Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = {
+ Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = {
+ Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = {
+ Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = {
+ Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = {
+ Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = {
+ Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = {
+ Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = {
+ Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = {
+ Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = {
+ Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = {
+ Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = {
+ Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = {
+ Opcode_rsr_debugcause_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = {
+ Opcode_wsr_debugcause_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = {
+ Opcode_xsr_debugcause_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = {
+ Opcode_rsr_icount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = {
+ Opcode_wsr_icount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = {
+ Opcode_xsr_icount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = {
+ Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = {
+ Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = {
+ Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = {
+ Opcode_rsr_ddr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = {
+ Opcode_wsr_ddr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = {
+ Opcode_xsr_ddr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_lddr32_p_encode_fns[] = {
+ Opcode_lddr32_p_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sddr32_p_encode_fns[] = {
+ Opcode_sddr32_p_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = {
+ Opcode_rfdo_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = {
+ Opcode_rfdd_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = {
+ Opcode_wsr_mmid_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = {
+ Opcode_rsr_ccount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = {
+ Opcode_wsr_ccount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = {
+ Opcode_xsr_ccount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = {
+ Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = {
+ Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = {
+ Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = {
+ Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = {
+ Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = {
+ Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = {
+ Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = {
+ Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = {
+ Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = {
+ Opcode_ipf_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = {
+ Opcode_ihi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = {
+ Opcode_ipfl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = {
+ Opcode_ihu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = {
+ Opcode_iiu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = {
+ Opcode_iii_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = {
+ Opcode_lict_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = {
+ Opcode_licw_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = {
+ Opcode_sict_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = {
+ Opcode_sicw_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = {
+ Opcode_dhwb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = {
+ Opcode_dhwbi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_diwbui_p_encode_fns[] = {
+ Opcode_diwbui_p_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = {
+ Opcode_diwb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = {
+ Opcode_diwbi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = {
+ Opcode_dhi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = {
+ Opcode_dii_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = {
+ Opcode_dpfr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = {
+ Opcode_dpfw_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = {
+ Opcode_dpfro_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = {
+ Opcode_dpfwo_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = {
+ Opcode_dpfl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = {
+ Opcode_dhu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = {
+ Opcode_diu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = {
+ Opcode_sdct_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = {
+ Opcode_ldct_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = {
+ Opcode_idtlb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = {
+ Opcode_pdtlb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = {
+ Opcode_rdtlb0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = {
+ Opcode_rdtlb1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = {
+ Opcode_wdtlb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = {
+ Opcode_iitlb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = {
+ Opcode_pitlb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = {
+ Opcode_ritlb0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = {
+ Opcode_ritlb1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = {
+ Opcode_witlb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = {
+ Opcode_clamps_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = {
+ Opcode_min_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = {
+ Opcode_max_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = {
+ Opcode_minu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = {
+ Opcode_maxu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = {
+ Opcode_nsa_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = {
+ Opcode_nsau_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = {
+ Opcode_sext_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = {
+ Opcode_l32ai_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = {
+ Opcode_s32ri_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = {
+ Opcode_s32c1i_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = {
+ Opcode_rsr_scompare1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = {
+ Opcode_wsr_scompare1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = {
+ Opcode_xsr_scompare1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = {
+ Opcode_rsr_atomctl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = {
+ Opcode_wsr_atomctl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = {
+ Opcode_xsr_atomctl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = {
+ Opcode_quou_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = {
+ Opcode_quos_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = {
+ Opcode_remu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = {
+ Opcode_rems_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = {
+ Opcode_rer_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = {
+ Opcode_wer_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rur_expstate_encode_fns[] = {
+ Opcode_rur_expstate_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wur_expstate_encode_fns[] = {
+ Opcode_wur_expstate_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_read_impwire_encode_fns[] = {
+ Opcode_read_impwire_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_setb_expstate_encode_fns[] = {
+ Opcode_setb_expstate_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_clrb_expstate_encode_fns[] = {
+ Opcode_clrb_expstate_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wrmsk_expstate_encode_fns[] = {
+ Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0
+};
+
+
+
+
+
+/* Opcode table. */
+
+static xtensa_opcode_internal opcodes[] = {
+ { "excw", ICLASS_xt_iclass_excw,
+ 0,
+ Opcode_excw_encode_fns, 0, 0 },
+ { "rfe", ICLASS_xt_iclass_rfe,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfe_encode_fns, 0, 0 },
+ { "rfde", ICLASS_xt_iclass_rfde,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfde_encode_fns, 0, 0 },
+ { "syscall", ICLASS_xt_iclass_syscall,
+ 0,
+ Opcode_syscall_encode_fns, 0, 0 },
+ { "call12", ICLASS_xt_iclass_call12,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_call12_encode_fns, 0, 0 },
+ { "call8", ICLASS_xt_iclass_call8,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_call8_encode_fns, 0, 0 },
+ { "call4", ICLASS_xt_iclass_call4,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_call4_encode_fns, 0, 0 },
+ { "callx12", ICLASS_xt_iclass_callx12,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_callx12_encode_fns, 0, 0 },
+ { "callx8", ICLASS_xt_iclass_callx8,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_callx8_encode_fns, 0, 0 },
+ { "callx4", ICLASS_xt_iclass_callx4,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_callx4_encode_fns, 0, 0 },
+ { "entry", ICLASS_xt_iclass_entry,
+ 0,
+ Opcode_entry_encode_fns, 0, 0 },
+ { "movsp", ICLASS_xt_iclass_movsp,
+ 0,
+ Opcode_movsp_encode_fns, 0, 0 },
+ { "rotw", ICLASS_xt_iclass_rotw,
+ 0,
+ Opcode_rotw_encode_fns, 0, 0 },
+ { "retw", ICLASS_xt_iclass_retw,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_retw_encode_fns, 0, 0 },
+ { "retw.n", ICLASS_xt_iclass_retw,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_retw_n_encode_fns, 0, 0 },
+ { "rfwo", ICLASS_xt_iclass_rfwou,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfwo_encode_fns, 0, 0 },
+ { "rfwu", ICLASS_xt_iclass_rfwou,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfwu_encode_fns, 0, 0 },
+ { "l32e", ICLASS_xt_iclass_l32e,
+ 0,
+ Opcode_l32e_encode_fns, 0, 0 },
+ { "s32e", ICLASS_xt_iclass_s32e,
+ 0,
+ Opcode_s32e_encode_fns, 0, 0 },
+ { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase,
+ 0,
+ Opcode_rsr_windowbase_encode_fns, 0, 0 },
+ { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase,
+ 0,
+ Opcode_wsr_windowbase_encode_fns, 0, 0 },
+ { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase,
+ 0,
+ Opcode_xsr_windowbase_encode_fns, 0, 0 },
+ { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart,
+ 0,
+ Opcode_rsr_windowstart_encode_fns, 0, 0 },
+ { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart,
+ 0,
+ Opcode_wsr_windowstart_encode_fns, 0, 0 },
+ { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart,
+ 0,
+ Opcode_xsr_windowstart_encode_fns, 0, 0 },
+ { "add.n", ICLASS_xt_iclass_add_n,
+ 0,
+ Opcode_add_n_encode_fns, 0, 0 },
+ { "addi.n", ICLASS_xt_iclass_addi_n,
+ 0,
+ Opcode_addi_n_encode_fns, 0, 0 },
+ { "beqz.n", ICLASS_xt_iclass_bz6,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_beqz_n_encode_fns, 0, 0 },
+ { "bnez.n", ICLASS_xt_iclass_bz6,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bnez_n_encode_fns, 0, 0 },
+ { "ill.n", ICLASS_xt_iclass_ill_n,
+ 0,
+ Opcode_ill_n_encode_fns, 0, 0 },
+ { "l32i.n", ICLASS_xt_iclass_loadi4,
+ 0,
+ Opcode_l32i_n_encode_fns, 0, 0 },
+ { "mov.n", ICLASS_xt_iclass_mov_n,
+ 0,
+ Opcode_mov_n_encode_fns, 0, 0 },
+ { "movi.n", ICLASS_xt_iclass_movi_n,
+ 0,
+ Opcode_movi_n_encode_fns, 0, 0 },
+ { "nop.n", ICLASS_xt_iclass_nopn,
+ 0,
+ Opcode_nop_n_encode_fns, 0, 0 },
+ { "ret.n", ICLASS_xt_iclass_retn,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_ret_n_encode_fns, 0, 0 },
+ { "s32i.n", ICLASS_xt_iclass_storei4,
+ 0,
+ Opcode_s32i_n_encode_fns, 0, 0 },
+ { "addi", ICLASS_xt_iclass_addi,
+ 0,
+ Opcode_addi_encode_fns, 0, 0 },
+ { "addmi", ICLASS_xt_iclass_addmi,
+ 0,
+ Opcode_addmi_encode_fns, 0, 0 },
+ { "add", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_add_encode_fns, 0, 0 },
+ { "sub", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_sub_encode_fns, 0, 0 },
+ { "addx2", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_addx2_encode_fns, 0, 0 },
+ { "addx4", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_addx4_encode_fns, 0, 0 },
+ { "addx8", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_addx8_encode_fns, 0, 0 },
+ { "subx2", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_subx2_encode_fns, 0, 0 },
+ { "subx4", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_subx4_encode_fns, 0, 0 },
+ { "subx8", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_subx8_encode_fns, 0, 0 },
+ { "and", ICLASS_xt_iclass_bit,
+ 0,
+ Opcode_and_encode_fns, 0, 0 },
+ { "or", ICLASS_xt_iclass_bit,
+ 0,
+ Opcode_or_encode_fns, 0, 0 },
+ { "xor", ICLASS_xt_iclass_bit,
+ 0,
+ Opcode_xor_encode_fns, 0, 0 },
+ { "beqi", ICLASS_xt_iclass_bsi8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_beqi_encode_fns, 0, 0 },
+ { "bnei", ICLASS_xt_iclass_bsi8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bnei_encode_fns, 0, 0 },
+ { "bgei", ICLASS_xt_iclass_bsi8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bgei_encode_fns, 0, 0 },
+ { "blti", ICLASS_xt_iclass_bsi8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_blti_encode_fns, 0, 0 },
+ { "bbci", ICLASS_xt_iclass_bsi8b,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bbci_encode_fns, 0, 0 },
+ { "bbsi", ICLASS_xt_iclass_bsi8b,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bbsi_encode_fns, 0, 0 },
+ { "bgeui", ICLASS_xt_iclass_bsi8u,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bgeui_encode_fns, 0, 0 },
+ { "bltui", ICLASS_xt_iclass_bsi8u,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bltui_encode_fns, 0, 0 },
+ { "beq", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_beq_encode_fns, 0, 0 },
+ { "bne", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bne_encode_fns, 0, 0 },
+ { "bge", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bge_encode_fns, 0, 0 },
+ { "blt", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_blt_encode_fns, 0, 0 },
+ { "bgeu", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bgeu_encode_fns, 0, 0 },
+ { "bltu", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bltu_encode_fns, 0, 0 },
+ { "bany", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bany_encode_fns, 0, 0 },
+ { "bnone", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bnone_encode_fns, 0, 0 },
+ { "ball", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_ball_encode_fns, 0, 0 },
+ { "bnall", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bnall_encode_fns, 0, 0 },
+ { "bbc", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bbc_encode_fns, 0, 0 },
+ { "bbs", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bbs_encode_fns, 0, 0 },
+ { "beqz", ICLASS_xt_iclass_bsz12,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_beqz_encode_fns, 0, 0 },
+ { "bnez", ICLASS_xt_iclass_bsz12,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bnez_encode_fns, 0, 0 },
+ { "bgez", ICLASS_xt_iclass_bsz12,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bgez_encode_fns, 0, 0 },
+ { "bltz", ICLASS_xt_iclass_bsz12,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bltz_encode_fns, 0, 0 },
+ { "call0", ICLASS_xt_iclass_call0,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_call0_encode_fns, 0, 0 },
+ { "callx0", ICLASS_xt_iclass_callx0,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_callx0_encode_fns, 0, 0 },
+ { "extui", ICLASS_xt_iclass_exti,
+ 0,
+ Opcode_extui_encode_fns, 0, 0 },
+ { "ill", ICLASS_xt_iclass_ill,
+ 0,
+ Opcode_ill_encode_fns, 0, 0 },
+ { "j", ICLASS_xt_iclass_jump,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_j_encode_fns, 0, 0 },
+ { "jx", ICLASS_xt_iclass_jumpx,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_jx_encode_fns, 0, 0 },
+ { "l16ui", ICLASS_xt_iclass_l16ui,
+ 0,
+ Opcode_l16ui_encode_fns, 0, 0 },
+ { "l16si", ICLASS_xt_iclass_l16si,
+ 0,
+ Opcode_l16si_encode_fns, 0, 0 },
+ { "l32i", ICLASS_xt_iclass_l32i,
+ 0,
+ Opcode_l32i_encode_fns, 0, 0 },
+ { "l32r", ICLASS_xt_iclass_l32r,
+ 0,
+ Opcode_l32r_encode_fns, 0, 0 },
+ { "l8ui", ICLASS_xt_iclass_l8i,
+ 0,
+ Opcode_l8ui_encode_fns, 0, 0 },
+ { "loop", ICLASS_xt_iclass_loop,
+ XTENSA_OPCODE_IS_LOOP,
+ Opcode_loop_encode_fns, 0, 0 },
+ { "loopnez", ICLASS_xt_iclass_loopz,
+ XTENSA_OPCODE_IS_LOOP,
+ Opcode_loopnez_encode_fns, 0, 0 },
+ { "loopgtz", ICLASS_xt_iclass_loopz,
+ XTENSA_OPCODE_IS_LOOP,
+ Opcode_loopgtz_encode_fns, 0, 0 },
+ { "movi", ICLASS_xt_iclass_movi,
+ 0,
+ Opcode_movi_encode_fns, 0, 0 },
+ { "moveqz", ICLASS_xt_iclass_movz,
+ 0,
+ Opcode_moveqz_encode_fns, 0, 0 },
+ { "movnez", ICLASS_xt_iclass_movz,
+ 0,
+ Opcode_movnez_encode_fns, 0, 0 },
+ { "movltz", ICLASS_xt_iclass_movz,
+ 0,
+ Opcode_movltz_encode_fns, 0, 0 },
+ { "movgez", ICLASS_xt_iclass_movz,
+ 0,
+ Opcode_movgez_encode_fns, 0, 0 },
+ { "neg", ICLASS_xt_iclass_neg,
+ 0,
+ Opcode_neg_encode_fns, 0, 0 },
+ { "abs", ICLASS_xt_iclass_neg,
+ 0,
+ Opcode_abs_encode_fns, 0, 0 },
+ { "nop", ICLASS_xt_iclass_nop,
+ 0,
+ Opcode_nop_encode_fns, 0, 0 },
+ { "ret", ICLASS_xt_iclass_return,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_ret_encode_fns, 0, 0 },
+ { "simcall", ICLASS_xt_iclass_simcall,
+ 0,
+ Opcode_simcall_encode_fns, 0, 0 },
+ { "s16i", ICLASS_xt_iclass_s16i,
+ 0,
+ Opcode_s16i_encode_fns, 0, 0 },
+ { "s32i", ICLASS_xt_iclass_s32i,
+ 0,
+ Opcode_s32i_encode_fns, 0, 0 },
+ { "s32nb", ICLASS_xt_iclass_s32nb,
+ 0,
+ Opcode_s32nb_encode_fns, 0, 0 },
+ { "s8i", ICLASS_xt_iclass_s8i,
+ 0,
+ Opcode_s8i_encode_fns, 0, 0 },
+ { "ssr", ICLASS_xt_iclass_sar,
+ 0,
+ Opcode_ssr_encode_fns, 0, 0 },
+ { "ssl", ICLASS_xt_iclass_sar,
+ 0,
+ Opcode_ssl_encode_fns, 0, 0 },
+ { "ssa8l", ICLASS_xt_iclass_sar,
+ 0,
+ Opcode_ssa8l_encode_fns, 0, 0 },
+ { "ssa8b", ICLASS_xt_iclass_sar,
+ 0,
+ Opcode_ssa8b_encode_fns, 0, 0 },
+ { "ssai", ICLASS_xt_iclass_sari,
+ 0,
+ Opcode_ssai_encode_fns, 0, 0 },
+ { "sll", ICLASS_xt_iclass_shifts,
+ 0,
+ Opcode_sll_encode_fns, 0, 0 },
+ { "src", ICLASS_xt_iclass_shiftst,
+ 0,
+ Opcode_src_encode_fns, 0, 0 },
+ { "srl", ICLASS_xt_iclass_shiftt,
+ 0,
+ Opcode_srl_encode_fns, 0, 0 },
+ { "sra", ICLASS_xt_iclass_shiftt,
+ 0,
+ Opcode_sra_encode_fns, 0, 0 },
+ { "slli", ICLASS_xt_iclass_slli,
+ 0,
+ Opcode_slli_encode_fns, 0, 0 },
+ { "srai", ICLASS_xt_iclass_srai,
+ 0,
+ Opcode_srai_encode_fns, 0, 0 },
+ { "srli", ICLASS_xt_iclass_srli,
+ 0,
+ Opcode_srli_encode_fns, 0, 0 },
+ { "memw", ICLASS_xt_iclass_memw,
+ 0,
+ Opcode_memw_encode_fns, 0, 0 },
+ { "extw", ICLASS_xt_iclass_extw,
+ 0,
+ Opcode_extw_encode_fns, 0, 0 },
+ { "isync", ICLASS_xt_iclass_isync,
+ 0,
+ Opcode_isync_encode_fns, 0, 0 },
+ { "rsync", ICLASS_xt_iclass_sync,
+ 0,
+ Opcode_rsync_encode_fns, 0, 0 },
+ { "esync", ICLASS_xt_iclass_sync,
+ 0,
+ Opcode_esync_encode_fns, 0, 0 },
+ { "dsync", ICLASS_xt_iclass_sync,
+ 0,
+ Opcode_dsync_encode_fns, 0, 0 },
+ { "rsil", ICLASS_xt_iclass_rsil,
+ 0,
+ Opcode_rsil_encode_fns, 0, 0 },
+ { "rsr.lend", ICLASS_xt_iclass_rsr_lend,
+ 0,
+ Opcode_rsr_lend_encode_fns, 0, 0 },
+ { "wsr.lend", ICLASS_xt_iclass_wsr_lend,
+ 0,
+ Opcode_wsr_lend_encode_fns, 0, 0 },
+ { "xsr.lend", ICLASS_xt_iclass_xsr_lend,
+ 0,
+ Opcode_xsr_lend_encode_fns, 0, 0 },
+ { "rsr.lcount", ICLASS_xt_iclass_rsr_lcount,
+ 0,
+ Opcode_rsr_lcount_encode_fns, 0, 0 },
+ { "wsr.lcount", ICLASS_xt_iclass_wsr_lcount,
+ 0,
+ Opcode_wsr_lcount_encode_fns, 0, 0 },
+ { "xsr.lcount", ICLASS_xt_iclass_xsr_lcount,
+ 0,
+ Opcode_xsr_lcount_encode_fns, 0, 0 },
+ { "rsr.lbeg", ICLASS_xt_iclass_rsr_lbeg,
+ 0,
+ Opcode_rsr_lbeg_encode_fns, 0, 0 },
+ { "wsr.lbeg", ICLASS_xt_iclass_wsr_lbeg,
+ 0,
+ Opcode_wsr_lbeg_encode_fns, 0, 0 },
+ { "xsr.lbeg", ICLASS_xt_iclass_xsr_lbeg,
+ 0,
+ Opcode_xsr_lbeg_encode_fns, 0, 0 },
+ { "rsr.sar", ICLASS_xt_iclass_rsr_sar,
+ 0,
+ Opcode_rsr_sar_encode_fns, 0, 0 },
+ { "wsr.sar", ICLASS_xt_iclass_wsr_sar,
+ 0,
+ Opcode_wsr_sar_encode_fns, 0, 0 },
+ { "xsr.sar", ICLASS_xt_iclass_xsr_sar,
+ 0,
+ Opcode_xsr_sar_encode_fns, 0, 0 },
+ { "rsr.memctl", ICLASS_xt_iclass_rsr_memctl,
+ 0,
+ Opcode_rsr_memctl_encode_fns, 0, 0 },
+ { "wsr.memctl", ICLASS_xt_iclass_wsr_memctl,
+ 0,
+ Opcode_wsr_memctl_encode_fns, 0, 0 },
+ { "xsr.memctl", ICLASS_xt_iclass_xsr_memctl,
+ 0,
+ Opcode_xsr_memctl_encode_fns, 0, 0 },
+ { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase,
+ 0,
+ Opcode_rsr_litbase_encode_fns, 0, 0 },
+ { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase,
+ 0,
+ Opcode_wsr_litbase_encode_fns, 0, 0 },
+ { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase,
+ 0,
+ Opcode_xsr_litbase_encode_fns, 0, 0 },
+ { "rsr.configid0", ICLASS_xt_iclass_rsr_configid0,
+ 0,
+ Opcode_rsr_configid0_encode_fns, 0, 0 },
+ { "wsr.configid0", ICLASS_xt_iclass_wsr_configid0,
+ 0,
+ Opcode_wsr_configid0_encode_fns, 0, 0 },
+ { "rsr.configid1", ICLASS_xt_iclass_rsr_configid1,
+ 0,
+ Opcode_rsr_configid1_encode_fns, 0, 0 },
+ { "rsr.ps", ICLASS_xt_iclass_rsr_ps,
+ 0,
+ Opcode_rsr_ps_encode_fns, 0, 0 },
+ { "wsr.ps", ICLASS_xt_iclass_wsr_ps,
+ 0,
+ Opcode_wsr_ps_encode_fns, 0, 0 },
+ { "xsr.ps", ICLASS_xt_iclass_xsr_ps,
+ 0,
+ Opcode_xsr_ps_encode_fns, 0, 0 },
+ { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1,
+ 0,
+ Opcode_rsr_epc1_encode_fns, 0, 0 },
+ { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1,
+ 0,
+ Opcode_wsr_epc1_encode_fns, 0, 0 },
+ { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1,
+ 0,
+ Opcode_xsr_epc1_encode_fns, 0, 0 },
+ { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1,
+ 0,
+ Opcode_rsr_excsave1_encode_fns, 0, 0 },
+ { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1,
+ 0,
+ Opcode_wsr_excsave1_encode_fns, 0, 0 },
+ { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1,
+ 0,
+ Opcode_xsr_excsave1_encode_fns, 0, 0 },
+ { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2,
+ 0,
+ Opcode_rsr_epc2_encode_fns, 0, 0 },
+ { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2,
+ 0,
+ Opcode_wsr_epc2_encode_fns, 0, 0 },
+ { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2,
+ 0,
+ Opcode_xsr_epc2_encode_fns, 0, 0 },
+ { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2,
+ 0,
+ Opcode_rsr_excsave2_encode_fns, 0, 0 },
+ { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2,
+ 0,
+ Opcode_wsr_excsave2_encode_fns, 0, 0 },
+ { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2,
+ 0,
+ Opcode_xsr_excsave2_encode_fns, 0, 0 },
+ { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3,
+ 0,
+ Opcode_rsr_epc3_encode_fns, 0, 0 },
+ { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3,
+ 0,
+ Opcode_wsr_epc3_encode_fns, 0, 0 },
+ { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3,
+ 0,
+ Opcode_xsr_epc3_encode_fns, 0, 0 },
+ { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3,
+ 0,
+ Opcode_rsr_excsave3_encode_fns, 0, 0 },
+ { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3,
+ 0,
+ Opcode_wsr_excsave3_encode_fns, 0, 0 },
+ { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3,
+ 0,
+ Opcode_xsr_excsave3_encode_fns, 0, 0 },
+ { "rsr.epc4", ICLASS_xt_iclass_rsr_epc4,
+ 0,
+ Opcode_rsr_epc4_encode_fns, 0, 0 },
+ { "wsr.epc4", ICLASS_xt_iclass_wsr_epc4,
+ 0,
+ Opcode_wsr_epc4_encode_fns, 0, 0 },
+ { "xsr.epc4", ICLASS_xt_iclass_xsr_epc4,
+ 0,
+ Opcode_xsr_epc4_encode_fns, 0, 0 },
+ { "rsr.excsave4", ICLASS_xt_iclass_rsr_excsave4,
+ 0,
+ Opcode_rsr_excsave4_encode_fns, 0, 0 },
+ { "wsr.excsave4", ICLASS_xt_iclass_wsr_excsave4,
+ 0,
+ Opcode_wsr_excsave4_encode_fns, 0, 0 },
+ { "xsr.excsave4", ICLASS_xt_iclass_xsr_excsave4,
+ 0,
+ Opcode_xsr_excsave4_encode_fns, 0, 0 },
+ { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5,
+ 0,
+ Opcode_rsr_epc5_encode_fns, 0, 0 },
+ { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5,
+ 0,
+ Opcode_wsr_epc5_encode_fns, 0, 0 },
+ { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5,
+ 0,
+ Opcode_xsr_epc5_encode_fns, 0, 0 },
+ { "rsr.excsave5", ICLASS_xt_iclass_rsr_excsave5,
+ 0,
+ Opcode_rsr_excsave5_encode_fns, 0, 0 },
+ { "wsr.excsave5", ICLASS_xt_iclass_wsr_excsave5,
+ 0,
+ Opcode_wsr_excsave5_encode_fns, 0, 0 },
+ { "xsr.excsave5", ICLASS_xt_iclass_xsr_excsave5,
+ 0,
+ Opcode_xsr_excsave5_encode_fns, 0, 0 },
+ { "rsr.epc6", ICLASS_xt_iclass_rsr_epc6,
+ 0,
+ Opcode_rsr_epc6_encode_fns, 0, 0 },
+ { "wsr.epc6", ICLASS_xt_iclass_wsr_epc6,
+ 0,
+ Opcode_wsr_epc6_encode_fns, 0, 0 },
+ { "xsr.epc6", ICLASS_xt_iclass_xsr_epc6,
+ 0,
+ Opcode_xsr_epc6_encode_fns, 0, 0 },
+ { "rsr.excsave6", ICLASS_xt_iclass_rsr_excsave6,
+ 0,
+ Opcode_rsr_excsave6_encode_fns, 0, 0 },
+ { "wsr.excsave6", ICLASS_xt_iclass_wsr_excsave6,
+ 0,
+ Opcode_wsr_excsave6_encode_fns, 0, 0 },
+ { "xsr.excsave6", ICLASS_xt_iclass_xsr_excsave6,
+ 0,
+ Opcode_xsr_excsave6_encode_fns, 0, 0 },
+ { "rsr.epc7", ICLASS_xt_iclass_rsr_epc7,
+ 0,
+ Opcode_rsr_epc7_encode_fns, 0, 0 },
+ { "wsr.epc7", ICLASS_xt_iclass_wsr_epc7,
+ 0,
+ Opcode_wsr_epc7_encode_fns, 0, 0 },
+ { "xsr.epc7", ICLASS_xt_iclass_xsr_epc7,
+ 0,
+ Opcode_xsr_epc7_encode_fns, 0, 0 },
+ { "rsr.excsave7", ICLASS_xt_iclass_rsr_excsave7,
+ 0,
+ Opcode_rsr_excsave7_encode_fns, 0, 0 },
+ { "wsr.excsave7", ICLASS_xt_iclass_wsr_excsave7,
+ 0,
+ Opcode_wsr_excsave7_encode_fns, 0, 0 },
+ { "xsr.excsave7", ICLASS_xt_iclass_xsr_excsave7,
+ 0,
+ Opcode_xsr_excsave7_encode_fns, 0, 0 },
+ { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2,
+ 0,
+ Opcode_rsr_eps2_encode_fns, 0, 0 },
+ { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2,
+ 0,
+ Opcode_wsr_eps2_encode_fns, 0, 0 },
+ { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2,
+ 0,
+ Opcode_xsr_eps2_encode_fns, 0, 0 },
+ { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3,
+ 0,
+ Opcode_rsr_eps3_encode_fns, 0, 0 },
+ { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3,
+ 0,
+ Opcode_wsr_eps3_encode_fns, 0, 0 },
+ { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3,
+ 0,
+ Opcode_xsr_eps3_encode_fns, 0, 0 },
+ { "rsr.eps4", ICLASS_xt_iclass_rsr_eps4,
+ 0,
+ Opcode_rsr_eps4_encode_fns, 0, 0 },
+ { "wsr.eps4", ICLASS_xt_iclass_wsr_eps4,
+ 0,
+ Opcode_wsr_eps4_encode_fns, 0, 0 },
+ { "xsr.eps4", ICLASS_xt_iclass_xsr_eps4,
+ 0,
+ Opcode_xsr_eps4_encode_fns, 0, 0 },
+ { "rsr.eps5", ICLASS_xt_iclass_rsr_eps5,
+ 0,
+ Opcode_rsr_eps5_encode_fns, 0, 0 },
+ { "wsr.eps5", ICLASS_xt_iclass_wsr_eps5,
+ 0,
+ Opcode_wsr_eps5_encode_fns, 0, 0 },
+ { "xsr.eps5", ICLASS_xt_iclass_xsr_eps5,
+ 0,
+ Opcode_xsr_eps5_encode_fns, 0, 0 },
+ { "rsr.eps6", ICLASS_xt_iclass_rsr_eps6,
+ 0,
+ Opcode_rsr_eps6_encode_fns, 0, 0 },
+ { "wsr.eps6", ICLASS_xt_iclass_wsr_eps6,
+ 0,
+ Opcode_wsr_eps6_encode_fns, 0, 0 },
+ { "xsr.eps6", ICLASS_xt_iclass_xsr_eps6,
+ 0,
+ Opcode_xsr_eps6_encode_fns, 0, 0 },
+ { "rsr.eps7", ICLASS_xt_iclass_rsr_eps7,
+ 0,
+ Opcode_rsr_eps7_encode_fns, 0, 0 },
+ { "wsr.eps7", ICLASS_xt_iclass_wsr_eps7,
+ 0,
+ Opcode_wsr_eps7_encode_fns, 0, 0 },
+ { "xsr.eps7", ICLASS_xt_iclass_xsr_eps7,
+ 0,
+ Opcode_xsr_eps7_encode_fns, 0, 0 },
+ { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr,
+ 0,
+ Opcode_rsr_excvaddr_encode_fns, 0, 0 },
+ { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr,
+ 0,
+ Opcode_wsr_excvaddr_encode_fns, 0, 0 },
+ { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr,
+ 0,
+ Opcode_xsr_excvaddr_encode_fns, 0, 0 },
+ { "rsr.depc", ICLASS_xt_iclass_rsr_depc,
+ 0,
+ Opcode_rsr_depc_encode_fns, 0, 0 },
+ { "wsr.depc", ICLASS_xt_iclass_wsr_depc,
+ 0,
+ Opcode_wsr_depc_encode_fns, 0, 0 },
+ { "xsr.depc", ICLASS_xt_iclass_xsr_depc,
+ 0,
+ Opcode_xsr_depc_encode_fns, 0, 0 },
+ { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause,
+ 0,
+ Opcode_rsr_exccause_encode_fns, 0, 0 },
+ { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause,
+ 0,
+ Opcode_wsr_exccause_encode_fns, 0, 0 },
+ { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause,
+ 0,
+ Opcode_xsr_exccause_encode_fns, 0, 0 },
+ { "rsr.misc0", ICLASS_xt_iclass_rsr_misc0,
+ 0,
+ Opcode_rsr_misc0_encode_fns, 0, 0 },
+ { "wsr.misc0", ICLASS_xt_iclass_wsr_misc0,
+ 0,
+ Opcode_wsr_misc0_encode_fns, 0, 0 },
+ { "xsr.misc0", ICLASS_xt_iclass_xsr_misc0,
+ 0,
+ Opcode_xsr_misc0_encode_fns, 0, 0 },
+ { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1,
+ 0,
+ Opcode_rsr_misc1_encode_fns, 0, 0 },
+ { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1,
+ 0,
+ Opcode_wsr_misc1_encode_fns, 0, 0 },
+ { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1,
+ 0,
+ Opcode_xsr_misc1_encode_fns, 0, 0 },
+ { "rsr.prid", ICLASS_xt_iclass_rsr_prid,
+ 0,
+ Opcode_rsr_prid_encode_fns, 0, 0 },
+ { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase,
+ 0,
+ Opcode_rsr_vecbase_encode_fns, 0, 0 },
+ { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase,
+ 0,
+ Opcode_wsr_vecbase_encode_fns, 0, 0 },
+ { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase,
+ 0,
+ Opcode_xsr_vecbase_encode_fns, 0, 0 },
+ { "mul16u", ICLASS_xt_mul16,
+ 0,
+ Opcode_mul16u_encode_fns, 0, 0 },
+ { "mul16s", ICLASS_xt_mul16,
+ 0,
+ Opcode_mul16s_encode_fns, 0, 0 },
+ { "mull", ICLASS_xt_mul32,
+ 0,
+ Opcode_mull_encode_fns, 0, 0 },
+ { "mul.aa.ll", ICLASS_xt_iclass_mac16_aa,
+ 0,
+ Opcode_mul_aa_ll_encode_fns, 0, 0 },
+ { "mul.aa.hl", ICLASS_xt_iclass_mac16_aa,
+ 0,
+ Opcode_mul_aa_hl_encode_fns, 0, 0 },
+ { "mul.aa.lh", ICLASS_xt_iclass_mac16_aa,
+ 0,
+ Opcode_mul_aa_lh_encode_fns, 0, 0 },
+ { "mul.aa.hh", ICLASS_xt_iclass_mac16_aa,
+ 0,
+ Opcode_mul_aa_hh_encode_fns, 0, 0 },
+ { "umul.aa.ll", ICLASS_xt_iclass_mac16_aa,
+ 0,
+ Opcode_umul_aa_ll_encode_fns, 0, 0 },
+ { "umul.aa.hl", ICLASS_xt_iclass_mac16_aa,
+ 0,
+ Opcode_umul_aa_hl_encode_fns, 0, 0 },
+ { "umul.aa.lh", ICLASS_xt_iclass_mac16_aa,
+ 0,
+ Opcode_umul_aa_lh_encode_fns, 0, 0 },
+ { "umul.aa.hh", ICLASS_xt_iclass_mac16_aa,
+ 0,
+ Opcode_umul_aa_hh_encode_fns, 0, 0 },
+ { "mul.ad.ll", ICLASS_xt_iclass_mac16_ad,
+ 0,
+ Opcode_mul_ad_ll_encode_fns, 0, 0 },
+ { "mul.ad.hl", ICLASS_xt_iclass_mac16_ad,
+ 0,
+ Opcode_mul_ad_hl_encode_fns, 0, 0 },
+ { "mul.ad.lh", ICLASS_xt_iclass_mac16_ad,
+ 0,
+ Opcode_mul_ad_lh_encode_fns, 0, 0 },
+ { "mul.ad.hh", ICLASS_xt_iclass_mac16_ad,
+ 0,
+ Opcode_mul_ad_hh_encode_fns, 0, 0 },
+ { "mul.da.ll", ICLASS_xt_iclass_mac16_da,
+ 0,
+ Opcode_mul_da_ll_encode_fns, 0, 0 },
+ { "mul.da.hl", ICLASS_xt_iclass_mac16_da,
+ 0,
+ Opcode_mul_da_hl_encode_fns, 0, 0 },
+ { "mul.da.lh", ICLASS_xt_iclass_mac16_da,
+ 0,
+ Opcode_mul_da_lh_encode_fns, 0, 0 },
+ { "mul.da.hh", ICLASS_xt_iclass_mac16_da,
+ 0,
+ Opcode_mul_da_hh_encode_fns, 0, 0 },
+ { "mul.dd.ll", ICLASS_xt_iclass_mac16_dd,
+ 0,
+ Opcode_mul_dd_ll_encode_fns, 0, 0 },
+ { "mul.dd.hl", ICLASS_xt_iclass_mac16_dd,
+ 0,
+ Opcode_mul_dd_hl_encode_fns, 0, 0 },
+ { "mul.dd.lh", ICLASS_xt_iclass_mac16_dd,
+ 0,
+ Opcode_mul_dd_lh_encode_fns, 0, 0 },
+ { "mul.dd.hh", ICLASS_xt_iclass_mac16_dd,
+ 0,
+ Opcode_mul_dd_hh_encode_fns, 0, 0 },
+ { "mula.aa.ll", ICLASS_xt_iclass_mac16a_aa,
+ 0,
+ Opcode_mula_aa_ll_encode_fns, 0, 0 },
+ { "mula.aa.hl", ICLASS_xt_iclass_mac16a_aa,
+ 0,
+ Opcode_mula_aa_hl_encode_fns, 0, 0 },
+ { "mula.aa.lh", ICLASS_xt_iclass_mac16a_aa,
+ 0,
+ Opcode_mula_aa_lh_encode_fns, 0, 0 },
+ { "mula.aa.hh", ICLASS_xt_iclass_mac16a_aa,
+ 0,
+ Opcode_mula_aa_hh_encode_fns, 0, 0 },
+ { "muls.aa.ll", ICLASS_xt_iclass_mac16a_aa,
+ 0,
+ Opcode_muls_aa_ll_encode_fns, 0, 0 },
+ { "muls.aa.hl", ICLASS_xt_iclass_mac16a_aa,
+ 0,
+ Opcode_muls_aa_hl_encode_fns, 0, 0 },
+ { "muls.aa.lh", ICLASS_xt_iclass_mac16a_aa,
+ 0,
+ Opcode_muls_aa_lh_encode_fns, 0, 0 },
+ { "muls.aa.hh", ICLASS_xt_iclass_mac16a_aa,
+ 0,
+ Opcode_muls_aa_hh_encode_fns, 0, 0 },
+ { "mula.ad.ll", ICLASS_xt_iclass_mac16a_ad,
+ 0,
+ Opcode_mula_ad_ll_encode_fns, 0, 0 },
+ { "mula.ad.hl", ICLASS_xt_iclass_mac16a_ad,
+ 0,
+ Opcode_mula_ad_hl_encode_fns, 0, 0 },
+ { "mula.ad.lh", ICLASS_xt_iclass_mac16a_ad,
+ 0,
+ Opcode_mula_ad_lh_encode_fns, 0, 0 },
+ { "mula.ad.hh", ICLASS_xt_iclass_mac16a_ad,
+ 0,
+ Opcode_mula_ad_hh_encode_fns, 0, 0 },
+ { "muls.ad.ll", ICLASS_xt_iclass_mac16a_ad,
+ 0,
+ Opcode_muls_ad_ll_encode_fns, 0, 0 },
+ { "muls.ad.hl", ICLASS_xt_iclass_mac16a_ad,
+ 0,
+ Opcode_muls_ad_hl_encode_fns, 0, 0 },
+ { "muls.ad.lh", ICLASS_xt_iclass_mac16a_ad,
+ 0,
+ Opcode_muls_ad_lh_encode_fns, 0, 0 },
+ { "muls.ad.hh", ICLASS_xt_iclass_mac16a_ad,
+ 0,
+ Opcode_muls_ad_hh_encode_fns, 0, 0 },
+ { "mula.da.ll", ICLASS_xt_iclass_mac16a_da,
+ 0,
+ Opcode_mula_da_ll_encode_fns, 0, 0 },
+ { "mula.da.hl", ICLASS_xt_iclass_mac16a_da,
+ 0,
+ Opcode_mula_da_hl_encode_fns, 0, 0 },
+ { "mula.da.lh", ICLASS_xt_iclass_mac16a_da,
+ 0,
+ Opcode_mula_da_lh_encode_fns, 0, 0 },
+ { "mula.da.hh", ICLASS_xt_iclass_mac16a_da,
+ 0,
+ Opcode_mula_da_hh_encode_fns, 0, 0 },
+ { "muls.da.ll", ICLASS_xt_iclass_mac16a_da,
+ 0,
+ Opcode_muls_da_ll_encode_fns, 0, 0 },
+ { "muls.da.hl", ICLASS_xt_iclass_mac16a_da,
+ 0,
+ Opcode_muls_da_hl_encode_fns, 0, 0 },
+ { "muls.da.lh", ICLASS_xt_iclass_mac16a_da,
+ 0,
+ Opcode_muls_da_lh_encode_fns, 0, 0 },
+ { "muls.da.hh", ICLASS_xt_iclass_mac16a_da,
+ 0,
+ Opcode_muls_da_hh_encode_fns, 0, 0 },
+ { "mula.dd.ll", ICLASS_xt_iclass_mac16a_dd,
+ 0,
+ Opcode_mula_dd_ll_encode_fns, 0, 0 },
+ { "mula.dd.hl", ICLASS_xt_iclass_mac16a_dd,
+ 0,
+ Opcode_mula_dd_hl_encode_fns, 0, 0 },
+ { "mula.dd.lh", ICLASS_xt_iclass_mac16a_dd,
+ 0,
+ Opcode_mula_dd_lh_encode_fns, 0, 0 },
+ { "mula.dd.hh", ICLASS_xt_iclass_mac16a_dd,
+ 0,
+ Opcode_mula_dd_hh_encode_fns, 0, 0 },
+ { "muls.dd.ll", ICLASS_xt_iclass_mac16a_dd,
+ 0,
+ Opcode_muls_dd_ll_encode_fns, 0, 0 },
+ { "muls.dd.hl", ICLASS_xt_iclass_mac16a_dd,
+ 0,
+ Opcode_muls_dd_hl_encode_fns, 0, 0 },
+ { "muls.dd.lh", ICLASS_xt_iclass_mac16a_dd,
+ 0,
+ Opcode_muls_dd_lh_encode_fns, 0, 0 },
+ { "muls.dd.hh", ICLASS_xt_iclass_mac16a_dd,
+ 0,
+ Opcode_muls_dd_hh_encode_fns, 0, 0 },
+ { "mula.da.ll.lddec", ICLASS_xt_iclass_mac16al_da,
+ 0,
+ Opcode_mula_da_ll_lddec_encode_fns, 0, 0 },
+ { "mula.da.ll.ldinc", ICLASS_xt_iclass_mac16al_da,
+ 0,
+ Opcode_mula_da_ll_ldinc_encode_fns, 0, 0 },
+ { "mula.da.hl.lddec", ICLASS_xt_iclass_mac16al_da,
+ 0,
+ Opcode_mula_da_hl_lddec_encode_fns, 0, 0 },
+ { "mula.da.hl.ldinc", ICLASS_xt_iclass_mac16al_da,
+ 0,
+ Opcode_mula_da_hl_ldinc_encode_fns, 0, 0 },
+ { "mula.da.lh.lddec", ICLASS_xt_iclass_mac16al_da,
+ 0,
+ Opcode_mula_da_lh_lddec_encode_fns, 0, 0 },
+ { "mula.da.lh.ldinc", ICLASS_xt_iclass_mac16al_da,
+ 0,
+ Opcode_mula_da_lh_ldinc_encode_fns, 0, 0 },
+ { "mula.da.hh.lddec", ICLASS_xt_iclass_mac16al_da,
+ 0,
+ Opcode_mula_da_hh_lddec_encode_fns, 0, 0 },
+ { "mula.da.hh.ldinc", ICLASS_xt_iclass_mac16al_da,
+ 0,
+ Opcode_mula_da_hh_ldinc_encode_fns, 0, 0 },
+ { "mula.dd.ll.lddec", ICLASS_xt_iclass_mac16al_dd,
+ 0,
+ Opcode_mula_dd_ll_lddec_encode_fns, 0, 0 },
+ { "mula.dd.ll.ldinc", ICLASS_xt_iclass_mac16al_dd,
+ 0,
+ Opcode_mula_dd_ll_ldinc_encode_fns, 0, 0 },
+ { "mula.dd.hl.lddec", ICLASS_xt_iclass_mac16al_dd,
+ 0,
+ Opcode_mula_dd_hl_lddec_encode_fns, 0, 0 },
+ { "mula.dd.hl.ldinc", ICLASS_xt_iclass_mac16al_dd,
+ 0,
+ Opcode_mula_dd_hl_ldinc_encode_fns, 0, 0 },
+ { "mula.dd.lh.lddec", ICLASS_xt_iclass_mac16al_dd,
+ 0,
+ Opcode_mula_dd_lh_lddec_encode_fns, 0, 0 },
+ { "mula.dd.lh.ldinc", ICLASS_xt_iclass_mac16al_dd,
+ 0,
+ Opcode_mula_dd_lh_ldinc_encode_fns, 0, 0 },
+ { "mula.dd.hh.lddec", ICLASS_xt_iclass_mac16al_dd,
+ 0,
+ Opcode_mula_dd_hh_lddec_encode_fns, 0, 0 },
+ { "mula.dd.hh.ldinc", ICLASS_xt_iclass_mac16al_dd,
+ 0,
+ Opcode_mula_dd_hh_ldinc_encode_fns, 0, 0 },
+ { "lddec", ICLASS_xt_iclass_mac16_l,
+ 0,
+ Opcode_lddec_encode_fns, 0, 0 },
+ { "ldinc", ICLASS_xt_iclass_mac16_l,
+ 0,
+ Opcode_ldinc_encode_fns, 0, 0 },
+ { "rsr.m0", ICLASS_xt_iclass_rsr_m0,
+ 0,
+ Opcode_rsr_m0_encode_fns, 0, 0 },
+ { "wsr.m0", ICLASS_xt_iclass_wsr_m0,
+ 0,
+ Opcode_wsr_m0_encode_fns, 0, 0 },
+ { "xsr.m0", ICLASS_xt_iclass_xsr_m0,
+ 0,
+ Opcode_xsr_m0_encode_fns, 0, 0 },
+ { "rsr.m1", ICLASS_xt_iclass_rsr_m1,
+ 0,
+ Opcode_rsr_m1_encode_fns, 0, 0 },
+ { "wsr.m1", ICLASS_xt_iclass_wsr_m1,
+ 0,
+ Opcode_wsr_m1_encode_fns, 0, 0 },
+ { "xsr.m1", ICLASS_xt_iclass_xsr_m1,
+ 0,
+ Opcode_xsr_m1_encode_fns, 0, 0 },
+ { "rsr.m2", ICLASS_xt_iclass_rsr_m2,
+ 0,
+ Opcode_rsr_m2_encode_fns, 0, 0 },
+ { "wsr.m2", ICLASS_xt_iclass_wsr_m2,
+ 0,
+ Opcode_wsr_m2_encode_fns, 0, 0 },
+ { "xsr.m2", ICLASS_xt_iclass_xsr_m2,
+ 0,
+ Opcode_xsr_m2_encode_fns, 0, 0 },
+ { "rsr.m3", ICLASS_xt_iclass_rsr_m3,
+ 0,
+ Opcode_rsr_m3_encode_fns, 0, 0 },
+ { "wsr.m3", ICLASS_xt_iclass_wsr_m3,
+ 0,
+ Opcode_wsr_m3_encode_fns, 0, 0 },
+ { "xsr.m3", ICLASS_xt_iclass_xsr_m3,
+ 0,
+ Opcode_xsr_m3_encode_fns, 0, 0 },
+ { "rsr.acclo", ICLASS_xt_iclass_rsr_acclo,
+ 0,
+ Opcode_rsr_acclo_encode_fns, 0, 0 },
+ { "wsr.acclo", ICLASS_xt_iclass_wsr_acclo,
+ 0,
+ Opcode_wsr_acclo_encode_fns, 0, 0 },
+ { "xsr.acclo", ICLASS_xt_iclass_xsr_acclo,
+ 0,
+ Opcode_xsr_acclo_encode_fns, 0, 0 },
+ { "rsr.acchi", ICLASS_xt_iclass_rsr_acchi,
+ 0,
+ Opcode_rsr_acchi_encode_fns, 0, 0 },
+ { "wsr.acchi", ICLASS_xt_iclass_wsr_acchi,
+ 0,
+ Opcode_wsr_acchi_encode_fns, 0, 0 },
+ { "xsr.acchi", ICLASS_xt_iclass_xsr_acchi,
+ 0,
+ Opcode_xsr_acchi_encode_fns, 0, 0 },
+ { "rfi", ICLASS_xt_iclass_rfi,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfi_encode_fns, 0, 0 },
+ { "waiti", ICLASS_xt_iclass_wait,
+ 0,
+ Opcode_waiti_encode_fns, 0, 0 },
+ { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt,
+ 0,
+ Opcode_rsr_interrupt_encode_fns, 0, 0 },
+ { "wsr.intset", ICLASS_xt_iclass_wsr_intset,
+ 0,
+ Opcode_wsr_intset_encode_fns, 0, 0 },
+ { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear,
+ 0,
+ Opcode_wsr_intclear_encode_fns, 0, 0 },
+ { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable,
+ 0,
+ Opcode_rsr_intenable_encode_fns, 0, 0 },
+ { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable,
+ 0,
+ Opcode_wsr_intenable_encode_fns, 0, 0 },
+ { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable,
+ 0,
+ Opcode_xsr_intenable_encode_fns, 0, 0 },
+ { "break", ICLASS_xt_iclass_break,
+ 0,
+ Opcode_break_encode_fns, 0, 0 },
+ { "break.n", ICLASS_xt_iclass_break_n,
+ 0,
+ Opcode_break_n_encode_fns, 0, 0 },
+ { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0,
+ 0,
+ Opcode_rsr_dbreaka0_encode_fns, 0, 0 },
+ { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0,
+ 0,
+ Opcode_wsr_dbreaka0_encode_fns, 0, 0 },
+ { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0,
+ 0,
+ Opcode_xsr_dbreaka0_encode_fns, 0, 0 },
+ { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0,
+ 0,
+ Opcode_rsr_dbreakc0_encode_fns, 0, 0 },
+ { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0,
+ 0,
+ Opcode_wsr_dbreakc0_encode_fns, 0, 0 },
+ { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0,
+ 0,
+ Opcode_xsr_dbreakc0_encode_fns, 0, 0 },
+ { "rsr.dbreaka1", ICLASS_xt_iclass_rsr_dbreaka1,
+ 0,
+ Opcode_rsr_dbreaka1_encode_fns, 0, 0 },
+ { "wsr.dbreaka1", ICLASS_xt_iclass_wsr_dbreaka1,
+ 0,
+ Opcode_wsr_dbreaka1_encode_fns, 0, 0 },
+ { "xsr.dbreaka1", ICLASS_xt_iclass_xsr_dbreaka1,
+ 0,
+ Opcode_xsr_dbreaka1_encode_fns, 0, 0 },
+ { "rsr.dbreakc1", ICLASS_xt_iclass_rsr_dbreakc1,
+ 0,
+ Opcode_rsr_dbreakc1_encode_fns, 0, 0 },
+ { "wsr.dbreakc1", ICLASS_xt_iclass_wsr_dbreakc1,
+ 0,
+ Opcode_wsr_dbreakc1_encode_fns, 0, 0 },
+ { "xsr.dbreakc1", ICLASS_xt_iclass_xsr_dbreakc1,
+ 0,
+ Opcode_xsr_dbreakc1_encode_fns, 0, 0 },
+ { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0,
+ 0,
+ Opcode_rsr_ibreaka0_encode_fns, 0, 0 },
+ { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0,
+ 0,
+ Opcode_wsr_ibreaka0_encode_fns, 0, 0 },
+ { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0,
+ 0,
+ Opcode_xsr_ibreaka0_encode_fns, 0, 0 },
+ { "rsr.ibreaka1", ICLASS_xt_iclass_rsr_ibreaka1,
+ 0,
+ Opcode_rsr_ibreaka1_encode_fns, 0, 0 },
+ { "wsr.ibreaka1", ICLASS_xt_iclass_wsr_ibreaka1,
+ 0,
+ Opcode_wsr_ibreaka1_encode_fns, 0, 0 },
+ { "xsr.ibreaka1", ICLASS_xt_iclass_xsr_ibreaka1,
+ 0,
+ Opcode_xsr_ibreaka1_encode_fns, 0, 0 },
+ { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable,
+ 0,
+ Opcode_rsr_ibreakenable_encode_fns, 0, 0 },
+ { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable,
+ 0,
+ Opcode_wsr_ibreakenable_encode_fns, 0, 0 },
+ { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable,
+ 0,
+ Opcode_xsr_ibreakenable_encode_fns, 0, 0 },
+ { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause,
+ 0,
+ Opcode_rsr_debugcause_encode_fns, 0, 0 },
+ { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause,
+ 0,
+ Opcode_wsr_debugcause_encode_fns, 0, 0 },
+ { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause,
+ 0,
+ Opcode_xsr_debugcause_encode_fns, 0, 0 },
+ { "rsr.icount", ICLASS_xt_iclass_rsr_icount,
+ 0,
+ Opcode_rsr_icount_encode_fns, 0, 0 },
+ { "wsr.icount", ICLASS_xt_iclass_wsr_icount,
+ 0,
+ Opcode_wsr_icount_encode_fns, 0, 0 },
+ { "xsr.icount", ICLASS_xt_iclass_xsr_icount,
+ 0,
+ Opcode_xsr_icount_encode_fns, 0, 0 },
+ { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel,
+ 0,
+ Opcode_rsr_icountlevel_encode_fns, 0, 0 },
+ { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel,
+ 0,
+ Opcode_wsr_icountlevel_encode_fns, 0, 0 },
+ { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel,
+ 0,
+ Opcode_xsr_icountlevel_encode_fns, 0, 0 },
+ { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr,
+ 0,
+ Opcode_rsr_ddr_encode_fns, 0, 0 },
+ { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr,
+ 0,
+ Opcode_wsr_ddr_encode_fns, 0, 0 },
+ { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr,
+ 0,
+ Opcode_xsr_ddr_encode_fns, 0, 0 },
+ { "lddr32.p", ICLASS_xt_iclass_lddr32_p,
+ 0,
+ Opcode_lddr32_p_encode_fns, 0, 0 },
+ { "sddr32.p", ICLASS_xt_iclass_sddr32_p,
+ 0,
+ Opcode_sddr32_p_encode_fns, 0, 0 },
+ { "rfdo", ICLASS_xt_iclass_rfdo,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfdo_encode_fns, 0, 0 },
+ { "rfdd", ICLASS_xt_iclass_rfdd,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfdd_encode_fns, 0, 0 },
+ { "wsr.mmid", ICLASS_xt_iclass_wsr_mmid,
+ 0,
+ Opcode_wsr_mmid_encode_fns, 0, 0 },
+ { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount,
+ 0,
+ Opcode_rsr_ccount_encode_fns, 0, 0 },
+ { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount,
+ 0,
+ Opcode_wsr_ccount_encode_fns, 0, 0 },
+ { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount,
+ 0,
+ Opcode_xsr_ccount_encode_fns, 0, 0 },
+ { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0,
+ 0,
+ Opcode_rsr_ccompare0_encode_fns, 0, 0 },
+ { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0,
+ 0,
+ Opcode_wsr_ccompare0_encode_fns, 0, 0 },
+ { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0,
+ 0,
+ Opcode_xsr_ccompare0_encode_fns, 0, 0 },
+ { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1,
+ 0,
+ Opcode_rsr_ccompare1_encode_fns, 0, 0 },
+ { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1,
+ 0,
+ Opcode_wsr_ccompare1_encode_fns, 0, 0 },
+ { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1,
+ 0,
+ Opcode_xsr_ccompare1_encode_fns, 0, 0 },
+ { "rsr.ccompare2", ICLASS_xt_iclass_rsr_ccompare2,
+ 0,
+ Opcode_rsr_ccompare2_encode_fns, 0, 0 },
+ { "wsr.ccompare2", ICLASS_xt_iclass_wsr_ccompare2,
+ 0,
+ Opcode_wsr_ccompare2_encode_fns, 0, 0 },
+ { "xsr.ccompare2", ICLASS_xt_iclass_xsr_ccompare2,
+ 0,
+ Opcode_xsr_ccompare2_encode_fns, 0, 0 },
+ { "ipf", ICLASS_xt_iclass_icache,
+ 0,
+ Opcode_ipf_encode_fns, 0, 0 },
+ { "ihi", ICLASS_xt_iclass_icache,
+ 0,
+ Opcode_ihi_encode_fns, 0, 0 },
+ { "ipfl", ICLASS_xt_iclass_icache_lock,
+ 0,
+ Opcode_ipfl_encode_fns, 0, 0 },
+ { "ihu", ICLASS_xt_iclass_icache_lock,
+ 0,
+ Opcode_ihu_encode_fns, 0, 0 },
+ { "iiu", ICLASS_xt_iclass_icache_lock,
+ 0,
+ Opcode_iiu_encode_fns, 0, 0 },
+ { "iii", ICLASS_xt_iclass_icache_inv,
+ 0,
+ Opcode_iii_encode_fns, 0, 0 },
+ { "lict", ICLASS_xt_iclass_licx,
+ 0,
+ Opcode_lict_encode_fns, 0, 0 },
+ { "licw", ICLASS_xt_iclass_licx,
+ 0,
+ Opcode_licw_encode_fns, 0, 0 },
+ { "sict", ICLASS_xt_iclass_sicx,
+ 0,
+ Opcode_sict_encode_fns, 0, 0 },
+ { "sicw", ICLASS_xt_iclass_sicx,
+ 0,
+ Opcode_sicw_encode_fns, 0, 0 },
+ { "dhwb", ICLASS_xt_iclass_dcache,
+ 0,
+ Opcode_dhwb_encode_fns, 0, 0 },
+ { "dhwbi", ICLASS_xt_iclass_dcache,
+ 0,
+ Opcode_dhwbi_encode_fns, 0, 0 },
+ { "diwbui.p", ICLASS_xt_iclass_dcache_dyn,
+ 0,
+ Opcode_diwbui_p_encode_fns, 0, 0 },
+ { "diwb", ICLASS_xt_iclass_dcache_ind,
+ 0,
+ Opcode_diwb_encode_fns, 0, 0 },
+ { "diwbi", ICLASS_xt_iclass_dcache_ind,
+ 0,
+ Opcode_diwbi_encode_fns, 0, 0 },
+ { "dhi", ICLASS_xt_iclass_dcache_inv,
+ 0,
+ Opcode_dhi_encode_fns, 0, 0 },
+ { "dii", ICLASS_xt_iclass_dcache_inv,
+ 0,
+ Opcode_dii_encode_fns, 0, 0 },
+ { "dpfr", ICLASS_xt_iclass_dpf,
+ 0,
+ Opcode_dpfr_encode_fns, 0, 0 },
+ { "dpfw", ICLASS_xt_iclass_dpf,
+ 0,
+ Opcode_dpfw_encode_fns, 0, 0 },
+ { "dpfro", ICLASS_xt_iclass_dpf,
+ 0,
+ Opcode_dpfro_encode_fns, 0, 0 },
+ { "dpfwo", ICLASS_xt_iclass_dpf,
+ 0,
+ Opcode_dpfwo_encode_fns, 0, 0 },
+ { "dpfl", ICLASS_xt_iclass_dcache_lock,
+ 0,
+ Opcode_dpfl_encode_fns, 0, 0 },
+ { "dhu", ICLASS_xt_iclass_dcache_lock,
+ 0,
+ Opcode_dhu_encode_fns, 0, 0 },
+ { "diu", ICLASS_xt_iclass_dcache_lock,
+ 0,
+ Opcode_diu_encode_fns, 0, 0 },
+ { "sdct", ICLASS_xt_iclass_sdct,
+ 0,
+ Opcode_sdct_encode_fns, 0, 0 },
+ { "ldct", ICLASS_xt_iclass_ldct,
+ 0,
+ Opcode_ldct_encode_fns, 0, 0 },
+ { "idtlb", ICLASS_xt_iclass_idtlb,
+ 0,
+ Opcode_idtlb_encode_fns, 0, 0 },
+ { "pdtlb", ICLASS_xt_iclass_rdtlb,
+ 0,
+ Opcode_pdtlb_encode_fns, 0, 0 },
+ { "rdtlb0", ICLASS_xt_iclass_rdtlb,
+ 0,
+ Opcode_rdtlb0_encode_fns, 0, 0 },
+ { "rdtlb1", ICLASS_xt_iclass_rdtlb,
+ 0,
+ Opcode_rdtlb1_encode_fns, 0, 0 },
+ { "wdtlb", ICLASS_xt_iclass_wdtlb,
+ 0,
+ Opcode_wdtlb_encode_fns, 0, 0 },
+ { "iitlb", ICLASS_xt_iclass_iitlb,
+ 0,
+ Opcode_iitlb_encode_fns, 0, 0 },
+ { "pitlb", ICLASS_xt_iclass_ritlb,
+ 0,
+ Opcode_pitlb_encode_fns, 0, 0 },
+ { "ritlb0", ICLASS_xt_iclass_ritlb,
+ 0,
+ Opcode_ritlb0_encode_fns, 0, 0 },
+ { "ritlb1", ICLASS_xt_iclass_ritlb,
+ 0,
+ Opcode_ritlb1_encode_fns, 0, 0 },
+ { "witlb", ICLASS_xt_iclass_witlb,
+ 0,
+ Opcode_witlb_encode_fns, 0, 0 },
+ { "clamps", ICLASS_xt_iclass_clamp,
+ 0,
+ Opcode_clamps_encode_fns, 0, 0 },
+ { "min", ICLASS_xt_iclass_minmax,
+ 0,
+ Opcode_min_encode_fns, 0, 0 },
+ { "max", ICLASS_xt_iclass_minmax,
+ 0,
+ Opcode_max_encode_fns, 0, 0 },
+ { "minu", ICLASS_xt_iclass_minmax,
+ 0,
+ Opcode_minu_encode_fns, 0, 0 },
+ { "maxu", ICLASS_xt_iclass_minmax,
+ 0,
+ Opcode_maxu_encode_fns, 0, 0 },
+ { "nsa", ICLASS_xt_iclass_nsa,
+ 0,
+ Opcode_nsa_encode_fns, 0, 0 },
+ { "nsau", ICLASS_xt_iclass_nsa,
+ 0,
+ Opcode_nsau_encode_fns, 0, 0 },
+ { "sext", ICLASS_xt_iclass_sx,
+ 0,
+ Opcode_sext_encode_fns, 0, 0 },
+ { "l32ai", ICLASS_xt_iclass_l32ai,
+ 0,
+ Opcode_l32ai_encode_fns, 0, 0 },
+ { "s32ri", ICLASS_xt_iclass_s32ri,
+ 0,
+ Opcode_s32ri_encode_fns, 0, 0 },
+ { "s32c1i", ICLASS_xt_iclass_s32c1i,
+ 0,
+ Opcode_s32c1i_encode_fns, 0, 0 },
+ { "rsr.scompare1", ICLASS_xt_iclass_rsr_scompare1,
+ 0,
+ Opcode_rsr_scompare1_encode_fns, 0, 0 },
+ { "wsr.scompare1", ICLASS_xt_iclass_wsr_scompare1,
+ 0,
+ Opcode_wsr_scompare1_encode_fns, 0, 0 },
+ { "xsr.scompare1", ICLASS_xt_iclass_xsr_scompare1,
+ 0,
+ Opcode_xsr_scompare1_encode_fns, 0, 0 },
+ { "rsr.atomctl", ICLASS_xt_iclass_rsr_atomctl,
+ 0,
+ Opcode_rsr_atomctl_encode_fns, 0, 0 },
+ { "wsr.atomctl", ICLASS_xt_iclass_wsr_atomctl,
+ 0,
+ Opcode_wsr_atomctl_encode_fns, 0, 0 },
+ { "xsr.atomctl", ICLASS_xt_iclass_xsr_atomctl,
+ 0,
+ Opcode_xsr_atomctl_encode_fns, 0, 0 },
+ { "quou", ICLASS_xt_iclass_div,
+ 0,
+ Opcode_quou_encode_fns, 0, 0 },
+ { "quos", ICLASS_xt_iclass_div,
+ 0,
+ Opcode_quos_encode_fns, 0, 0 },
+ { "remu", ICLASS_xt_iclass_div,
+ 0,
+ Opcode_remu_encode_fns, 0, 0 },
+ { "rems", ICLASS_xt_iclass_div,
+ 0,
+ Opcode_rems_encode_fns, 0, 0 },
+ { "rer", ICLASS_xt_iclass_rer,
+ 0,
+ Opcode_rer_encode_fns, 0, 0 },
+ { "wer", ICLASS_xt_iclass_wer,
+ 0,
+ Opcode_wer_encode_fns, 0, 0 },
+ { "rur.expstate", ICLASS_rur_expstate,
+ 0,
+ Opcode_rur_expstate_encode_fns, 0, 0 },
+ { "wur.expstate", ICLASS_wur_expstate,
+ 0,
+ Opcode_wur_expstate_encode_fns, 0, 0 },
+ { "read_impwire", ICLASS_iclass_READ_IMPWIRE,
+ 0,
+ Opcode_read_impwire_encode_fns, 0, 0 },
+ { "setb_expstate", ICLASS_iclass_SETB_EXPSTATE,
+ 0,
+ Opcode_setb_expstate_encode_fns, 0, 0 },
+ { "clrb_expstate", ICLASS_iclass_CLRB_EXPSTATE,
+ 0,
+ Opcode_clrb_expstate_encode_fns, 0, 0 },
+ { "wrmsk_expstate", ICLASS_iclass_WRMSK_EXPSTATE,
+ 0,
+ Opcode_wrmsk_expstate_encode_fns, 0, 0 }
+};
+
+enum xtensa_opcode_id {
+ OPCODE_EXCW,
+ OPCODE_RFE,
+ OPCODE_RFDE,
+ OPCODE_SYSCALL,
+ OPCODE_CALL12,
+ OPCODE_CALL8,
+ OPCODE_CALL4,
+ OPCODE_CALLX12,
+ OPCODE_CALLX8,
+ OPCODE_CALLX4,
+ OPCODE_ENTRY,
+ OPCODE_MOVSP,
+ OPCODE_ROTW,
+ OPCODE_RETW,
+ OPCODE_RETW_N,
+ OPCODE_RFWO,
+ OPCODE_RFWU,
+ OPCODE_L32E,
+ OPCODE_S32E,
+ OPCODE_RSR_WINDOWBASE,
+ OPCODE_WSR_WINDOWBASE,
+ OPCODE_XSR_WINDOWBASE,
+ OPCODE_RSR_WINDOWSTART,
+ OPCODE_WSR_WINDOWSTART,
+ OPCODE_XSR_WINDOWSTART,
+ OPCODE_ADD_N,
+ OPCODE_ADDI_N,
+ OPCODE_BEQZ_N,
+ OPCODE_BNEZ_N,
+ OPCODE_ILL_N,
+ OPCODE_L32I_N,
+ OPCODE_MOV_N,
+ OPCODE_MOVI_N,
+ OPCODE_NOP_N,
+ OPCODE_RET_N,
+ OPCODE_S32I_N,
+ OPCODE_ADDI,
+ OPCODE_ADDMI,
+ OPCODE_ADD,
+ OPCODE_SUB,
+ OPCODE_ADDX2,
+ OPCODE_ADDX4,
+ OPCODE_ADDX8,
+ OPCODE_SUBX2,
+ OPCODE_SUBX4,
+ OPCODE_SUBX8,
+ OPCODE_AND,
+ OPCODE_OR,
+ OPCODE_XOR,
+ OPCODE_BEQI,
+ OPCODE_BNEI,
+ OPCODE_BGEI,
+ OPCODE_BLTI,
+ OPCODE_BBCI,
+ OPCODE_BBSI,
+ OPCODE_BGEUI,
+ OPCODE_BLTUI,
+ OPCODE_BEQ,
+ OPCODE_BNE,
+ OPCODE_BGE,
+ OPCODE_BLT,
+ OPCODE_BGEU,
+ OPCODE_BLTU,
+ OPCODE_BANY,
+ OPCODE_BNONE,
+ OPCODE_BALL,
+ OPCODE_BNALL,
+ OPCODE_BBC,
+ OPCODE_BBS,
+ OPCODE_BEQZ,
+ OPCODE_BNEZ,
+ OPCODE_BGEZ,
+ OPCODE_BLTZ,
+ OPCODE_CALL0,
+ OPCODE_CALLX0,
+ OPCODE_EXTUI,
+ OPCODE_ILL,
+ OPCODE_J,
+ OPCODE_JX,
+ OPCODE_L16UI,
+ OPCODE_L16SI,
+ OPCODE_L32I,
+ OPCODE_L32R,
+ OPCODE_L8UI,
+ OPCODE_LOOP,
+ OPCODE_LOOPNEZ,
+ OPCODE_LOOPGTZ,
+ OPCODE_MOVI,
+ OPCODE_MOVEQZ,
+ OPCODE_MOVNEZ,
+ OPCODE_MOVLTZ,
+ OPCODE_MOVGEZ,
+ OPCODE_NEG,
+ OPCODE_ABS,
+ OPCODE_NOP,
+ OPCODE_RET,
+ OPCODE_SIMCALL,
+ OPCODE_S16I,
+ OPCODE_S32I,
+ OPCODE_S32NB,
+ OPCODE_S8I,
+ OPCODE_SSR,
+ OPCODE_SSL,
+ OPCODE_SSA8L,
+ OPCODE_SSA8B,
+ OPCODE_SSAI,
+ OPCODE_SLL,
+ OPCODE_SRC,
+ OPCODE_SRL,
+ OPCODE_SRA,
+ OPCODE_SLLI,
+ OPCODE_SRAI,
+ OPCODE_SRLI,
+ OPCODE_MEMW,
+ OPCODE_EXTW,
+ OPCODE_ISYNC,
+ OPCODE_RSYNC,
+ OPCODE_ESYNC,
+ OPCODE_DSYNC,
+ OPCODE_RSIL,
+ OPCODE_RSR_LEND,
+ OPCODE_WSR_LEND,
+ OPCODE_XSR_LEND,
+ OPCODE_RSR_LCOUNT,
+ OPCODE_WSR_LCOUNT,
+ OPCODE_XSR_LCOUNT,
+ OPCODE_RSR_LBEG,
+ OPCODE_WSR_LBEG,
+ OPCODE_XSR_LBEG,
+ OPCODE_RSR_SAR,
+ OPCODE_WSR_SAR,
+ OPCODE_XSR_SAR,
+ OPCODE_RSR_MEMCTL,
+ OPCODE_WSR_MEMCTL,
+ OPCODE_XSR_MEMCTL,
+ OPCODE_RSR_LITBASE,
+ OPCODE_WSR_LITBASE,
+ OPCODE_XSR_LITBASE,
+ OPCODE_RSR_CONFIGID0,
+ OPCODE_WSR_CONFIGID0,
+ OPCODE_RSR_CONFIGID1,
+ OPCODE_RSR_PS,
+ OPCODE_WSR_PS,
+ OPCODE_XSR_PS,
+ OPCODE_RSR_EPC1,
+ OPCODE_WSR_EPC1,
+ OPCODE_XSR_EPC1,
+ OPCODE_RSR_EXCSAVE1,
+ OPCODE_WSR_EXCSAVE1,
+ OPCODE_XSR_EXCSAVE1,
+ OPCODE_RSR_EPC2,
+ OPCODE_WSR_EPC2,
+ OPCODE_XSR_EPC2,
+ OPCODE_RSR_EXCSAVE2,
+ OPCODE_WSR_EXCSAVE2,
+ OPCODE_XSR_EXCSAVE2,
+ OPCODE_RSR_EPC3,
+ OPCODE_WSR_EPC3,
+ OPCODE_XSR_EPC3,
+ OPCODE_RSR_EXCSAVE3,
+ OPCODE_WSR_EXCSAVE3,
+ OPCODE_XSR_EXCSAVE3,
+ OPCODE_RSR_EPC4,
+ OPCODE_WSR_EPC4,
+ OPCODE_XSR_EPC4,
+ OPCODE_RSR_EXCSAVE4,
+ OPCODE_WSR_EXCSAVE4,
+ OPCODE_XSR_EXCSAVE4,
+ OPCODE_RSR_EPC5,
+ OPCODE_WSR_EPC5,
+ OPCODE_XSR_EPC5,
+ OPCODE_RSR_EXCSAVE5,
+ OPCODE_WSR_EXCSAVE5,
+ OPCODE_XSR_EXCSAVE5,
+ OPCODE_RSR_EPC6,
+ OPCODE_WSR_EPC6,
+ OPCODE_XSR_EPC6,
+ OPCODE_RSR_EXCSAVE6,
+ OPCODE_WSR_EXCSAVE6,
+ OPCODE_XSR_EXCSAVE6,
+ OPCODE_RSR_EPC7,
+ OPCODE_WSR_EPC7,
+ OPCODE_XSR_EPC7,
+ OPCODE_RSR_EXCSAVE7,
+ OPCODE_WSR_EXCSAVE7,
+ OPCODE_XSR_EXCSAVE7,
+ OPCODE_RSR_EPS2,
+ OPCODE_WSR_EPS2,
+ OPCODE_XSR_EPS2,
+ OPCODE_RSR_EPS3,
+ OPCODE_WSR_EPS3,
+ OPCODE_XSR_EPS3,
+ OPCODE_RSR_EPS4,
+ OPCODE_WSR_EPS4,
+ OPCODE_XSR_EPS4,
+ OPCODE_RSR_EPS5,
+ OPCODE_WSR_EPS5,
+ OPCODE_XSR_EPS5,
+ OPCODE_RSR_EPS6,
+ OPCODE_WSR_EPS6,
+ OPCODE_XSR_EPS6,
+ OPCODE_RSR_EPS7,
+ OPCODE_WSR_EPS7,
+ OPCODE_XSR_EPS7,
+ OPCODE_RSR_EXCVADDR,
+ OPCODE_WSR_EXCVADDR,
+ OPCODE_XSR_EXCVADDR,
+ OPCODE_RSR_DEPC,
+ OPCODE_WSR_DEPC,
+ OPCODE_XSR_DEPC,
+ OPCODE_RSR_EXCCAUSE,
+ OPCODE_WSR_EXCCAUSE,
+ OPCODE_XSR_EXCCAUSE,
+ OPCODE_RSR_MISC0,
+ OPCODE_WSR_MISC0,
+ OPCODE_XSR_MISC0,
+ OPCODE_RSR_MISC1,
+ OPCODE_WSR_MISC1,
+ OPCODE_XSR_MISC1,
+ OPCODE_RSR_PRID,
+ OPCODE_RSR_VECBASE,
+ OPCODE_WSR_VECBASE,
+ OPCODE_XSR_VECBASE,
+ OPCODE_MUL16U,
+ OPCODE_MUL16S,
+ OPCODE_MULL,
+ OPCODE_MUL_AA_LL,
+ OPCODE_MUL_AA_HL,
+ OPCODE_MUL_AA_LH,
+ OPCODE_MUL_AA_HH,
+ OPCODE_UMUL_AA_LL,
+ OPCODE_UMUL_AA_HL,
+ OPCODE_UMUL_AA_LH,
+ OPCODE_UMUL_AA_HH,
+ OPCODE_MUL_AD_LL,
+ OPCODE_MUL_AD_HL,
+ OPCODE_MUL_AD_LH,
+ OPCODE_MUL_AD_HH,
+ OPCODE_MUL_DA_LL,
+ OPCODE_MUL_DA_HL,
+ OPCODE_MUL_DA_LH,
+ OPCODE_MUL_DA_HH,
+ OPCODE_MUL_DD_LL,
+ OPCODE_MUL_DD_HL,
+ OPCODE_MUL_DD_LH,
+ OPCODE_MUL_DD_HH,
+ OPCODE_MULA_AA_LL,
+ OPCODE_MULA_AA_HL,
+ OPCODE_MULA_AA_LH,
+ OPCODE_MULA_AA_HH,
+ OPCODE_MULS_AA_LL,
+ OPCODE_MULS_AA_HL,
+ OPCODE_MULS_AA_LH,
+ OPCODE_MULS_AA_HH,
+ OPCODE_MULA_AD_LL,
+ OPCODE_MULA_AD_HL,
+ OPCODE_MULA_AD_LH,
+ OPCODE_MULA_AD_HH,
+ OPCODE_MULS_AD_LL,
+ OPCODE_MULS_AD_HL,
+ OPCODE_MULS_AD_LH,
+ OPCODE_MULS_AD_HH,
+ OPCODE_MULA_DA_LL,
+ OPCODE_MULA_DA_HL,
+ OPCODE_MULA_DA_LH,
+ OPCODE_MULA_DA_HH,
+ OPCODE_MULS_DA_LL,
+ OPCODE_MULS_DA_HL,
+ OPCODE_MULS_DA_LH,
+ OPCODE_MULS_DA_HH,
+ OPCODE_MULA_DD_LL,
+ OPCODE_MULA_DD_HL,
+ OPCODE_MULA_DD_LH,
+ OPCODE_MULA_DD_HH,
+ OPCODE_MULS_DD_LL,
+ OPCODE_MULS_DD_HL,
+ OPCODE_MULS_DD_LH,
+ OPCODE_MULS_DD_HH,
+ OPCODE_MULA_DA_LL_LDDEC,
+ OPCODE_MULA_DA_LL_LDINC,
+ OPCODE_MULA_DA_HL_LDDEC,
+ OPCODE_MULA_DA_HL_LDINC,
+ OPCODE_MULA_DA_LH_LDDEC,
+ OPCODE_MULA_DA_LH_LDINC,
+ OPCODE_MULA_DA_HH_LDDEC,
+ OPCODE_MULA_DA_HH_LDINC,
+ OPCODE_MULA_DD_LL_LDDEC,
+ OPCODE_MULA_DD_LL_LDINC,
+ OPCODE_MULA_DD_HL_LDDEC,
+ OPCODE_MULA_DD_HL_LDINC,
+ OPCODE_MULA_DD_LH_LDDEC,
+ OPCODE_MULA_DD_LH_LDINC,
+ OPCODE_MULA_DD_HH_LDDEC,
+ OPCODE_MULA_DD_HH_LDINC,
+ OPCODE_LDDEC,
+ OPCODE_LDINC,
+ OPCODE_RSR_M0,
+ OPCODE_WSR_M0,
+ OPCODE_XSR_M0,
+ OPCODE_RSR_M1,
+ OPCODE_WSR_M1,
+ OPCODE_XSR_M1,
+ OPCODE_RSR_M2,
+ OPCODE_WSR_M2,
+ OPCODE_XSR_M2,
+ OPCODE_RSR_M3,
+ OPCODE_WSR_M3,
+ OPCODE_XSR_M3,
+ OPCODE_RSR_ACCLO,
+ OPCODE_WSR_ACCLO,
+ OPCODE_XSR_ACCLO,
+ OPCODE_RSR_ACCHI,
+ OPCODE_WSR_ACCHI,
+ OPCODE_XSR_ACCHI,
+ OPCODE_RFI,
+ OPCODE_WAITI,
+ OPCODE_RSR_INTERRUPT,
+ OPCODE_WSR_INTSET,
+ OPCODE_WSR_INTCLEAR,
+ OPCODE_RSR_INTENABLE,
+ OPCODE_WSR_INTENABLE,
+ OPCODE_XSR_INTENABLE,
+ OPCODE_BREAK,
+ OPCODE_BREAK_N,
+ OPCODE_RSR_DBREAKA0,
+ OPCODE_WSR_DBREAKA0,
+ OPCODE_XSR_DBREAKA0,
+ OPCODE_RSR_DBREAKC0,
+ OPCODE_WSR_DBREAKC0,
+ OPCODE_XSR_DBREAKC0,
+ OPCODE_RSR_DBREAKA1,
+ OPCODE_WSR_DBREAKA1,
+ OPCODE_XSR_DBREAKA1,
+ OPCODE_RSR_DBREAKC1,
+ OPCODE_WSR_DBREAKC1,
+ OPCODE_XSR_DBREAKC1,
+ OPCODE_RSR_IBREAKA0,
+ OPCODE_WSR_IBREAKA0,
+ OPCODE_XSR_IBREAKA0,
+ OPCODE_RSR_IBREAKA1,
+ OPCODE_WSR_IBREAKA1,
+ OPCODE_XSR_IBREAKA1,
+ OPCODE_RSR_IBREAKENABLE,
+ OPCODE_WSR_IBREAKENABLE,
+ OPCODE_XSR_IBREAKENABLE,
+ OPCODE_RSR_DEBUGCAUSE,
+ OPCODE_WSR_DEBUGCAUSE,
+ OPCODE_XSR_DEBUGCAUSE,
+ OPCODE_RSR_ICOUNT,
+ OPCODE_WSR_ICOUNT,
+ OPCODE_XSR_ICOUNT,
+ OPCODE_RSR_ICOUNTLEVEL,
+ OPCODE_WSR_ICOUNTLEVEL,
+ OPCODE_XSR_ICOUNTLEVEL,
+ OPCODE_RSR_DDR,
+ OPCODE_WSR_DDR,
+ OPCODE_XSR_DDR,
+ OPCODE_LDDR32_P,
+ OPCODE_SDDR32_P,
+ OPCODE_RFDO,
+ OPCODE_RFDD,
+ OPCODE_WSR_MMID,
+ OPCODE_RSR_CCOUNT,
+ OPCODE_WSR_CCOUNT,
+ OPCODE_XSR_CCOUNT,
+ OPCODE_RSR_CCOMPARE0,
+ OPCODE_WSR_CCOMPARE0,
+ OPCODE_XSR_CCOMPARE0,
+ OPCODE_RSR_CCOMPARE1,
+ OPCODE_WSR_CCOMPARE1,
+ OPCODE_XSR_CCOMPARE1,
+ OPCODE_RSR_CCOMPARE2,
+ OPCODE_WSR_CCOMPARE2,
+ OPCODE_XSR_CCOMPARE2,
+ OPCODE_IPF,
+ OPCODE_IHI,
+ OPCODE_IPFL,
+ OPCODE_IHU,
+ OPCODE_IIU,
+ OPCODE_III,
+ OPCODE_LICT,
+ OPCODE_LICW,
+ OPCODE_SICT,
+ OPCODE_SICW,
+ OPCODE_DHWB,
+ OPCODE_DHWBI,
+ OPCODE_DIWBUI_P,
+ OPCODE_DIWB,
+ OPCODE_DIWBI,
+ OPCODE_DHI,
+ OPCODE_DII,
+ OPCODE_DPFR,
+ OPCODE_DPFW,
+ OPCODE_DPFRO,
+ OPCODE_DPFWO,
+ OPCODE_DPFL,
+ OPCODE_DHU,
+ OPCODE_DIU,
+ OPCODE_SDCT,
+ OPCODE_LDCT,
+ OPCODE_IDTLB,
+ OPCODE_PDTLB,
+ OPCODE_RDTLB0,
+ OPCODE_RDTLB1,
+ OPCODE_WDTLB,
+ OPCODE_IITLB,
+ OPCODE_PITLB,
+ OPCODE_RITLB0,
+ OPCODE_RITLB1,
+ OPCODE_WITLB,
+ OPCODE_CLAMPS,
+ OPCODE_MIN,
+ OPCODE_MAX,
+ OPCODE_MINU,
+ OPCODE_MAXU,
+ OPCODE_NSA,
+ OPCODE_NSAU,
+ OPCODE_SEXT,
+ OPCODE_L32AI,
+ OPCODE_S32RI,
+ OPCODE_S32C1I,
+ OPCODE_RSR_SCOMPARE1,
+ OPCODE_WSR_SCOMPARE1,
+ OPCODE_XSR_SCOMPARE1,
+ OPCODE_RSR_ATOMCTL,
+ OPCODE_WSR_ATOMCTL,
+ OPCODE_XSR_ATOMCTL,
+ OPCODE_QUOU,
+ OPCODE_QUOS,
+ OPCODE_REMU,
+ OPCODE_REMS,
+ OPCODE_RER,
+ OPCODE_WER,
+ OPCODE_RUR_EXPSTATE,
+ OPCODE_WUR_EXPSTATE,
+ OPCODE_READ_IMPWIRE,
+ OPCODE_SETB_EXPSTATE,
+ OPCODE_CLRB_EXPSTATE,
+ OPCODE_WRMSK_EXPSTATE
+};
+
+
+/* Slot-specific opcode decode functions. */
+
+static int
+Slot_inst_decode (const xtensa_insnbuf insn)
+{
+ if (Field_op0_Slot_inst_get (insn) == 0)
+ {
+ if (Field_op1_Slot_inst_get (insn) == 0)
+ {
+ if (Field_op2_Slot_inst_get (insn) == 0)
+ {
+ if (Field_r_Slot_inst_get (insn) == 0)
+ {
+ if (Field_m_Slot_inst_get (insn) == 0 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_n_Slot_inst_get (insn) == 0)
+ return OPCODE_ILL;
+ if (Field_m_Slot_inst_get (insn) == 2)
+ {
+ if (Field_n_Slot_inst_get (insn) == 0)
+ return OPCODE_RET;
+ if (Field_n_Slot_inst_get (insn) == 1)
+ return OPCODE_RETW;
+ if (Field_n_Slot_inst_get (insn) == 2)
+ return OPCODE_JX;
+ }
+ if (Field_m_Slot_inst_get (insn) == 3)
+ {
+ if (Field_n_Slot_inst_get (insn) == 0)
+ return OPCODE_CALLX0;
+ if (Field_n_Slot_inst_get (insn) == 1)
+ return OPCODE_CALLX4;
+ if (Field_n_Slot_inst_get (insn) == 2)
+ return OPCODE_CALLX8;
+ if (Field_n_Slot_inst_get (insn) == 3)
+ return OPCODE_CALLX12;
+ }
+ }
+ if (Field_r_Slot_inst_get (insn) == 1)
+ return OPCODE_MOVSP;
+ if (Field_r_Slot_inst_get (insn) == 2)
+ {
+ if (Field_s_Slot_inst_get (insn) == 0)
+ {
+ if (Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_ISYNC;
+ if (Field_t_Slot_inst_get (insn) == 1)
+ return OPCODE_RSYNC;
+ if (Field_t_Slot_inst_get (insn) == 2)
+ return OPCODE_ESYNC;
+ if (Field_t_Slot_inst_get (insn) == 3)
+ return OPCODE_DSYNC;
+ if (Field_t_Slot_inst_get (insn) == 8)
+ return OPCODE_EXCW;
+ if (Field_t_Slot_inst_get (insn) == 12)
+ return OPCODE_MEMW;
+ if (Field_t_Slot_inst_get (insn) == 13)
+ return OPCODE_EXTW;
+ if (Field_t_Slot_inst_get (insn) == 15)
+ return OPCODE_NOP;
+ }
+ }
+ if (Field_r_Slot_inst_get (insn) == 3)
+ {
+ if (Field_t_Slot_inst_get (insn) == 0)
+ {
+ if (Field_s_Slot_inst_get (insn) == 0)
+ return OPCODE_RFE;
+ if (Field_s_Slot_inst_get (insn) == 2)
+ return OPCODE_RFDE;
+ if (Field_s_Slot_inst_get (insn) == 4)
+ return OPCODE_RFWO;
+ if (Field_s_Slot_inst_get (insn) == 5)
+ return OPCODE_RFWU;
+ }
+ if (Field_t_Slot_inst_get (insn) == 1)
+ return OPCODE_RFI;
+ }
+ if (Field_r_Slot_inst_get (insn) == 4)
+ return OPCODE_BREAK;
+ if (Field_r_Slot_inst_get (insn) == 5)
+ {
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_SYSCALL;
+ if (Field_s_Slot_inst_get (insn) == 1 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_SIMCALL;
+ }
+ if (Field_r_Slot_inst_get (insn) == 6)
+ return OPCODE_RSIL;
+ if (Field_r_Slot_inst_get (insn) == 7 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_WAITI;
+ if (Field_r_Slot_inst_get (insn) == 7)
+ {
+ if (Field_t_Slot_inst_get (insn) == 14)
+ return OPCODE_LDDR32_P;
+ if (Field_t_Slot_inst_get (insn) == 15)
+ return OPCODE_SDDR32_P;
+ }
+ }
+ if (Field_op2_Slot_inst_get (insn) == 1)
+ return OPCODE_AND;
+ if (Field_op2_Slot_inst_get (insn) == 2)
+ return OPCODE_OR;
+ if (Field_op2_Slot_inst_get (insn) == 3)
+ return OPCODE_XOR;
+ if (Field_op2_Slot_inst_get (insn) == 4)
+ {
+ if (Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_SSR;
+ if (Field_r_Slot_inst_get (insn) == 1 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_SSL;
+ if (Field_r_Slot_inst_get (insn) == 2 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_SSA8L;
+ if (Field_r_Slot_inst_get (insn) == 3 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_SSA8B;
+ if (Field_r_Slot_inst_get (insn) == 4 &&
+ Field_thi3_Slot_inst_get (insn) == 0)
+ return OPCODE_SSAI;
+ if (Field_r_Slot_inst_get (insn) == 6)
+ return OPCODE_RER;
+ if (Field_r_Slot_inst_get (insn) == 7)
+ return OPCODE_WER;
+ if (Field_r_Slot_inst_get (insn) == 8 &&
+ Field_s_Slot_inst_get (insn) == 0)
+ return OPCODE_ROTW;
+ if (Field_r_Slot_inst_get (insn) == 14)
+ return OPCODE_NSA;
+ if (Field_r_Slot_inst_get (insn) == 15)
+ return OPCODE_NSAU;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 5)
+ {
+ if (Field_r_Slot_inst_get (insn) == 3)
+ return OPCODE_RITLB0;
+ if (Field_r_Slot_inst_get (insn) == 4 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_IITLB;
+ if (Field_r_Slot_inst_get (insn) == 5)
+ return OPCODE_PITLB;
+ if (Field_r_Slot_inst_get (insn) == 6)
+ return OPCODE_WITLB;
+ if (Field_r_Slot_inst_get (insn) == 7)
+ return OPCODE_RITLB1;
+ if (Field_r_Slot_inst_get (insn) == 11)
+ return OPCODE_RDTLB0;
+ if (Field_r_Slot_inst_get (insn) == 12 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_IDTLB;
+ if (Field_r_Slot_inst_get (insn) == 13)
+ return OPCODE_PDTLB;
+ if (Field_r_Slot_inst_get (insn) == 14)
+ return OPCODE_WDTLB;
+ if (Field_r_Slot_inst_get (insn) == 15)
+ return OPCODE_RDTLB1;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 6)
+ {
+ if (Field_s_Slot_inst_get (insn) == 0)
+ return OPCODE_NEG;
+ if (Field_s_Slot_inst_get (insn) == 1)
+ return OPCODE_ABS;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 8)
+ return OPCODE_ADD;
+ if (Field_op2_Slot_inst_get (insn) == 9)
+ return OPCODE_ADDX2;
+ if (Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_ADDX4;
+ if (Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_ADDX8;
+ if (Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_SUB;
+ if (Field_op2_Slot_inst_get (insn) == 13)
+ return OPCODE_SUBX2;
+ if (Field_op2_Slot_inst_get (insn) == 14)
+ return OPCODE_SUBX4;
+ if (Field_op2_Slot_inst_get (insn) == 15)
+ return OPCODE_SUBX8;
+ }
+ if (Field_op1_Slot_inst_get (insn) == 1)
+ {
+ if ((Field_op2_Slot_inst_get (insn) == 0 ||
+ Field_op2_Slot_inst_get (insn) == 1))
+ return OPCODE_SLLI;
+ if ((Field_op2_Slot_inst_get (insn) == 2 ||
+ Field_op2_Slot_inst_get (insn) == 3))
+ return OPCODE_SRAI;
+ if (Field_op2_Slot_inst_get (insn) == 4)
+ return OPCODE_SRLI;
+ if (Field_op2_Slot_inst_get (insn) == 6)
+ {
+ if (Field_sr_Slot_inst_get (insn) == 0)
+ return OPCODE_XSR_LBEG;
+ if (Field_sr_Slot_inst_get (insn) == 1)
+ return OPCODE_XSR_LEND;
+ if (Field_sr_Slot_inst_get (insn) == 2)
+ return OPCODE_XSR_LCOUNT;
+ if (Field_sr_Slot_inst_get (insn) == 3)
+ return OPCODE_XSR_SAR;
+ if (Field_sr_Slot_inst_get (insn) == 5)
+ return OPCODE_XSR_LITBASE;
+ if (Field_sr_Slot_inst_get (insn) == 12)
+ return OPCODE_XSR_SCOMPARE1;
+ if (Field_sr_Slot_inst_get (insn) == 16)
+ return OPCODE_XSR_ACCLO;
+ if (Field_sr_Slot_inst_get (insn) == 17)
+ return OPCODE_XSR_ACCHI;
+ if (Field_sr_Slot_inst_get (insn) == 32)
+ return OPCODE_XSR_M0;
+ if (Field_sr_Slot_inst_get (insn) == 33)
+ return OPCODE_XSR_M1;
+ if (Field_sr_Slot_inst_get (insn) == 34)
+ return OPCODE_XSR_M2;
+ if (Field_sr_Slot_inst_get (insn) == 35)
+ return OPCODE_XSR_M3;
+ if (Field_sr_Slot_inst_get (insn) == 72)
+ return OPCODE_XSR_WINDOWBASE;
+ if (Field_sr_Slot_inst_get (insn) == 73)
+ return OPCODE_XSR_WINDOWSTART;
+ if (Field_sr_Slot_inst_get (insn) == 96)
+ return OPCODE_XSR_IBREAKENABLE;
+ if (Field_sr_Slot_inst_get (insn) == 97)
+ return OPCODE_XSR_MEMCTL;
+ if (Field_sr_Slot_inst_get (insn) == 99)
+ return OPCODE_XSR_ATOMCTL;
+ if (Field_sr_Slot_inst_get (insn) == 104)
+ return OPCODE_XSR_DDR;
+ if (Field_sr_Slot_inst_get (insn) == 128)
+ return OPCODE_XSR_IBREAKA0;
+ if (Field_sr_Slot_inst_get (insn) == 129)
+ return OPCODE_XSR_IBREAKA1;
+ if (Field_sr_Slot_inst_get (insn) == 144)
+ return OPCODE_XSR_DBREAKA0;
+ if (Field_sr_Slot_inst_get (insn) == 145)
+ return OPCODE_XSR_DBREAKA1;
+ if (Field_sr_Slot_inst_get (insn) == 160)
+ return OPCODE_XSR_DBREAKC0;
+ if (Field_sr_Slot_inst_get (insn) == 161)
+ return OPCODE_XSR_DBREAKC1;
+ if (Field_sr_Slot_inst_get (insn) == 177)
+ return OPCODE_XSR_EPC1;
+ if (Field_sr_Slot_inst_get (insn) == 178)
+ return OPCODE_XSR_EPC2;
+ if (Field_sr_Slot_inst_get (insn) == 179)
+ return OPCODE_XSR_EPC3;
+ if (Field_sr_Slot_inst_get (insn) == 180)
+ return OPCODE_XSR_EPC4;
+ if (Field_sr_Slot_inst_get (insn) == 181)
+ return OPCODE_XSR_EPC5;
+ if (Field_sr_Slot_inst_get (insn) == 182)
+ return OPCODE_XSR_EPC6;
+ if (Field_sr_Slot_inst_get (insn) == 183)
+ return OPCODE_XSR_EPC7;
+ if (Field_sr_Slot_inst_get (insn) == 192)
+ return OPCODE_XSR_DEPC;
+ if (Field_sr_Slot_inst_get (insn) == 194)
+ return OPCODE_XSR_EPS2;
+ if (Field_sr_Slot_inst_get (insn) == 195)
+ return OPCODE_XSR_EPS3;
+ if (Field_sr_Slot_inst_get (insn) == 196)
+ return OPCODE_XSR_EPS4;
+ if (Field_sr_Slot_inst_get (insn) == 197)
+ return OPCODE_XSR_EPS5;
+ if (Field_sr_Slot_inst_get (insn) == 198)
+ return OPCODE_XSR_EPS6;
+ if (Field_sr_Slot_inst_get (insn) == 199)
+ return OPCODE_XSR_EPS7;
+ if (Field_sr_Slot_inst_get (insn) == 209)
+ return OPCODE_XSR_EXCSAVE1;
+ if (Field_sr_Slot_inst_get (insn) == 210)
+ return OPCODE_XSR_EXCSAVE2;
+ if (Field_sr_Slot_inst_get (insn) == 211)
+ return OPCODE_XSR_EXCSAVE3;
+ if (Field_sr_Slot_inst_get (insn) == 212)
+ return OPCODE_XSR_EXCSAVE4;
+ if (Field_sr_Slot_inst_get (insn) == 213)
+ return OPCODE_XSR_EXCSAVE5;
+ if (Field_sr_Slot_inst_get (insn) == 214)
+ return OPCODE_XSR_EXCSAVE6;
+ if (Field_sr_Slot_inst_get (insn) == 215)
+ return OPCODE_XSR_EXCSAVE7;
+ if (Field_sr_Slot_inst_get (insn) == 228)
+ return OPCODE_XSR_INTENABLE;
+ if (Field_sr_Slot_inst_get (insn) == 230)
+ return OPCODE_XSR_PS;
+ if (Field_sr_Slot_inst_get (insn) == 231)
+ return OPCODE_XSR_VECBASE;
+ if (Field_sr_Slot_inst_get (insn) == 232)
+ return OPCODE_XSR_EXCCAUSE;
+ if (Field_sr_Slot_inst_get (insn) == 233)
+ return OPCODE_XSR_DEBUGCAUSE;
+ if (Field_sr_Slot_inst_get (insn) == 234)
+ return OPCODE_XSR_CCOUNT;
+ if (Field_sr_Slot_inst_get (insn) == 236)
+ return OPCODE_XSR_ICOUNT;
+ if (Field_sr_Slot_inst_get (insn) == 237)
+ return OPCODE_XSR_ICOUNTLEVEL;
+ if (Field_sr_Slot_inst_get (insn) == 238)
+ return OPCODE_XSR_EXCVADDR;
+ if (Field_sr_Slot_inst_get (insn) == 240)
+ return OPCODE_XSR_CCOMPARE0;
+ if (Field_sr_Slot_inst_get (insn) == 241)
+ return OPCODE_XSR_CCOMPARE1;
+ if (Field_sr_Slot_inst_get (insn) == 242)
+ return OPCODE_XSR_CCOMPARE2;
+ if (Field_sr_Slot_inst_get (insn) == 244)
+ return OPCODE_XSR_MISC0;
+ if (Field_sr_Slot_inst_get (insn) == 245)
+ return OPCODE_XSR_MISC1;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 8)
+ return OPCODE_SRC;
+ if (Field_op2_Slot_inst_get (insn) == 9 &&
+ Field_s_Slot_inst_get (insn) == 0)
+ return OPCODE_SRL;
+ if (Field_op2_Slot_inst_get (insn) == 10 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_SLL;
+ if (Field_op2_Slot_inst_get (insn) == 11 &&
+ Field_s_Slot_inst_get (insn) == 0)
+ return OPCODE_SRA;
+ if (Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_MUL16U;
+ if (Field_op2_Slot_inst_get (insn) == 13)
+ return OPCODE_MUL16S;
+ if (Field_op2_Slot_inst_get (insn) == 15)
+ {
+ if (Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_LICT;
+ if (Field_r_Slot_inst_get (insn) == 1)
+ return OPCODE_SICT;
+ if (Field_r_Slot_inst_get (insn) == 2)
+ return OPCODE_LICW;
+ if (Field_r_Slot_inst_get (insn) == 3)
+ return OPCODE_SICW;
+ if (Field_r_Slot_inst_get (insn) == 8)
+ return OPCODE_LDCT;
+ if (Field_r_Slot_inst_get (insn) == 9)
+ return OPCODE_SDCT;
+ if (Field_r_Slot_inst_get (insn) == 14 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_RFDO;
+ if (Field_r_Slot_inst_get (insn) == 14 &&
+ Field_t_Slot_inst_get (insn) == 1)
+ return OPCODE_RFDD;
+ }
+ }
+ if (Field_op1_Slot_inst_get (insn) == 2)
+ {
+ if (Field_op2_Slot_inst_get (insn) == 8)
+ return OPCODE_MULL;
+ if (Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_QUOU;
+ if (Field_op2_Slot_inst_get (insn) == 13)
+ return OPCODE_QUOS;
+ if (Field_op2_Slot_inst_get (insn) == 14)
+ return OPCODE_REMU;
+ if (Field_op2_Slot_inst_get (insn) == 15)
+ return OPCODE_REMS;
+ }
+ if (Field_op1_Slot_inst_get (insn) == 3)
+ {
+ if (Field_op2_Slot_inst_get (insn) == 0)
+ {
+ if (Field_sr_Slot_inst_get (insn) == 0)
+ return OPCODE_RSR_LBEG;
+ if (Field_sr_Slot_inst_get (insn) == 1)
+ return OPCODE_RSR_LEND;
+ if (Field_sr_Slot_inst_get (insn) == 2)
+ return OPCODE_RSR_LCOUNT;
+ if (Field_sr_Slot_inst_get (insn) == 3)
+ return OPCODE_RSR_SAR;
+ if (Field_sr_Slot_inst_get (insn) == 5)
+ return OPCODE_RSR_LITBASE;
+ if (Field_sr_Slot_inst_get (insn) == 12)
+ return OPCODE_RSR_SCOMPARE1;
+ if (Field_sr_Slot_inst_get (insn) == 16)
+ return OPCODE_RSR_ACCLO;
+ if (Field_sr_Slot_inst_get (insn) == 17)
+ return OPCODE_RSR_ACCHI;
+ if (Field_sr_Slot_inst_get (insn) == 32)
+ return OPCODE_RSR_M0;
+ if (Field_sr_Slot_inst_get (insn) == 33)
+ return OPCODE_RSR_M1;
+ if (Field_sr_Slot_inst_get (insn) == 34)
+ return OPCODE_RSR_M2;
+ if (Field_sr_Slot_inst_get (insn) == 35)
+ return OPCODE_RSR_M3;
+ if (Field_sr_Slot_inst_get (insn) == 72)
+ return OPCODE_RSR_WINDOWBASE;
+ if (Field_sr_Slot_inst_get (insn) == 73)
+ return OPCODE_RSR_WINDOWSTART;
+ if (Field_sr_Slot_inst_get (insn) == 96)
+ return OPCODE_RSR_IBREAKENABLE;
+ if (Field_sr_Slot_inst_get (insn) == 97)
+ return OPCODE_RSR_MEMCTL;
+ if (Field_sr_Slot_inst_get (insn) == 99)
+ return OPCODE_RSR_ATOMCTL;
+ if (Field_sr_Slot_inst_get (insn) == 104)
+ return OPCODE_RSR_DDR;
+ if (Field_sr_Slot_inst_get (insn) == 128)
+ return OPCODE_RSR_IBREAKA0;
+ if (Field_sr_Slot_inst_get (insn) == 129)
+ return OPCODE_RSR_IBREAKA1;
+ if (Field_sr_Slot_inst_get (insn) == 144)
+ return OPCODE_RSR_DBREAKA0;
+ if (Field_sr_Slot_inst_get (insn) == 145)
+ return OPCODE_RSR_DBREAKA1;
+ if (Field_sr_Slot_inst_get (insn) == 160)
+ return OPCODE_RSR_DBREAKC0;
+ if (Field_sr_Slot_inst_get (insn) == 161)
+ return OPCODE_RSR_DBREAKC1;
+ if (Field_sr_Slot_inst_get (insn) == 176)
+ return OPCODE_RSR_CONFIGID0;
+ if (Field_sr_Slot_inst_get (insn) == 177)
+ return OPCODE_RSR_EPC1;
+ if (Field_sr_Slot_inst_get (insn) == 178)
+ return OPCODE_RSR_EPC2;
+ if (Field_sr_Slot_inst_get (insn) == 179)
+ return OPCODE_RSR_EPC3;
+ if (Field_sr_Slot_inst_get (insn) == 180)
+ return OPCODE_RSR_EPC4;
+ if (Field_sr_Slot_inst_get (insn) == 181)
+ return OPCODE_RSR_EPC5;
+ if (Field_sr_Slot_inst_get (insn) == 182)
+ return OPCODE_RSR_EPC6;
+ if (Field_sr_Slot_inst_get (insn) == 183)
+ return OPCODE_RSR_EPC7;
+ if (Field_sr_Slot_inst_get (insn) == 192)
+ return OPCODE_RSR_DEPC;
+ if (Field_sr_Slot_inst_get (insn) == 194)
+ return OPCODE_RSR_EPS2;
+ if (Field_sr_Slot_inst_get (insn) == 195)
+ return OPCODE_RSR_EPS3;
+ if (Field_sr_Slot_inst_get (insn) == 196)
+ return OPCODE_RSR_EPS4;
+ if (Field_sr_Slot_inst_get (insn) == 197)
+ return OPCODE_RSR_EPS5;
+ if (Field_sr_Slot_inst_get (insn) == 198)
+ return OPCODE_RSR_EPS6;
+ if (Field_sr_Slot_inst_get (insn) == 199)
+ return OPCODE_RSR_EPS7;
+ if (Field_sr_Slot_inst_get (insn) == 208)
+ return OPCODE_RSR_CONFIGID1;
+ if (Field_sr_Slot_inst_get (insn) == 209)
+ return OPCODE_RSR_EXCSAVE1;
+ if (Field_sr_Slot_inst_get (insn) == 210)
+ return OPCODE_RSR_EXCSAVE2;
+ if (Field_sr_Slot_inst_get (insn) == 211)
+ return OPCODE_RSR_EXCSAVE3;
+ if (Field_sr_Slot_inst_get (insn) == 212)
+ return OPCODE_RSR_EXCSAVE4;
+ if (Field_sr_Slot_inst_get (insn) == 213)
+ return OPCODE_RSR_EXCSAVE5;
+ if (Field_sr_Slot_inst_get (insn) == 214)
+ return OPCODE_RSR_EXCSAVE6;
+ if (Field_sr_Slot_inst_get (insn) == 215)
+ return OPCODE_RSR_EXCSAVE7;
+ if (Field_sr_Slot_inst_get (insn) == 226)
+ return OPCODE_RSR_INTERRUPT;
+ if (Field_sr_Slot_inst_get (insn) == 228)
+ return OPCODE_RSR_INTENABLE;
+ if (Field_sr_Slot_inst_get (insn) == 230)
+ return OPCODE_RSR_PS;
+ if (Field_sr_Slot_inst_get (insn) == 231)
+ return OPCODE_RSR_VECBASE;
+ if (Field_sr_Slot_inst_get (insn) == 232)
+ return OPCODE_RSR_EXCCAUSE;
+ if (Field_sr_Slot_inst_get (insn) == 233)
+ return OPCODE_RSR_DEBUGCAUSE;
+ if (Field_sr_Slot_inst_get (insn) == 234)
+ return OPCODE_RSR_CCOUNT;
+ if (Field_sr_Slot_inst_get (insn) == 235)
+ return OPCODE_RSR_PRID;
+ if (Field_sr_Slot_inst_get (insn) == 236)
+ return OPCODE_RSR_ICOUNT;
+ if (Field_sr_Slot_inst_get (insn) == 237)
+ return OPCODE_RSR_ICOUNTLEVEL;
+ if (Field_sr_Slot_inst_get (insn) == 238)
+ return OPCODE_RSR_EXCVADDR;
+ if (Field_sr_Slot_inst_get (insn) == 240)
+ return OPCODE_RSR_CCOMPARE0;
+ if (Field_sr_Slot_inst_get (insn) == 241)
+ return OPCODE_RSR_CCOMPARE1;
+ if (Field_sr_Slot_inst_get (insn) == 242)
+ return OPCODE_RSR_CCOMPARE2;
+ if (Field_sr_Slot_inst_get (insn) == 244)
+ return OPCODE_RSR_MISC0;
+ if (Field_sr_Slot_inst_get (insn) == 245)
+ return OPCODE_RSR_MISC1;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 1)
+ {
+ if (Field_sr_Slot_inst_get (insn) == 0)
+ return OPCODE_WSR_LBEG;
+ if (Field_sr_Slot_inst_get (insn) == 1)
+ return OPCODE_WSR_LEND;
+ if (Field_sr_Slot_inst_get (insn) == 2)
+ return OPCODE_WSR_LCOUNT;
+ if (Field_sr_Slot_inst_get (insn) == 3)
+ return OPCODE_WSR_SAR;
+ if (Field_sr_Slot_inst_get (insn) == 5)
+ return OPCODE_WSR_LITBASE;
+ if (Field_sr_Slot_inst_get (insn) == 12)
+ return OPCODE_WSR_SCOMPARE1;
+ if (Field_sr_Slot_inst_get (insn) == 16)
+ return OPCODE_WSR_ACCLO;
+ if (Field_sr_Slot_inst_get (insn) == 17)
+ return OPCODE_WSR_ACCHI;
+ if (Field_sr_Slot_inst_get (insn) == 32)
+ return OPCODE_WSR_M0;
+ if (Field_sr_Slot_inst_get (insn) == 33)
+ return OPCODE_WSR_M1;
+ if (Field_sr_Slot_inst_get (insn) == 34)
+ return OPCODE_WSR_M2;
+ if (Field_sr_Slot_inst_get (insn) == 35)
+ return OPCODE_WSR_M3;
+ if (Field_sr_Slot_inst_get (insn) == 72)
+ return OPCODE_WSR_WINDOWBASE;
+ if (Field_sr_Slot_inst_get (insn) == 73)
+ return OPCODE_WSR_WINDOWSTART;
+ if (Field_sr_Slot_inst_get (insn) == 89)
+ return OPCODE_WSR_MMID;
+ if (Field_sr_Slot_inst_get (insn) == 96)
+ return OPCODE_WSR_IBREAKENABLE;
+ if (Field_sr_Slot_inst_get (insn) == 97)
+ return OPCODE_WSR_MEMCTL;
+ if (Field_sr_Slot_inst_get (insn) == 99)
+ return OPCODE_WSR_ATOMCTL;
+ if (Field_sr_Slot_inst_get (insn) == 104)
+ return OPCODE_WSR_DDR;
+ if (Field_sr_Slot_inst_get (insn) == 128)
+ return OPCODE_WSR_IBREAKA0;
+ if (Field_sr_Slot_inst_get (insn) == 129)
+ return OPCODE_WSR_IBREAKA1;
+ if (Field_sr_Slot_inst_get (insn) == 144)
+ return OPCODE_WSR_DBREAKA0;
+ if (Field_sr_Slot_inst_get (insn) == 145)
+ return OPCODE_WSR_DBREAKA1;
+ if (Field_sr_Slot_inst_get (insn) == 160)
+ return OPCODE_WSR_DBREAKC0;
+ if (Field_sr_Slot_inst_get (insn) == 161)
+ return OPCODE_WSR_DBREAKC1;
+ if (Field_sr_Slot_inst_get (insn) == 176)
+ return OPCODE_WSR_CONFIGID0;
+ if (Field_sr_Slot_inst_get (insn) == 177)
+ return OPCODE_WSR_EPC1;
+ if (Field_sr_Slot_inst_get (insn) == 178)
+ return OPCODE_WSR_EPC2;
+ if (Field_sr_Slot_inst_get (insn) == 179)
+ return OPCODE_WSR_EPC3;
+ if (Field_sr_Slot_inst_get (insn) == 180)
+ return OPCODE_WSR_EPC4;
+ if (Field_sr_Slot_inst_get (insn) == 181)
+ return OPCODE_WSR_EPC5;
+ if (Field_sr_Slot_inst_get (insn) == 182)
+ return OPCODE_WSR_EPC6;
+ if (Field_sr_Slot_inst_get (insn) == 183)
+ return OPCODE_WSR_EPC7;
+ if (Field_sr_Slot_inst_get (insn) == 192)
+ return OPCODE_WSR_DEPC;
+ if (Field_sr_Slot_inst_get (insn) == 194)
+ return OPCODE_WSR_EPS2;
+ if (Field_sr_Slot_inst_get (insn) == 195)
+ return OPCODE_WSR_EPS3;
+ if (Field_sr_Slot_inst_get (insn) == 196)
+ return OPCODE_WSR_EPS4;
+ if (Field_sr_Slot_inst_get (insn) == 197)
+ return OPCODE_WSR_EPS5;
+ if (Field_sr_Slot_inst_get (insn) == 198)
+ return OPCODE_WSR_EPS6;
+ if (Field_sr_Slot_inst_get (insn) == 199)
+ return OPCODE_WSR_EPS7;
+ if (Field_sr_Slot_inst_get (insn) == 209)
+ return OPCODE_WSR_EXCSAVE1;
+ if (Field_sr_Slot_inst_get (insn) == 210)
+ return OPCODE_WSR_EXCSAVE2;
+ if (Field_sr_Slot_inst_get (insn) == 211)
+ return OPCODE_WSR_EXCSAVE3;
+ if (Field_sr_Slot_inst_get (insn) == 212)
+ return OPCODE_WSR_EXCSAVE4;
+ if (Field_sr_Slot_inst_get (insn) == 213)
+ return OPCODE_WSR_EXCSAVE5;
+ if (Field_sr_Slot_inst_get (insn) == 214)
+ return OPCODE_WSR_EXCSAVE6;
+ if (Field_sr_Slot_inst_get (insn) == 215)
+ return OPCODE_WSR_EXCSAVE7;
+ if (Field_sr_Slot_inst_get (insn) == 226)
+ return OPCODE_WSR_INTSET;
+ if (Field_sr_Slot_inst_get (insn) == 227)
+ return OPCODE_WSR_INTCLEAR;
+ if (Field_sr_Slot_inst_get (insn) == 228)
+ return OPCODE_WSR_INTENABLE;
+ if (Field_sr_Slot_inst_get (insn) == 230)
+ return OPCODE_WSR_PS;
+ if (Field_sr_Slot_inst_get (insn) == 231)
+ return OPCODE_WSR_VECBASE;
+ if (Field_sr_Slot_inst_get (insn) == 232)
+ return OPCODE_WSR_EXCCAUSE;
+ if (Field_sr_Slot_inst_get (insn) == 233)
+ return OPCODE_WSR_DEBUGCAUSE;
+ if (Field_sr_Slot_inst_get (insn) == 234)
+ return OPCODE_WSR_CCOUNT;
+ if (Field_sr_Slot_inst_get (insn) == 236)
+ return OPCODE_WSR_ICOUNT;
+ if (Field_sr_Slot_inst_get (insn) == 237)
+ return OPCODE_WSR_ICOUNTLEVEL;
+ if (Field_sr_Slot_inst_get (insn) == 238)
+ return OPCODE_WSR_EXCVADDR;
+ if (Field_sr_Slot_inst_get (insn) == 240)
+ return OPCODE_WSR_CCOMPARE0;
+ if (Field_sr_Slot_inst_get (insn) == 241)
+ return OPCODE_WSR_CCOMPARE1;
+ if (Field_sr_Slot_inst_get (insn) == 242)
+ return OPCODE_WSR_CCOMPARE2;
+ if (Field_sr_Slot_inst_get (insn) == 244)
+ return OPCODE_WSR_MISC0;
+ if (Field_sr_Slot_inst_get (insn) == 245)
+ return OPCODE_WSR_MISC1;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 2)
+ return OPCODE_SEXT;
+ if (Field_op2_Slot_inst_get (insn) == 3)
+ return OPCODE_CLAMPS;
+ if (Field_op2_Slot_inst_get (insn) == 4)
+ return OPCODE_MIN;
+ if (Field_op2_Slot_inst_get (insn) == 5)
+ return OPCODE_MAX;
+ if (Field_op2_Slot_inst_get (insn) == 6)
+ return OPCODE_MINU;
+ if (Field_op2_Slot_inst_get (insn) == 7)
+ return OPCODE_MAXU;
+ if (Field_op2_Slot_inst_get (insn) == 8)
+ return OPCODE_MOVEQZ;
+ if (Field_op2_Slot_inst_get (insn) == 9)
+ return OPCODE_MOVNEZ;
+ if (Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_MOVLTZ;
+ if (Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_MOVGEZ;
+ if (Field_op2_Slot_inst_get (insn) == 14)
+ {
+ if (Field_st_Slot_inst_get (insn) == 230)
+ return OPCODE_RUR_EXPSTATE;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 15)
+ {
+ if (Field_sr_Slot_inst_get (insn) == 230)
+ return OPCODE_WUR_EXPSTATE;
+ }
+ }
+ if ((Field_op1_Slot_inst_get (insn) == 4 ||
+ Field_op1_Slot_inst_get (insn) == 5))
+ return OPCODE_EXTUI;
+ if (Field_op1_Slot_inst_get (insn) == 9)
+ {
+ if (Field_op2_Slot_inst_get (insn) == 0)
+ return OPCODE_L32E;
+ if (Field_op2_Slot_inst_get (insn) == 4)
+ return OPCODE_S32E;
+ if (Field_op2_Slot_inst_get (insn) == 5)
+ return OPCODE_S32NB;
+ }
+ if (Field_r_Slot_inst_get (insn) == 0 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_op2_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 14)
+ return OPCODE_READ_IMPWIRE;
+ if (Field_r_Slot_inst_get (insn) == 1 &&
+ Field_s3to1_Slot_inst_get (insn) == 0 &&
+ Field_op2_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 14)
+ return OPCODE_SETB_EXPSTATE;
+ if (Field_r_Slot_inst_get (insn) == 1 &&
+ Field_s3to1_Slot_inst_get (insn) == 1 &&
+ Field_op2_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 14)
+ return OPCODE_CLRB_EXPSTATE;
+ if (Field_r_Slot_inst_get (insn) == 2 &&
+ Field_op2_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 14)
+ return OPCODE_WRMSK_EXPSTATE;
+ }
+ if (Field_op0_Slot_inst_get (insn) == 1)
+ return OPCODE_L32R;
+ if (Field_op0_Slot_inst_get (insn) == 2)
+ {
+ if (Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_L8UI;
+ if (Field_r_Slot_inst_get (insn) == 1)
+ return OPCODE_L16UI;
+ if (Field_r_Slot_inst_get (insn) == 2)
+ return OPCODE_L32I;
+ if (Field_r_Slot_inst_get (insn) == 4)
+ return OPCODE_S8I;
+ if (Field_r_Slot_inst_get (insn) == 5)
+ return OPCODE_S16I;
+ if (Field_r_Slot_inst_get (insn) == 6)
+ return OPCODE_S32I;
+ if (Field_r_Slot_inst_get (insn) == 7)
+ {
+ if (Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_DPFR;
+ if (Field_t_Slot_inst_get (insn) == 1)
+ return OPCODE_DPFW;
+ if (Field_t_Slot_inst_get (insn) == 2)
+ return OPCODE_DPFRO;
+ if (Field_t_Slot_inst_get (insn) == 3)
+ return OPCODE_DPFWO;
+ if (Field_t_Slot_inst_get (insn) == 4)
+ return OPCODE_DHWB;
+ if (Field_t_Slot_inst_get (insn) == 5)
+ return OPCODE_DHWBI;
+ if (Field_t_Slot_inst_get (insn) == 6)
+ return OPCODE_DHI;
+ if (Field_t_Slot_inst_get (insn) == 7)
+ return OPCODE_DII;
+ if (Field_t_Slot_inst_get (insn) == 8)
+ {
+ if (Field_op1_Slot_inst_get (insn) == 0)
+ return OPCODE_DPFL;
+ if (Field_op1_Slot_inst_get (insn) == 2)
+ return OPCODE_DHU;
+ if (Field_op1_Slot_inst_get (insn) == 3)
+ return OPCODE_DIU;
+ if (Field_op1_Slot_inst_get (insn) == 4)
+ return OPCODE_DIWB;
+ if (Field_op1_Slot_inst_get (insn) == 5)
+ return OPCODE_DIWBI;
+ if (Field_op1_Slot_inst_get (insn) == 15 &&
+ Field_op2_Slot_inst_get (insn) == 0)
+ return OPCODE_DIWBUI_P;
+ }
+ if (Field_t_Slot_inst_get (insn) == 12)
+ return OPCODE_IPF;
+ if (Field_t_Slot_inst_get (insn) == 13)
+ {
+ if (Field_op1_Slot_inst_get (insn) == 0)
+ return OPCODE_IPFL;
+ if (Field_op1_Slot_inst_get (insn) == 2)
+ return OPCODE_IHU;
+ if (Field_op1_Slot_inst_get (insn) == 3)
+ return OPCODE_IIU;
+ }
+ if (Field_t_Slot_inst_get (insn) == 14)
+ return OPCODE_IHI;
+ if (Field_t_Slot_inst_get (insn) == 15)
+ return OPCODE_III;
+ }
+ if (Field_r_Slot_inst_get (insn) == 9)
+ return OPCODE_L16SI;
+ if (Field_r_Slot_inst_get (insn) == 10)
+ return OPCODE_MOVI;
+ if (Field_r_Slot_inst_get (insn) == 11)
+ return OPCODE_L32AI;
+ if (Field_r_Slot_inst_get (insn) == 12)
+ return OPCODE_ADDI;
+ if (Field_r_Slot_inst_get (insn) == 13)
+ return OPCODE_ADDMI;
+ if (Field_r_Slot_inst_get (insn) == 14)
+ return OPCODE_S32C1I;
+ if (Field_r_Slot_inst_get (insn) == 15)
+ return OPCODE_S32RI;
+ }
+ if (Field_op0_Slot_inst_get (insn) == 4)
+ {
+ if (Field_op2_Slot_inst_get (insn) == 0)
+ {
+ if (Field_op1_Slot_inst_get (insn) == 8 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DD_LL_LDINC;
+ if (Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DD_HL_LDINC;
+ if (Field_op1_Slot_inst_get (insn) == 10 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DD_LH_LDINC;
+ if (Field_op1_Slot_inst_get (insn) == 11 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DD_HH_LDINC;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 1)
+ {
+ if (Field_op1_Slot_inst_get (insn) == 8 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DD_LL_LDDEC;
+ if (Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DD_HL_LDDEC;
+ if (Field_op1_Slot_inst_get (insn) == 10 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DD_LH_LDDEC;
+ if (Field_op1_Slot_inst_get (insn) == 11 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DD_HH_LDDEC;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 2)
+ {
+ if (Field_op1_Slot_inst_get (insn) == 4 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_DD_LL;
+ if (Field_op1_Slot_inst_get (insn) == 5 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_DD_HL;
+ if (Field_op1_Slot_inst_get (insn) == 6 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_DD_LH;
+ if (Field_op1_Slot_inst_get (insn) == 7 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_DD_HH;
+ if (Field_op1_Slot_inst_get (insn) == 8 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DD_LL;
+ if (Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DD_HL;
+ if (Field_op1_Slot_inst_get (insn) == 10 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DD_LH;
+ if (Field_op1_Slot_inst_get (insn) == 11 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DD_HH;
+ if (Field_op1_Slot_inst_get (insn) == 12 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_DD_LL;
+ if (Field_op1_Slot_inst_get (insn) == 13 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_DD_HL;
+ if (Field_op1_Slot_inst_get (insn) == 14 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_DD_LH;
+ if (Field_op1_Slot_inst_get (insn) == 15 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_DD_HH;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 3)
+ {
+ if (Field_op1_Slot_inst_get (insn) == 4 &&
+ Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_AD_LL;
+ if (Field_op1_Slot_inst_get (insn) == 5 &&
+ Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_AD_HL;
+ if (Field_op1_Slot_inst_get (insn) == 6 &&
+ Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_AD_LH;
+ if (Field_op1_Slot_inst_get (insn) == 7 &&
+ Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_AD_HH;
+ if (Field_op1_Slot_inst_get (insn) == 8 &&
+ Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_AD_LL;
+ if (Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_AD_HL;
+ if (Field_op1_Slot_inst_get (insn) == 10 &&
+ Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_AD_LH;
+ if (Field_op1_Slot_inst_get (insn) == 11 &&
+ Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_AD_HH;
+ if (Field_op1_Slot_inst_get (insn) == 12 &&
+ Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_AD_LL;
+ if (Field_op1_Slot_inst_get (insn) == 13 &&
+ Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_AD_HL;
+ if (Field_op1_Slot_inst_get (insn) == 14 &&
+ Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_AD_LH;
+ if (Field_op1_Slot_inst_get (insn) == 15 &&
+ Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_AD_HH;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 4)
+ {
+ if (Field_op1_Slot_inst_get (insn) == 8 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DA_LL_LDINC;
+ if (Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DA_HL_LDINC;
+ if (Field_op1_Slot_inst_get (insn) == 10 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DA_LH_LDINC;
+ if (Field_op1_Slot_inst_get (insn) == 11 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DA_HH_LDINC;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 5)
+ {
+ if (Field_op1_Slot_inst_get (insn) == 8 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DA_LL_LDDEC;
+ if (Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DA_HL_LDDEC;
+ if (Field_op1_Slot_inst_get (insn) == 10 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DA_LH_LDDEC;
+ if (Field_op1_Slot_inst_get (insn) == 11 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DA_HH_LDDEC;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 6)
+ {
+ if (Field_op1_Slot_inst_get (insn) == 4 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_DA_LL;
+ if (Field_op1_Slot_inst_get (insn) == 5 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_DA_HL;
+ if (Field_op1_Slot_inst_get (insn) == 6 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_DA_LH;
+ if (Field_op1_Slot_inst_get (insn) == 7 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_DA_HH;
+ if (Field_op1_Slot_inst_get (insn) == 8 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DA_LL;
+ if (Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DA_HL;
+ if (Field_op1_Slot_inst_get (insn) == 10 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DA_LH;
+ if (Field_op1_Slot_inst_get (insn) == 11 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DA_HH;
+ if (Field_op1_Slot_inst_get (insn) == 12 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_DA_LL;
+ if (Field_op1_Slot_inst_get (insn) == 13 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_DA_HL;
+ if (Field_op1_Slot_inst_get (insn) == 14 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_DA_LH;
+ if (Field_op1_Slot_inst_get (insn) == 15 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_DA_HH;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 7)
+ {
+ if (Field_op1_Slot_inst_get (insn) == 0 &&
+ Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_UMUL_AA_LL;
+ if (Field_op1_Slot_inst_get (insn) == 1 &&
+ Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_UMUL_AA_HL;
+ if (Field_op1_Slot_inst_get (insn) == 2 &&
+ Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_UMUL_AA_LH;
+ if (Field_op1_Slot_inst_get (insn) == 3 &&
+ Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_UMUL_AA_HH;
+ if (Field_op1_Slot_inst_get (insn) == 4 &&
+ Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_AA_LL;
+ if (Field_op1_Slot_inst_get (insn) == 5 &&
+ Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_AA_HL;
+ if (Field_op1_Slot_inst_get (insn) == 6 &&
+ Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_AA_LH;
+ if (Field_op1_Slot_inst_get (insn) == 7 &&
+ Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_AA_HH;
+ if (Field_op1_Slot_inst_get (insn) == 8 &&
+ Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_AA_LL;
+ if (Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_AA_HL;
+ if (Field_op1_Slot_inst_get (insn) == 10 &&
+ Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_AA_LH;
+ if (Field_op1_Slot_inst_get (insn) == 11 &&
+ Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_AA_HH;
+ if (Field_op1_Slot_inst_get (insn) == 12 &&
+ Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_AA_LL;
+ if (Field_op1_Slot_inst_get (insn) == 13 &&
+ Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_AA_HL;
+ if (Field_op1_Slot_inst_get (insn) == 14 &&
+ Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_AA_LH;
+ if (Field_op1_Slot_inst_get (insn) == 15 &&
+ Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_AA_HH;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 8)
+ {
+ if (Field_op1_Slot_inst_get (insn) == 0 &&
+ Field_t_Slot_inst_get (insn) == 0 &&
+ Field_rhi_Slot_inst_get (insn) == 0)
+ return OPCODE_LDINC;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 9)
+ {
+ if (Field_op1_Slot_inst_get (insn) == 0 &&
+ Field_t_Slot_inst_get (insn) == 0 &&
+ Field_rhi_Slot_inst_get (insn) == 0)
+ return OPCODE_LDDEC;
+ }
+ }
+ if (Field_op0_Slot_inst_get (insn) == 5)
+ {
+ if (Field_n_Slot_inst_get (insn) == 0)
+ return OPCODE_CALL0;
+ if (Field_n_Slot_inst_get (insn) == 1)
+ return OPCODE_CALL4;
+ if (Field_n_Slot_inst_get (insn) == 2)
+ return OPCODE_CALL8;
+ if (Field_n_Slot_inst_get (insn) == 3)
+ return OPCODE_CALL12;
+ }
+ if (Field_op0_Slot_inst_get (insn) == 6)
+ {
+ if (Field_n_Slot_inst_get (insn) == 0)
+ return OPCODE_J;
+ if (Field_n_Slot_inst_get (insn) == 1)
+ {
+ if (Field_m_Slot_inst_get (insn) == 0)
+ return OPCODE_BEQZ;
+ if (Field_m_Slot_inst_get (insn) == 1)
+ return OPCODE_BNEZ;
+ if (Field_m_Slot_inst_get (insn) == 2)
+ return OPCODE_BLTZ;
+ if (Field_m_Slot_inst_get (insn) == 3)
+ return OPCODE_BGEZ;
+ }
+ if (Field_n_Slot_inst_get (insn) == 2)
+ {
+ if (Field_m_Slot_inst_get (insn) == 0)
+ return OPCODE_BEQI;
+ if (Field_m_Slot_inst_get (insn) == 1)
+ return OPCODE_BNEI;
+ if (Field_m_Slot_inst_get (insn) == 2)
+ return OPCODE_BLTI;
+ if (Field_m_Slot_inst_get (insn) == 3)
+ return OPCODE_BGEI;
+ }
+ if (Field_n_Slot_inst_get (insn) == 3)
+ {
+ if (Field_m_Slot_inst_get (insn) == 0)
+ return OPCODE_ENTRY;
+ if (Field_m_Slot_inst_get (insn) == 1)
+ {
+ if (Field_r_Slot_inst_get (insn) == 8)
+ return OPCODE_LOOP;
+ if (Field_r_Slot_inst_get (insn) == 9)
+ return OPCODE_LOOPNEZ;
+ if (Field_r_Slot_inst_get (insn) == 10)
+ return OPCODE_LOOPGTZ;
+ }
+ if (Field_m_Slot_inst_get (insn) == 2)
+ return OPCODE_BLTUI;
+ if (Field_m_Slot_inst_get (insn) == 3)
+ return OPCODE_BGEUI;
+ }
+ }
+ if (Field_op0_Slot_inst_get (insn) == 7)
+ {
+ if (Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_BNONE;
+ if (Field_r_Slot_inst_get (insn) == 1)
+ return OPCODE_BEQ;
+ if (Field_r_Slot_inst_get (insn) == 2)
+ return OPCODE_BLT;
+ if (Field_r_Slot_inst_get (insn) == 3)
+ return OPCODE_BLTU;
+ if (Field_r_Slot_inst_get (insn) == 4)
+ return OPCODE_BALL;
+ if (Field_r_Slot_inst_get (insn) == 5)
+ return OPCODE_BBC;
+ if ((Field_r_Slot_inst_get (insn) == 6 ||
+ Field_r_Slot_inst_get (insn) == 7))
+ return OPCODE_BBCI;
+ if (Field_r_Slot_inst_get (insn) == 8)
+ return OPCODE_BANY;
+ if (Field_r_Slot_inst_get (insn) == 9)
+ return OPCODE_BNE;
+ if (Field_r_Slot_inst_get (insn) == 10)
+ return OPCODE_BGE;
+ if (Field_r_Slot_inst_get (insn) == 11)
+ return OPCODE_BGEU;
+ if (Field_r_Slot_inst_get (insn) == 12)
+ return OPCODE_BNALL;
+ if (Field_r_Slot_inst_get (insn) == 13)
+ return OPCODE_BBS;
+ if ((Field_r_Slot_inst_get (insn) == 14 ||
+ Field_r_Slot_inst_get (insn) == 15))
+ return OPCODE_BBSI;
+ }
+ return XTENSA_UNDEFINED;
+}
+
+static int
+Slot_inst16b_decode (const xtensa_insnbuf insn)
+{
+ if (Field_op0_Slot_inst16b_get (insn) == 12)
+ {
+ if (Field_i_Slot_inst16b_get (insn) == 0)
+ return OPCODE_MOVI_N;
+ if (Field_i_Slot_inst16b_get (insn) == 1)
+ {
+ if (Field_z_Slot_inst16b_get (insn) == 0)
+ return OPCODE_BEQZ_N;
+ if (Field_z_Slot_inst16b_get (insn) == 1)
+ return OPCODE_BNEZ_N;
+ }
+ }
+ if (Field_op0_Slot_inst16b_get (insn) == 13)
+ {
+ if (Field_r_Slot_inst16b_get (insn) == 0)
+ return OPCODE_MOV_N;
+ if (Field_r_Slot_inst16b_get (insn) == 15)
+ {
+ if (Field_t_Slot_inst16b_get (insn) == 0)
+ return OPCODE_RET_N;
+ if (Field_t_Slot_inst16b_get (insn) == 1)
+ return OPCODE_RETW_N;
+ if (Field_t_Slot_inst16b_get (insn) == 2)
+ return OPCODE_BREAK_N;
+ if (Field_t_Slot_inst16b_get (insn) == 3 &&
+ Field_s_Slot_inst16b_get (insn) == 0)
+ return OPCODE_NOP_N;
+ if (Field_t_Slot_inst16b_get (insn) == 6 &&
+ Field_s_Slot_inst16b_get (insn) == 0)
+ return OPCODE_ILL_N;
+ }
+ }
+ return XTENSA_UNDEFINED;
+}
+
+static int
+Slot_inst16a_decode (const xtensa_insnbuf insn)
+{
+ if (Field_op0_Slot_inst16a_get (insn) == 8)
+ return OPCODE_L32I_N;
+ if (Field_op0_Slot_inst16a_get (insn) == 9)
+ return OPCODE_S32I_N;
+ if (Field_op0_Slot_inst16a_get (insn) == 10)
+ return OPCODE_ADD_N;
+ if (Field_op0_Slot_inst16a_get (insn) == 11)
+ return OPCODE_ADDI_N;
+ return XTENSA_UNDEFINED;
+}
+
+
+/* Instruction slots. */
+
+static void
+Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn,
+ xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = (insn[0] & 0xffffff);
+}
+
+static void
+Slot_x24_Format_inst_0_set (xtensa_insnbuf insn,
+ const xtensa_insnbuf slotbuf)
+{
+ insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff);
+}
+
+static void
+Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn,
+ xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = (insn[0] & 0xffff);
+}
+
+static void
+Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn,
+ const xtensa_insnbuf slotbuf)
+{
+ insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
+}
+
+static void
+Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn,
+ xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = (insn[0] & 0xffff);
+}
+
+static void
+Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn,
+ const xtensa_insnbuf slotbuf)
+{
+ insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
+}
+
+static xtensa_get_field_fn
+Slot_inst_get_field_fns[] = {
+ Field_t_Slot_inst_get,
+ Field_bbi4_Slot_inst_get,
+ Field_bbi_Slot_inst_get,
+ Field_imm12_Slot_inst_get,
+ Field_imm8_Slot_inst_get,
+ Field_s_Slot_inst_get,
+ Field_imm12b_Slot_inst_get,
+ Field_imm16_Slot_inst_get,
+ Field_m_Slot_inst_get,
+ Field_n_Slot_inst_get,
+ Field_offset_Slot_inst_get,
+ Field_op0_Slot_inst_get,
+ Field_op1_Slot_inst_get,
+ Field_op2_Slot_inst_get,
+ Field_r_Slot_inst_get,
+ Field_sa4_Slot_inst_get,
+ Field_sae4_Slot_inst_get,
+ Field_sae_Slot_inst_get,
+ Field_sal_Slot_inst_get,
+ Field_sargt_Slot_inst_get,
+ Field_sas4_Slot_inst_get,
+ Field_sas_Slot_inst_get,
+ Field_sr_Slot_inst_get,
+ Field_st_Slot_inst_get,
+ Field_thi3_Slot_inst_get,
+ Field_imm4_Slot_inst_get,
+ Field_mn_Slot_inst_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_r3_Slot_inst_get,
+ Field_rbit2_Slot_inst_get,
+ Field_rhi_Slot_inst_get,
+ Field_t3_Slot_inst_get,
+ Field_tbit2_Slot_inst_get,
+ Field_tlo_Slot_inst_get,
+ Field_w_Slot_inst_get,
+ Field_y_Slot_inst_get,
+ Field_x_Slot_inst_get,
+ Field_xt_wbr15_imm_Slot_inst_get,
+ Field_xt_wbr18_imm_Slot_inst_get,
+ Field_bitindex_Slot_inst_get,
+ Field_s3to1_Slot_inst_get,
+ Implicit_Field_ar0_get,
+ Implicit_Field_ar4_get,
+ Implicit_Field_ar8_get,
+ Implicit_Field_ar12_get,
+ Implicit_Field_mr0_get,
+ Implicit_Field_mr1_get,
+ Implicit_Field_mr2_get,
+ Implicit_Field_mr3_get
+};
+
+static xtensa_set_field_fn
+Slot_inst_set_field_fns[] = {
+ Field_t_Slot_inst_set,
+ Field_bbi4_Slot_inst_set,
+ Field_bbi_Slot_inst_set,
+ Field_imm12_Slot_inst_set,
+ Field_imm8_Slot_inst_set,
+ Field_s_Slot_inst_set,
+ Field_imm12b_Slot_inst_set,
+ Field_imm16_Slot_inst_set,
+ Field_m_Slot_inst_set,
+ Field_n_Slot_inst_set,
+ Field_offset_Slot_inst_set,
+ Field_op0_Slot_inst_set,
+ Field_op1_Slot_inst_set,
+ Field_op2_Slot_inst_set,
+ Field_r_Slot_inst_set,
+ Field_sa4_Slot_inst_set,
+ Field_sae4_Slot_inst_set,
+ Field_sae_Slot_inst_set,
+ Field_sal_Slot_inst_set,
+ Field_sargt_Slot_inst_set,
+ Field_sas4_Slot_inst_set,
+ Field_sas_Slot_inst_set,
+ Field_sr_Slot_inst_set,
+ Field_st_Slot_inst_set,
+ Field_thi3_Slot_inst_set,
+ Field_imm4_Slot_inst_set,
+ Field_mn_Slot_inst_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_r3_Slot_inst_set,
+ Field_rbit2_Slot_inst_set,
+ Field_rhi_Slot_inst_set,
+ Field_t3_Slot_inst_set,
+ Field_tbit2_Slot_inst_set,
+ Field_tlo_Slot_inst_set,
+ Field_w_Slot_inst_set,
+ Field_y_Slot_inst_set,
+ Field_x_Slot_inst_set,
+ Field_xt_wbr15_imm_Slot_inst_set,
+ Field_xt_wbr18_imm_Slot_inst_set,
+ Field_bitindex_Slot_inst_set,
+ Field_s3to1_Slot_inst_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set
+};
+
+static xtensa_get_field_fn
+Slot_inst16a_get_field_fns[] = {
+ Field_t_Slot_inst16a_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_s_Slot_inst16a_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_op0_Slot_inst16a_get,
+ 0,
+ 0,
+ Field_r_Slot_inst16a_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_sr_Slot_inst16a_get,
+ Field_st_Slot_inst16a_get,
+ 0,
+ Field_imm4_Slot_inst16a_get,
+ 0,
+ Field_i_Slot_inst16a_get,
+ Field_imm6lo_Slot_inst16a_get,
+ Field_imm6hi_Slot_inst16a_get,
+ Field_imm7lo_Slot_inst16a_get,
+ Field_imm7hi_Slot_inst16a_get,
+ Field_z_Slot_inst16a_get,
+ Field_imm6_Slot_inst16a_get,
+ Field_imm7_Slot_inst16a_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_bitindex_Slot_inst16a_get,
+ Field_s3to1_Slot_inst16a_get,
+ Implicit_Field_ar0_get,
+ Implicit_Field_ar4_get,
+ Implicit_Field_ar8_get,
+ Implicit_Field_ar12_get,
+ Implicit_Field_mr0_get,
+ Implicit_Field_mr1_get,
+ Implicit_Field_mr2_get,
+ Implicit_Field_mr3_get
+};
+
+static xtensa_set_field_fn
+Slot_inst16a_set_field_fns[] = {
+ Field_t_Slot_inst16a_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_s_Slot_inst16a_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_op0_Slot_inst16a_set,
+ 0,
+ 0,
+ Field_r_Slot_inst16a_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_sr_Slot_inst16a_set,
+ Field_st_Slot_inst16a_set,
+ 0,
+ Field_imm4_Slot_inst16a_set,
+ 0,
+ Field_i_Slot_inst16a_set,
+ Field_imm6lo_Slot_inst16a_set,
+ Field_imm6hi_Slot_inst16a_set,
+ Field_imm7lo_Slot_inst16a_set,
+ Field_imm7hi_Slot_inst16a_set,
+ Field_z_Slot_inst16a_set,
+ Field_imm6_Slot_inst16a_set,
+ Field_imm7_Slot_inst16a_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_bitindex_Slot_inst16a_set,
+ Field_s3to1_Slot_inst16a_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set
+};
+
+static xtensa_get_field_fn
+Slot_inst16b_get_field_fns[] = {
+ Field_t_Slot_inst16b_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_s_Slot_inst16b_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_op0_Slot_inst16b_get,
+ 0,
+ 0,
+ Field_r_Slot_inst16b_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_sr_Slot_inst16b_get,
+ Field_st_Slot_inst16b_get,
+ 0,
+ Field_imm4_Slot_inst16b_get,
+ 0,
+ Field_i_Slot_inst16b_get,
+ Field_imm6lo_Slot_inst16b_get,
+ Field_imm6hi_Slot_inst16b_get,
+ Field_imm7lo_Slot_inst16b_get,
+ Field_imm7hi_Slot_inst16b_get,
+ Field_z_Slot_inst16b_get,
+ Field_imm6_Slot_inst16b_get,
+ Field_imm7_Slot_inst16b_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_bitindex_Slot_inst16b_get,
+ Field_s3to1_Slot_inst16b_get,
+ Implicit_Field_ar0_get,
+ Implicit_Field_ar4_get,
+ Implicit_Field_ar8_get,
+ Implicit_Field_ar12_get,
+ Implicit_Field_mr0_get,
+ Implicit_Field_mr1_get,
+ Implicit_Field_mr2_get,
+ Implicit_Field_mr3_get
+};
+
+static xtensa_set_field_fn
+Slot_inst16b_set_field_fns[] = {
+ Field_t_Slot_inst16b_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_s_Slot_inst16b_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_op0_Slot_inst16b_set,
+ 0,
+ 0,
+ Field_r_Slot_inst16b_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_sr_Slot_inst16b_set,
+ Field_st_Slot_inst16b_set,
+ 0,
+ Field_imm4_Slot_inst16b_set,
+ 0,
+ Field_i_Slot_inst16b_set,
+ Field_imm6lo_Slot_inst16b_set,
+ Field_imm6hi_Slot_inst16b_set,
+ Field_imm7lo_Slot_inst16b_set,
+ Field_imm7hi_Slot_inst16b_set,
+ Field_z_Slot_inst16b_set,
+ Field_imm6_Slot_inst16b_set,
+ Field_imm7_Slot_inst16b_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_bitindex_Slot_inst16b_set,
+ Field_s3to1_Slot_inst16b_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set
+};
+
+static xtensa_slot_internal slots[] = {
+ { "Inst", "x24", 0,
+ Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set,
+ Slot_inst_get_field_fns, Slot_inst_set_field_fns,
+ Slot_inst_decode, "nop" },
+ { "Inst16a", "x16a", 0,
+ Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set,
+ Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns,
+ Slot_inst16a_decode, "" },
+ { "Inst16b", "x16b", 0,
+ Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set,
+ Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns,
+ Slot_inst16b_decode, "nop.n" }
+};
+
+
+/* Instruction formats. */
+
+static void
+Format_x24_encode (xtensa_insnbuf insn)
+{
+ insn[0] = 0;
+}
+
+static void
+Format_x16a_encode (xtensa_insnbuf insn)
+{
+ insn[0] = 0x8;
+}
+
+static void
+Format_x16b_encode (xtensa_insnbuf insn)
+{
+ insn[0] = 0xc;
+}
+
+static int Format_x24_slots[] = { 0 };
+
+static int Format_x16a_slots[] = { 1 };
+
+static int Format_x16b_slots[] = { 2 };
+
+static xtensa_format_internal formats[] = {
+ { "x24", 3, Format_x24_encode, 1, Format_x24_slots },
+ { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots },
+ { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots }
+};
+
+
+static int
+format_decoder (const xtensa_insnbuf insn)
+{
+ if ((insn[0] & 0x8) == 0)
+ return 0; /* x24 */
+ if ((insn[0] & 0xc) == 0x8)
+ return 1; /* x16a */
+ if ((insn[0] & 0xe) == 0xc)
+ return 2; /* x16b */
+ return -1;
+}
+
+static int length_table[256] = {
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1
+};
+
+static int
+length_decoder (const unsigned char *insn)
+{
+ int l = insn[0];
+ return length_table[l];
+}
+
+
+/* Top-level ISA structure. */
+
+xtensa_isa_internal xtensa_modules = {
+ 0 /* little-endian */,
+ 3 /* insn_size */, 0,
+ 3, formats, format_decoder, length_decoder,
+ 3, slots,
+ 56 /* num_fields */,
+ 94, operands,
+ 313, iclasses,
+ 439, opcodes, 0,
+ 2, regfiles,
+ NUM_STATES, states, 0,
+ NUM_SYSREGS, sysregs, 0,
+ { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 },
+ 6, interfaces, 0,
+ 0, funcUnits, 0
+};
diff --git a/target/xtensa/core-sample_controller.c b/target/xtensa/core-sample_controller.c
new file mode 100644
index 0000000..879e853
--- /dev/null
+++ b/target/xtensa/core-sample_controller.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2018, Max Filippov, Open Source and Linux Lab.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the Open Source and Linux Lab nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "exec/exec-all.h"
+#include "exec/gdbstub.h"
+#include "qemu-common.h"
+#include "qemu/host-utils.h"
+
+#include "core-sample_controller/core-isa.h"
+#include "overlay_tool.h"
+
+#define xtensa_modules xtensa_modules_sample_controller
+#include "core-sample_controller/xtensa-modules.c"
+
+static XtensaConfig sample_controller __attribute__((unused)) = {
+ .name = "sample_controller",
+ .gdb_regmap = {
+ .reg = {
+#include "core-sample_controller/gdb-config.c"
+ }
+ },
+ .isa_internal = &xtensa_modules,
+ .clock_freq_khz = 10000,
+ DEFAULT_SECTIONS
+};
+
+REGISTER_CORE(sample_controller)
diff --git a/target/xtensa/core-sample_controller/core-isa.h b/target/xtensa/core-sample_controller/core-isa.h
new file mode 100644
index 0000000..e681e43
--- /dev/null
+++ b/target/xtensa/core-sample_controller/core-isa.h
@@ -0,0 +1,644 @@
+/*
+ * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
+ * processor CORE configuration
+ *
+ * See <xtensa/config/core.h>, which includes this file, for more details.
+ */
+
+/* Xtensa processor core configuration information.
+
+ Copyright (c) 1999-2016 Tensilica Inc.
+
+ Permission is hereby granted, free of charge, to any person obtaining
+ a copy of this software and associated documentation files (the
+ "Software"), to deal in the Software without restriction, including
+ without limitation the rights to use, copy, modify, merge, publish,
+ distribute, sublicense, and/or sell copies of the Software, and to
+ permit persons to whom the Software is furnished to do so, subject to
+ the following conditions:
+
+ The above copyright notice and this permission notice shall be included
+ in all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+#ifndef _XTENSA_CORE_CONFIGURATION_H
+#define _XTENSA_CORE_CONFIGURATION_H
+
+
+/****************************************************************************
+ Parameters Useful for Any Code, USER or PRIVILEGED
+ ****************************************************************************/
+
+/*
+ * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
+ * configured, and a value of 0 otherwise. These macros are always defined.
+ */
+
+
+/*----------------------------------------------------------------------
+ ISA
+ ----------------------------------------------------------------------*/
+
+#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
+#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
+#define XCHAL_NUM_AREGS 32 /* num of physical addr regs */
+#define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */
+#define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */
+#define XCHAL_HAVE_DEBUG 1 /* debug option */
+#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
+#define XCHAL_HAVE_LOOPS 0 /* zero-overhead loops */
+#define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */
+#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
+#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
+#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
+#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */
+#define XCHAL_HAVE_CLAMPS 0 /* CLAMPS instruction */
+#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
+#define XCHAL_HAVE_MUL32 1 /* MULL instruction */
+#define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */
+#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */
+#define XCHAL_HAVE_L32R 1 /* L32R instruction */
+#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */
+#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
+#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
+#define XCHAL_HAVE_EXCLUSIVE 0 /* L32EX/S32EX instructions */
+#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
+#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
+#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
+#define XCHAL_HAVE_ABS 1 /* ABS instruction */
+/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */
+/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */
+#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */
+#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */
+#define XCHAL_HAVE_SPECULATION 0 /* speculation */
+#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */
+#define XCHAL_NUM_CONTEXTS 1 /* */
+#define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */
+#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
+#define XCHAL_HAVE_PRID 1 /* processor ID register */
+#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */
+#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */
+#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */
+#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */
+#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */
+#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */
+#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */
+#define XCHAL_HAVE_THREADPTR 0 /* THREADPTR register */
+#define XCHAL_HAVE_BOOLEANS 0 /* boolean registers */
+#define XCHAL_HAVE_CP 0 /* CPENABLE reg (coprocessor) */
+#define XCHAL_CP_MAXCFG 0 /* max allowed cp id plus one */
+#define XCHAL_HAVE_MAC16 0 /* MAC16 package */
+
+#define XCHAL_HAVE_FUSION 0 /* Fusion*/
+#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */
+#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */
+#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */
+#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */
+#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */
+#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */
+#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */
+#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */
+#define XCHAL_HAVE_FUSION_VITERBI 0 /* Fusion Viterbi option */
+#define XCHAL_HAVE_FUSION_SOFTDEMAP 0 /* Fusion Soft Bit Demap option */
+#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */
+#define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */
+#define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */
+#define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */
+#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */
+#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */
+#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */
+#define XCHAL_HAVE_HIFI_MINI 0
+
+
+
+#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
+#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */
+#define XCHAL_HAVE_USER_SPFPU 0 /* user DP floating-point pkg */
+#define XCHAL_HAVE_FP 0 /* single prec floating point */
+#define XCHAL_HAVE_FP_DIV 0 /* FP with DIV instructions */
+#define XCHAL_HAVE_FP_RECIP 0 /* FP with RECIP instructions */
+#define XCHAL_HAVE_FP_SQRT 0 /* FP with SQRT instructions */
+#define XCHAL_HAVE_FP_RSQRT 0 /* FP with RSQRT instructions */
+#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */
+#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */
+#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/
+#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */
+#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/
+#define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */
+#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */
+
+#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */
+#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */
+#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
+#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
+
+#define XCHAL_HAVE_FUSIONG 0 /* FusionG */
+#define XCHAL_HAVE_FUSIONG3 0 /* FusionG3 */
+#define XCHAL_HAVE_FUSIONG_SP_VFPU 0 /* sp_vfpu option on FusionG */
+#define XCHAL_HAVE_FUSIONG_DP_VFPU 0 /* dp_vfpu option on FusionG */
+#define XCHAL_FUSIONG_SIMD32 0 /* simd32 for FusionG */
+
+#define XCHAL_HAVE_PDX 0 /* PDX */
+#define XCHAL_PDX_SIMD32 0 /* simd32 for PDX */
+#define XCHAL_HAVE_PDX4 0 /* PDX4 */
+#define XCHAL_HAVE_PDX8 0 /* PDX8 */
+#define XCHAL_HAVE_PDX16 0 /* PDX16 */
+
+#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */
+#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */
+#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */
+#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */
+#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */
+#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */
+#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */
+#define XCHAL_HAVE_BBENEP_SP_VFPU 0 /* sp_vfpu option on BBE-EP */
+#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */
+#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */
+#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */
+#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */
+#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */
+#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */
+#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */
+#define XCHAL_HAVE_GRIVPEP 0 /* General Release of IVPEP */
+#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */
+
+#define XCHAL_HAVE_VISION 0 /* Vision P5/P6 */
+#define XCHAL_VISION_SIMD16 0 /* simd16 for Vision P5/P6 */
+#define XCHAL_VISION_TYPE 0 /* Vision P5, P6, or P3 */
+#define XCHAL_VISION_QUAD_MAC_TYPE 0 /* quad_mac option on Vision P6 */
+#define XCHAL_HAVE_VISION_HISTOGRAM 0 /* histogram option on Vision P5/P6 */
+#define XCHAL_HAVE_VISION_SP_VFPU 0 /* sp_vfpu option on Vision P5/P6 */
+#define XCHAL_HAVE_VISION_HP_VFPU 0 /* hp_vfpu option on Vision P6 */
+
+/*----------------------------------------------------------------------
+ MISC
+ ----------------------------------------------------------------------*/
+
+#define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */
+#define XCHAL_NUM_WRITEBUFFER_ENTRIES 4 /* size of write buffer */
+#define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */
+#define XCHAL_DATA_WIDTH 4 /* data width in bytes */
+#define XCHAL_DATA_PIPE_DELAY 1 /* d-side pipeline delay
+ (1 = 5-stage, 2 = 7-stage) */
+#define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */
+#define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */
+/* In T1050, applies to selected core load and store instructions (see ISA): */
+#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */
+#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/
+#define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */
+#define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/
+
+#define XCHAL_SW_VERSION 1200004 /* sw version of this header */
+
+#define XCHAL_CORE_ID "sample_controller" /* alphanum core name
+ (CoreID) set in the Xtensa
+ Processor Generator */
+
+#define XCHAL_BUILD_UNIQUE_ID 0x00064D47 /* 22-bit sw build ID */
+
+/*
+ * These definitions describe the hardware targeted by this software.
+ */
+#define XCHAL_HW_CONFIGID0 0xC280DAFE /* ConfigID hi 32 bits*/
+#define XCHAL_HW_CONFIGID1 0x21064D47 /* ConfigID lo 32 bits*/
+#define XCHAL_HW_VERSION_NAME "LX7.0.4" /* full version name */
+#define XCHAL_HW_VERSION_MAJOR 2700 /* major ver# of targeted hw */
+#define XCHAL_HW_VERSION_MINOR 4 /* minor ver# of targeted hw */
+#define XCHAL_HW_VERSION 270004 /* major*100+minor */
+#define XCHAL_HW_REL_LX7 1
+#define XCHAL_HW_REL_LX7_0 1
+#define XCHAL_HW_REL_LX7_0_4 1
+#define XCHAL_HW_CONFIGID_RELIABLE 1
+/* If software targets a *range* of hardware versions, these are the bounds: */
+#define XCHAL_HW_MIN_VERSION_MAJOR 2700 /* major v of earliest tgt hw */
+#define XCHAL_HW_MIN_VERSION_MINOR 4 /* minor v of earliest tgt hw */
+#define XCHAL_HW_MIN_VERSION 270004 /* earliest targeted hw */
+#define XCHAL_HW_MAX_VERSION_MAJOR 2700 /* major v of latest tgt hw */
+#define XCHAL_HW_MAX_VERSION_MINOR 4 /* minor v of latest tgt hw */
+#define XCHAL_HW_MAX_VERSION 270004 /* latest targeted hw */
+
+
+/*----------------------------------------------------------------------
+ CACHE
+ ----------------------------------------------------------------------*/
+
+#define XCHAL_ICACHE_LINESIZE 4 /* I-cache line size in bytes */
+#define XCHAL_DCACHE_LINESIZE 4 /* D-cache line size in bytes */
+#define XCHAL_ICACHE_LINEWIDTH 2 /* log2(I line size in bytes) */
+#define XCHAL_DCACHE_LINEWIDTH 2 /* log2(D line size in bytes) */
+
+#define XCHAL_ICACHE_SIZE 0 /* I-cache size in bytes or 0 */
+#define XCHAL_DCACHE_SIZE 0 /* D-cache size in bytes or 0 */
+
+#define XCHAL_DCACHE_IS_WRITEBACK 0 /* writeback feature */
+#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */
+
+#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */
+#define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */
+#define XCHAL_PREFETCH_CASTOUT_LINES 0 /* dcache pref. castout bufsz */
+#define XCHAL_PREFETCH_ENTRIES 0 /* cache prefetch entries */
+#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */
+#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */
+#define XCHAL_HAVE_ICACHE_TEST 0 /* Icache test instructions */
+#define XCHAL_HAVE_DCACHE_TEST 0 /* Dcache test instructions */
+#define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */
+#define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */
+
+
+
+
+/****************************************************************************
+ Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
+ ****************************************************************************/
+
+
+#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
+
+/*----------------------------------------------------------------------
+ CACHE
+ ----------------------------------------------------------------------*/
+
+#define XCHAL_HAVE_PIF 1 /* any outbound bus present */
+
+#define XCHAL_HAVE_AXI 0 /* AXI bus */
+#define XCHAL_HAVE_AXI_ECC 0 /* ECC on AXI bus */
+#define XCHAL_HAVE_ACELITE 0 /* ACELite bus */
+
+#define XCHAL_HAVE_PIF_WR_RESP 0 /* pif write response */
+#define XCHAL_HAVE_PIF_REQ_ATTR 0 /* pif attribute */
+
+/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
+
+/* Number of cache sets in log2(lines per way): */
+#define XCHAL_ICACHE_SETWIDTH 0
+#define XCHAL_DCACHE_SETWIDTH 0
+
+/* Cache set associativity (number of ways): */
+#define XCHAL_ICACHE_WAYS 1
+#define XCHAL_DCACHE_WAYS 1
+
+/* Cache features: */
+#define XCHAL_ICACHE_LINE_LOCKABLE 0
+#define XCHAL_DCACHE_LINE_LOCKABLE 0
+#define XCHAL_ICACHE_ECC_PARITY 0
+#define XCHAL_DCACHE_ECC_PARITY 0
+
+/* Cache access size in bytes (affects operation of SICW instruction): */
+#define XCHAL_ICACHE_ACCESS_SIZE 1
+#define XCHAL_DCACHE_ACCESS_SIZE 1
+
+#define XCHAL_DCACHE_BANKS 0 /* number of banks */
+
+/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
+#define XCHAL_CA_BITS 4
+
+
+/*----------------------------------------------------------------------
+ INTERNAL I/D RAM/ROMs and XLMI
+ ----------------------------------------------------------------------*/
+#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */
+#define XCHAL_NUM_INSTRAM 1 /* number of core instr. RAMs */
+#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */
+#define XCHAL_NUM_DATARAM 2 /* number of core data RAMs */
+#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
+#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */
+
+/* Instruction RAM 0: */
+#define XCHAL_INSTRAM0_VADDR 0x40000000 /* virtual address */
+#define XCHAL_INSTRAM0_PADDR 0x40000000 /* physical address */
+#define XCHAL_INSTRAM0_SIZE 131072 /* size in bytes */
+#define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
+#define XCHAL_HAVE_INSTRAM0
+#define XCHAL_INSTRAM0_HAVE_IDMA 0 /* idma supported by this local memory */
+
+/* Data RAM 0: */
+#define XCHAL_DATARAM0_VADDR 0x3FFE0000 /* virtual address */
+#define XCHAL_DATARAM0_PADDR 0x3FFE0000 /* physical address */
+#define XCHAL_DATARAM0_SIZE 131072 /* size in bytes */
+#define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
+#define XCHAL_DATARAM0_BANKS 1 /* number of banks */
+#define XCHAL_HAVE_DATARAM0
+#define XCHAL_DATARAM0_HAVE_IDMA 0 /* idma supported by this local memory */
+
+/* Data RAM 1: */
+#define XCHAL_DATARAM1_VADDR 0x3FFC0000 /* virtual address */
+#define XCHAL_DATARAM1_PADDR 0x3FFC0000 /* physical address */
+#define XCHAL_DATARAM1_SIZE 131072 /* size in bytes */
+#define XCHAL_DATARAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */
+#define XCHAL_DATARAM1_BANKS 1 /* number of banks */
+#define XCHAL_HAVE_DATARAM1
+#define XCHAL_DATARAM1_HAVE_IDMA 0 /* idma supported by this local memory */
+
+#define XCHAL_HAVE_IDMA 0
+#define XCHAL_HAVE_IDMA_TRANSPOSE 0
+
+#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/
+
+
+/*----------------------------------------------------------------------
+ INTERRUPTS and TIMERS
+ ----------------------------------------------------------------------*/
+
+#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
+#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
+#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */
+#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
+#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */
+#define XCHAL_NUM_INTERRUPTS 22 /* number of interrupts */
+#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */
+#define XCHAL_NUM_EXTINTERRUPTS 17 /* num of external interrupts */
+#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels
+ (not including level zero) */
+#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */
+ /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
+
+/* Masks of interrupts at each interrupt level: */
+#define XCHAL_INTLEVEL1_MASK 0x001F80FF
+#define XCHAL_INTLEVEL2_MASK 0x00000100
+#define XCHAL_INTLEVEL3_MASK 0x00200E00
+#define XCHAL_INTLEVEL4_MASK 0x00001000
+#define XCHAL_INTLEVEL5_MASK 0x00002000
+#define XCHAL_INTLEVEL6_MASK 0x00000000
+#define XCHAL_INTLEVEL7_MASK 0x00004000
+
+/* Masks of interrupts at each range 1..n of interrupt levels: */
+#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x001F80FF
+#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x001F81FF
+#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x003F8FFF
+#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x003F9FFF
+#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x003FBFFF
+#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x003FBFFF
+#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x003FFFFF
+
+/* Level of each interrupt: */
+#define XCHAL_INT0_LEVEL 1
+#define XCHAL_INT1_LEVEL 1
+#define XCHAL_INT2_LEVEL 1
+#define XCHAL_INT3_LEVEL 1
+#define XCHAL_INT4_LEVEL 1
+#define XCHAL_INT5_LEVEL 1
+#define XCHAL_INT6_LEVEL 1
+#define XCHAL_INT7_LEVEL 1
+#define XCHAL_INT8_LEVEL 2
+#define XCHAL_INT9_LEVEL 3
+#define XCHAL_INT10_LEVEL 3
+#define XCHAL_INT11_LEVEL 3
+#define XCHAL_INT12_LEVEL 4
+#define XCHAL_INT13_LEVEL 5
+#define XCHAL_INT14_LEVEL 7
+#define XCHAL_INT15_LEVEL 1
+#define XCHAL_INT16_LEVEL 1
+#define XCHAL_INT17_LEVEL 1
+#define XCHAL_INT18_LEVEL 1
+#define XCHAL_INT19_LEVEL 1
+#define XCHAL_INT20_LEVEL 1
+#define XCHAL_INT21_LEVEL 3
+#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */
+#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
+#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with
+ EXCSAVE/EPS/EPC_n, RFI n) */
+
+/* Type of each interrupt: */
+#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER
+#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE
+#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER
+#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE
+#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER
+#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI
+#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE
+
+/* Masks of interrupts for each type of interrupt: */
+#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFC00000
+#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000880
+#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x003F8000
+#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000133F
+#define XCHAL_INTTYPE_MASK_TIMER 0x00002440
+#define XCHAL_INTTYPE_MASK_NMI 0x00004000
+#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
+#define XCHAL_INTTYPE_MASK_PROFILING 0x00000000
+#define XCHAL_INTTYPE_MASK_IDMA_DONE 0x00000000
+#define XCHAL_INTTYPE_MASK_IDMA_ERR 0x00000000
+#define XCHAL_INTTYPE_MASK_GS_ERR 0x00000000
+
+/* Interrupt numbers assigned to specific interrupt sources: */
+#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */
+#define XCHAL_TIMER1_INTERRUPT 10 /* CCOMPARE1 */
+#define XCHAL_TIMER2_INTERRUPT 13 /* CCOMPARE2 */
+#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
+#define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */
+
+/* Interrupt numbers for levels at which only one interrupt is configured: */
+#define XCHAL_INTLEVEL2_NUM 8
+#define XCHAL_INTLEVEL4_NUM 12
+#define XCHAL_INTLEVEL5_NUM 13
+#define XCHAL_INTLEVEL7_NUM 14
+/* (There are many interrupts each at level(s) 1, 3.) */
+
+
+/*
+ * External interrupt mapping.
+ * These macros describe how Xtensa processor interrupt numbers
+ * (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
+ * map to external BInterrupt<n> pins, for those interrupts
+ * configured as external (level-triggered, edge-triggered, or NMI).
+ * See the Xtensa processor databook for more details.
+ */
+
+/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */
+#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
+#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */
+#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */
+#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
+#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */
+#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */
+#define XCHAL_EXTINT6_NUM 8 /* (intlevel 2) */
+#define XCHAL_EXTINT7_NUM 9 /* (intlevel 3) */
+#define XCHAL_EXTINT8_NUM 12 /* (intlevel 4) */
+#define XCHAL_EXTINT9_NUM 14 /* (intlevel 7) */
+#define XCHAL_EXTINT10_NUM 15 /* (intlevel 1) */
+#define XCHAL_EXTINT11_NUM 16 /* (intlevel 1) */
+#define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */
+#define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */
+#define XCHAL_EXTINT14_NUM 19 /* (intlevel 1) */
+#define XCHAL_EXTINT15_NUM 20 /* (intlevel 1) */
+#define XCHAL_EXTINT16_NUM 21 /* (intlevel 3) */
+/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */
+#define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */
+#define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */
+#define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */
+#define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */
+#define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */
+#define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */
+#define XCHAL_INT8_EXTNUM 6 /* (intlevel 2) */
+#define XCHAL_INT9_EXTNUM 7 /* (intlevel 3) */
+#define XCHAL_INT12_EXTNUM 8 /* (intlevel 4) */
+#define XCHAL_INT14_EXTNUM 9 /* (intlevel 7) */
+#define XCHAL_INT15_EXTNUM 10 /* (intlevel 1) */
+#define XCHAL_INT16_EXTNUM 11 /* (intlevel 1) */
+#define XCHAL_INT17_EXTNUM 12 /* (intlevel 1) */
+#define XCHAL_INT18_EXTNUM 13 /* (intlevel 1) */
+#define XCHAL_INT19_EXTNUM 14 /* (intlevel 1) */
+#define XCHAL_INT20_EXTNUM 15 /* (intlevel 1) */
+#define XCHAL_INT21_EXTNUM 16 /* (intlevel 3) */
+
+
+/*----------------------------------------------------------------------
+ EXCEPTIONS and VECTORS
+ ----------------------------------------------------------------------*/
+
+#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
+ number: 1 == XEA1 (old)
+ 2 == XEA2 (new)
+ 0 == XEAX (extern) or TX */
+#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
+#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
+#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
+#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
+#define XCHAL_HAVE_HALT 0 /* halt architecture option */
+#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */
+#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
+#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */
+#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */
+#define XCHAL_VECBASE_RESET_VADDR 0x40000000 /* VECBASE reset value */
+#define XCHAL_VECBASE_RESET_PADDR 0x40000000
+#define XCHAL_RESET_VECBASE_OVERLAP 0
+
+#define XCHAL_RESET_VECTOR0_VADDR 0x50000000
+#define XCHAL_RESET_VECTOR0_PADDR 0x50000000
+#define XCHAL_RESET_VECTOR1_VADDR 0x40000400
+#define XCHAL_RESET_VECTOR1_PADDR 0x40000400
+#define XCHAL_RESET_VECTOR_VADDR 0x50000000
+#define XCHAL_RESET_VECTOR_PADDR 0x50000000
+#define XCHAL_USER_VECOFS 0x00000340
+#define XCHAL_USER_VECTOR_VADDR 0x40000340
+#define XCHAL_USER_VECTOR_PADDR 0x40000340
+#define XCHAL_KERNEL_VECOFS 0x00000300
+#define XCHAL_KERNEL_VECTOR_VADDR 0x40000300
+#define XCHAL_KERNEL_VECTOR_PADDR 0x40000300
+#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0
+#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x400003C0
+#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x400003C0
+#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
+#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
+#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
+#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
+#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
+#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
+#define XCHAL_WINDOW_VECTORS_VADDR 0x40000000
+#define XCHAL_WINDOW_VECTORS_PADDR 0x40000000
+#define XCHAL_INTLEVEL2_VECOFS 0x00000180
+#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x40000180
+#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x40000180
+#define XCHAL_INTLEVEL3_VECOFS 0x000001C0
+#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x400001C0
+#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x400001C0
+#define XCHAL_INTLEVEL4_VECOFS 0x00000200
+#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x40000200
+#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x40000200
+#define XCHAL_INTLEVEL5_VECOFS 0x00000240
+#define XCHAL_INTLEVEL5_VECTOR_VADDR 0x40000240
+#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x40000240
+#define XCHAL_INTLEVEL6_VECOFS 0x00000280
+#define XCHAL_INTLEVEL6_VECTOR_VADDR 0x40000280
+#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x40000280
+#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS
+#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR
+#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR
+#define XCHAL_NMI_VECOFS 0x000002C0
+#define XCHAL_NMI_VECTOR_VADDR 0x400002C0
+#define XCHAL_NMI_VECTOR_PADDR 0x400002C0
+#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS
+#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
+#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
+
+
+/*----------------------------------------------------------------------
+ DEBUG MODULE
+ ----------------------------------------------------------------------*/
+
+/* Misc */
+#define XCHAL_HAVE_DEBUG_ERI 0 /* ERI to debug module */
+#define XCHAL_HAVE_DEBUG_APB 0 /* APB to debug module */
+#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */
+
+/* On-Chip Debug (OCD) */
+#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
+#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */
+#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
+#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */
+#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */
+
+/* TRAX (in core) */
+#define XCHAL_HAVE_TRAX 0 /* TRAX in debug module */
+#define XCHAL_TRAX_MEM_SIZE 0 /* TRAX memory size in bytes */
+#define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */
+#define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */
+#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */
+
+/* Perf counters */
+#define XCHAL_NUM_PERF_COUNTERS 0 /* performance counters */
+
+
+/*----------------------------------------------------------------------
+ MMU
+ ----------------------------------------------------------------------*/
+
+/* See core-matmap.h header file for more details. */
+
+#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
+#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */
+#define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */
+#define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */
+#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
+#define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */
+#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */
+#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table
+ [autorefill] and protection)
+ usable for an MMU-based OS */
+
+/* If none of the above last 5 are set, it's a custom TLB configuration. */
+
+#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */
+#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */
+#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */
+
+/*----------------------------------------------------------------------
+ MPU
+ ----------------------------------------------------------------------*/
+#define XCHAL_HAVE_MPU 0
+#define XCHAL_MPU_ENTRIES 0
+
+#define XCHAL_MPU_ALIGN_REQ 1 /* MPU requires alignment of entries to background map */
+#define XCHAL_MPU_BACKGROUND_ENTRIES 0 /* number of entries in bg map*/
+#define XCHAL_MPU_BG_CACHEADRDIS 0 /* default CACHEADRDIS for bg */
+
+#define XCHAL_MPU_ALIGN_BITS 0
+#define XCHAL_MPU_ALIGN 0
+
+#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
+
+
+#endif /* _XTENSA_CORE_CONFIGURATION_H */
+
diff --git a/target/xtensa/core-sample_controller/gdb-config.c b/target/xtensa/core-sample_controller/gdb-config.c
new file mode 100644
index 0000000..99e172d
--- /dev/null
+++ b/target/xtensa/core-sample_controller/gdb-config.c
@@ -0,0 +1,141 @@
+/* Configuration for the Xtensa architecture for GDB, the GNU debugger.
+
+ Copyright (c) 2003-2016 Tensilica Inc.
+
+ Permission is hereby granted, free of charge, to any person obtaining
+ a copy of this software and associated documentation files (the
+ "Software"), to deal in the Software without restriction, including
+ without limitation the rights to use, copy, modify, merge, publish,
+ distribute, sublicense, and/or sell copies of the Software, and to
+ permit persons to whom the Software is furnished to do so, subject to
+ the following conditions:
+
+ The above copyright notice and this permission notice shall be included
+ in all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+ XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0)
+ XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
+ XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
+ XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
+ XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
+ XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
+ XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
+ XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
+ XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
+ XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0)
+ XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9, 0,0,0,0,0,0)
+ XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10, 0,0,0,0,0,0)
+ XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, 0,0,0,0,0,0)
+ XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12, 0,0,0,0,0,0)
+ XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13, 0,0,0,0,0,0)
+ XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14, 0,0,0,0,0,0)
+ XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15, 0,0,0,0,0,0)
+ XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16, 0,0,0,0,0,0)
+ XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17, 0,0,0,0,0,0)
+ XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18, 0,0,0,0,0,0)
+ XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19, 0,0,0,0,0,0)
+ XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20, 0,0,0,0,0,0)
+ XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21, 0,0,0,0,0,0)
+ XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22, 0,0,0,0,0,0)
+ XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23, 0,0,0,0,0,0)
+ XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24, 0,0,0,0,0,0)
+ XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25, 0,0,0,0,0,0)
+ XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26, 0,0,0,0,0,0)
+ XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27, 0,0,0,0,0,0)
+ XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28, 0,0,0,0,0,0)
+ XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, 0,0,0,0,0,0)
+ XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, 0,0,0,0,0,0)
+ XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, 0,0,0,0,0,0)
+ XTREG( 33,132, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0)
+ XTREG( 34,136, 3, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0)
+ XTREG( 35,140, 8, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0)
+ XTREG( 36,144,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0, 0,0,0,0,0,0)
+ XTREG( 37,148,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1, 0,0,0,0,0,0)
+ XTREG( 38,152,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0)
+ XTREG( 39,156,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1, 0,0,0,0,0,0)
+ XTREG( 40,160,32, 4, 4,0x03e6,0x000e,-1, 3,0x0110,expstate, 0,0,0,0,0,0)
+ XTREG( 41,164,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid, 0,0,0,0,0,0)
+ XTREG( 42,168, 2, 4, 4,0x0260,0x0007,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0)
+ XTREG( 43,172, 6, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl, 0,0,0,0,0,0)
+ XTREG( 44,176,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0)
+ XTREG( 45,180,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0, 0,0,0,0,0,0)
+ XTREG( 46,184,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1, 0,0,0,0,0,0)
+ XTREG( 47,188,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0, 0,0,0,0,0,0)
+ XTREG( 48,192,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1, 0,0,0,0,0,0)
+ XTREG( 49,196,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0, 0,0,0,0,0,0)
+ XTREG( 50,200,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1, 0,0,0,0,0,0)
+ XTREG( 51,204,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0)
+ XTREG( 52,208,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0)
+ XTREG( 53,212,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3, 0,0,0,0,0,0)
+ XTREG( 54,216,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4, 0,0,0,0,0,0)
+ XTREG( 55,220,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, 0,0,0,0,0,0)
+ XTREG( 56,224,32, 4, 4,0x02b6,0x0007,-2, 2,0x1000,epc6, 0,0,0,0,0,0)
+ XTREG( 57,228,32, 4, 4,0x02b7,0x0007,-2, 2,0x1000,epc7, 0,0,0,0,0,0)
+ XTREG( 58,232,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0)
+ XTREG( 59,236,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0)
+ XTREG( 60,240,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3, 0,0,0,0,0,0)
+ XTREG( 61,244,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4, 0,0,0,0,0,0)
+ XTREG( 62,248,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5, 0,0,0,0,0,0)
+ XTREG( 63,252,19, 4, 4,0x02c6,0x0007,-2, 2,0x1000,eps6, 0,0,0,0,0,0)
+ XTREG( 64,256,19, 4, 4,0x02c7,0x0007,-2, 2,0x1000,eps7, 0,0,0,0,0,0)
+ XTREG( 65,260,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0)
+ XTREG( 66,264,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0)
+ XTREG( 67,268,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3, 0,0,0,0,0,0)
+ XTREG( 68,272,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4, 0,0,0,0,0,0)
+ XTREG( 69,276,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5, 0,0,0,0,0,0)
+ XTREG( 70,280,32, 4, 4,0x02d6,0x0007,-2, 2,0x1000,excsave6, 0,0,0,0,0,0)
+ XTREG( 71,284,32, 4, 4,0x02d7,0x0007,-2, 2,0x1000,excsave7, 0,0,0,0,0,0)
+ XTREG( 72,288,22, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0)
+ XTREG( 73,292,22, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0)
+ XTREG( 74,296,22, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0)
+ XTREG( 75,300,22, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0)
+ XTREG( 76,304,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0)
+ XTREG( 77,308, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0)
+ XTREG( 78,312,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0)
+ XTREG( 79,316,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0)
+ XTREG( 80,320,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0)
+ XTREG( 81,324,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0)
+ XTREG( 82,328, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0)
+ XTREG( 83,332,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0)
+ XTREG( 84,336,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0)
+ XTREG( 85,340,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0)
+ XTREG( 86,344,32, 4, 4,0x02f2,0x000f,-2, 2,0x1000,ccompare2, 0,0,0,0,0,0)
+ XTREG( 87,348,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0, 0,0,0,0,0,0)
+ XTREG( 88,352,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, 0,0,0,0,0,0)
+ XTREG( 89,356,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0, 0,0,0,0,0,0)
+ XTREG( 90,360,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1, 0,0,0,0,0,0)
+ XTREG( 91,364,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2, 0,0,0,0,0,0)
+ XTREG( 92,368,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3, 0,0,0,0,0,0)
+ XTREG( 93,372,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4, 0,0,0,0,0,0)
+ XTREG( 94,376,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5, 0,0,0,0,0,0)
+ XTREG( 95,380,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6, 0,0,0,0,0,0)
+ XTREG( 96,384,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7, 0,0,0,0,0,0)
+ XTREG( 97,388,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8, 0,0,0,0,0,0)
+ XTREG( 98,392,32, 4, 4,0x0009,0x0006,-2, 8,0x0100,a9, 0,0,0,0,0,0)
+ XTREG( 99,396,32, 4, 4,0x000a,0x0006,-2, 8,0x0100,a10, 0,0,0,0,0,0)
+ XTREG(100,400,32, 4, 4,0x000b,0x0006,-2, 8,0x0100,a11, 0,0,0,0,0,0)
+ XTREG(101,404,32, 4, 4,0x000c,0x0006,-2, 8,0x0100,a12, 0,0,0,0,0,0)
+ XTREG(102,408,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13, 0,0,0,0,0,0)
+ XTREG(103,412,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14, 0,0,0,0,0,0)
+ XTREG(104,416,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15, 0,0,0,0,0,0)
+ XTREG(105,420, 4, 4, 4,0x2008,0x0006,-2, 6,0x1010,psintlevel,
+ 0,0,&xtensa_mask0,0,0,0)
+ XTREG(106,424, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,psum,
+ 0,0,&xtensa_mask1,0,0,0)
+ XTREG(107,428, 1, 4, 4,0x200a,0x0006,-2, 6,0x1010,pswoe,
+ 0,0,&xtensa_mask2,0,0,0)
+ XTREG(108,432, 1, 4, 4,0x200b,0x0006,-2, 6,0x1010,psexcm,
+ 0,0,&xtensa_mask3,0,0,0)
+ XTREG(109,436, 2, 4, 4,0x200c,0x0006,-2, 6,0x1010,pscallinc,
+ 0,0,&xtensa_mask4,0,0,0)
+ XTREG(110,440, 4, 4, 4,0x200d,0x0006,-2, 6,0x1010,psowb,
+ 0,0,&xtensa_mask5,0,0,0)
+ XTREG_END
diff --git a/target/xtensa/core-sample_controller/xtensa-modules.c b/target/xtensa/core-sample_controller/xtensa-modules.c
new file mode 100644
index 0000000..2f00019
--- /dev/null
+++ b/target/xtensa/core-sample_controller/xtensa-modules.c
@@ -0,0 +1,11377 @@
+/* Xtensa configuration-specific ISA information.
+
+ Copyright (c) 2003-2016 Tensilica Inc.
+
+ Permission is hereby granted, free of charge, to any person obtaining
+ a copy of this software and associated documentation files (the
+ "Software"), to deal in the Software without restriction, including
+ without limitation the rights to use, copy, modify, merge, publish,
+ distribute, sublicense, and/or sell copies of the Software, and to
+ permit persons to whom the Software is furnished to do so, subject to
+ the following conditions:
+
+ The above copyright notice and this permission notice shall be included
+ in all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+#include <xtensa-isa.h>
+#include "xtensa-isa-internal.h"
+
+
+/* Sysregs. */
+
+static xtensa_sysreg_internal sysregs[] = {
+ { "MMID", 89, 0 },
+ { "DDR", 104, 0 },
+ { "CONFIGID0", 176, 0 },
+ { "CONFIGID1", 208, 0 },
+ { "INTERRUPT", 226, 0 },
+ { "INTCLEAR", 227, 0 },
+ { "CCOUNT", 234, 0 },
+ { "PRID", 235, 0 },
+ { "ICOUNT", 236, 0 },
+ { "CCOMPARE0", 240, 0 },
+ { "CCOMPARE1", 241, 0 },
+ { "CCOMPARE2", 242, 0 },
+ { "VECBASE", 231, 0 },
+ { "EPC1", 177, 0 },
+ { "EPC2", 178, 0 },
+ { "EPC3", 179, 0 },
+ { "EPC4", 180, 0 },
+ { "EPC5", 181, 0 },
+ { "EPC6", 182, 0 },
+ { "EPC7", 183, 0 },
+ { "EXCSAVE1", 209, 0 },
+ { "EXCSAVE2", 210, 0 },
+ { "EXCSAVE3", 211, 0 },
+ { "EXCSAVE4", 212, 0 },
+ { "EXCSAVE5", 213, 0 },
+ { "EXCSAVE6", 214, 0 },
+ { "EXCSAVE7", 215, 0 },
+ { "EPS2", 194, 0 },
+ { "EPS3", 195, 0 },
+ { "EPS4", 196, 0 },
+ { "EPS5", 197, 0 },
+ { "EPS6", 198, 0 },
+ { "EPS7", 199, 0 },
+ { "EXCCAUSE", 232, 0 },
+ { "DEPC", 192, 0 },
+ { "EXCVADDR", 238, 0 },
+ { "WINDOWBASE", 72, 0 },
+ { "WINDOWSTART", 73, 0 },
+ { "SAR", 3, 0 },
+ { "PS", 230, 0 },
+ { "MISC0", 244, 0 },
+ { "MISC1", 245, 0 },
+ { "INTENABLE", 228, 0 },
+ { "DBREAKA0", 144, 0 },
+ { "DBREAKC0", 160, 0 },
+ { "DBREAKA1", 145, 0 },
+ { "DBREAKC1", 161, 0 },
+ { "IBREAKA0", 128, 0 },
+ { "IBREAKA1", 129, 0 },
+ { "IBREAKENABLE", 96, 0 },
+ { "ICOUNTLEVEL", 237, 0 },
+ { "DEBUGCAUSE", 233, 0 },
+ { "SCOMPARE1", 12, 0 },
+ { "ATOMCTL", 99, 0 },
+ { "EXPSTATE", 230, 1 }
+};
+
+#define NUM_SYSREGS 55
+#define MAX_SPECIAL_REG 245
+#define MAX_USER_REG 230
+
+
+/* Processor states. */
+
+static xtensa_state_internal states[] = {
+ { "PC", 32, 0 },
+ { "ICOUNT", 32, 0 },
+ { "DDR", 32, 0 },
+ { "INTERRUPT", 22, 0 },
+ { "CCOUNT", 32, 0 },
+ { "XTSYNC", 1, 0 },
+ { "VECBASE", 22, 0 },
+ { "EPC1", 32, 0 },
+ { "EPC2", 32, 0 },
+ { "EPC3", 32, 0 },
+ { "EPC4", 32, 0 },
+ { "EPC5", 32, 0 },
+ { "EPC6", 32, 0 },
+ { "EPC7", 32, 0 },
+ { "EXCSAVE1", 32, 0 },
+ { "EXCSAVE2", 32, 0 },
+ { "EXCSAVE3", 32, 0 },
+ { "EXCSAVE4", 32, 0 },
+ { "EXCSAVE5", 32, 0 },
+ { "EXCSAVE6", 32, 0 },
+ { "EXCSAVE7", 32, 0 },
+ { "EPS2", 13, 0 },
+ { "EPS3", 13, 0 },
+ { "EPS4", 13, 0 },
+ { "EPS5", 13, 0 },
+ { "EPS6", 13, 0 },
+ { "EPS7", 13, 0 },
+ { "EXCCAUSE", 6, 0 },
+ { "PSINTLEVEL", 4, 0 },
+ { "PSUM", 1, 0 },
+ { "PSWOE", 1, 0 },
+ { "PSEXCM", 1, 0 },
+ { "DEPC", 32, 0 },
+ { "EXCVADDR", 32, 0 },
+ { "WindowBase", 3, 0 },
+ { "WindowStart", 8, 0 },
+ { "PSCALLINC", 2, 0 },
+ { "PSOWB", 4, 0 },
+ { "SAR", 6, 0 },
+ { "MISC0", 32, 0 },
+ { "MISC1", 32, 0 },
+ { "InOCDMode", 1, 0 },
+ { "INTENABLE", 22, 0 },
+ { "DBREAKA0", 32, 0 },
+ { "DBREAKC0", 8, 0 },
+ { "DBREAKA1", 32, 0 },
+ { "DBREAKC1", 8, 0 },
+ { "IBREAKA0", 32, 0 },
+ { "IBREAKA1", 32, 0 },
+ { "IBREAKENABLE", 2, 0 },
+ { "ICOUNTLEVEL", 4, 0 },
+ { "DEBUGCAUSE", 6, 0 },
+ { "DBNUM", 4, 0 },
+ { "CCOMPARE0", 32, 0 },
+ { "CCOMPARE1", 32, 0 },
+ { "CCOMPARE2", 32, 0 },
+ { "SCOMPARE1", 32, 0 },
+ { "ATOMCTL", 6, 0 },
+ { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED }
+};
+
+#define NUM_STATES 59
+
+enum xtensa_state_id {
+ STATE_PC,
+ STATE_ICOUNT,
+ STATE_DDR,
+ STATE_INTERRUPT,
+ STATE_CCOUNT,
+ STATE_XTSYNC,
+ STATE_VECBASE,
+ STATE_EPC1,
+ STATE_EPC2,
+ STATE_EPC3,
+ STATE_EPC4,
+ STATE_EPC5,
+ STATE_EPC6,
+ STATE_EPC7,
+ STATE_EXCSAVE1,
+ STATE_EXCSAVE2,
+ STATE_EXCSAVE3,
+ STATE_EXCSAVE4,
+ STATE_EXCSAVE5,
+ STATE_EXCSAVE6,
+ STATE_EXCSAVE7,
+ STATE_EPS2,
+ STATE_EPS3,
+ STATE_EPS4,
+ STATE_EPS5,
+ STATE_EPS6,
+ STATE_EPS7,
+ STATE_EXCCAUSE,
+ STATE_PSINTLEVEL,
+ STATE_PSUM,
+ STATE_PSWOE,
+ STATE_PSEXCM,
+ STATE_DEPC,
+ STATE_EXCVADDR,
+ STATE_WindowBase,
+ STATE_WindowStart,
+ STATE_PSCALLINC,
+ STATE_PSOWB,
+ STATE_SAR,
+ STATE_MISC0,
+ STATE_MISC1,
+ STATE_InOCDMode,
+ STATE_INTENABLE,
+ STATE_DBREAKA0,
+ STATE_DBREAKC0,
+ STATE_DBREAKA1,
+ STATE_DBREAKC1,
+ STATE_IBREAKA0,
+ STATE_IBREAKA1,
+ STATE_IBREAKENABLE,
+ STATE_ICOUNTLEVEL,
+ STATE_DEBUGCAUSE,
+ STATE_DBNUM,
+ STATE_CCOMPARE0,
+ STATE_CCOMPARE1,
+ STATE_CCOMPARE2,
+ STATE_SCOMPARE1,
+ STATE_ATOMCTL,
+ STATE_EXPSTATE
+};
+
+
+/* Field definitions. */
+
+static unsigned
+Field_t_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_s_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_r_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
+ return tie_t;
+}
+
+static void
+Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
+}
+
+static unsigned
+Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
+ return tie_t;
+}
+
+static void
+Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
+}
+
+static unsigned
+Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_n_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ return tie_t;
+}
+
+static void
+Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_m_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
+ return tie_t;
+}
+
+static void
+Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
+ return tie_t;
+}
+
+static void
+Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
+}
+
+static unsigned
+Field_st_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+ return tie_t;
+}
+
+static void
+Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+}
+
+static unsigned
+Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_t_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
+ return tie_t;
+}
+
+static void
+Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
+}
+
+static unsigned
+Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+}
+
+static unsigned
+Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_t_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
+ return tie_t;
+}
+
+static void
+Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
+}
+
+static unsigned
+Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20);
+ return tie_t;
+}
+
+static void
+Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 20) >> 20;
+ insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
+ return tie_t;
+}
+
+static void
+Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
+}
+
+static unsigned
+Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
+ return tie_t;
+}
+
+static void
+Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
+ tie_t = (val << 20) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16);
+ return tie_t;
+}
+
+static void
+Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 16) >> 16;
+ insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8);
+}
+
+static unsigned
+Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
+ return tie_t;
+}
+
+static void
+Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 14) >> 14;
+ insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
+ return tie_t;
+}
+
+static void
+Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
+}
+
+static unsigned
+Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
+ return tie_t;
+}
+
+static void
+Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
+}
+
+static unsigned
+Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
+}
+
+static unsigned
+Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
+}
+
+static unsigned
+Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
+}
+
+static unsigned
+Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
+ return tie_t;
+}
+
+static void
+Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
+}
+
+static unsigned
+Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
+}
+
+static unsigned
+Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_st_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_st_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_mn_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ return tie_t;
+}
+
+static void
+Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+}
+
+static unsigned
+Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ return tie_t;
+}
+
+static void
+Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ return tie_t;
+}
+
+static void
+Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
+ return tie_t;
+}
+
+static void
+Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
+ return tie_t;
+}
+
+static void
+Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
+}
+
+static unsigned
+Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
+ return tie_t;
+}
+
+static void
+Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
+}
+
+static unsigned
+Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+ tie_t = (val << 25) >> 29;
+ insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+ tie_t = (val << 25) >> 29;
+ insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
+}
+
+static unsigned
+Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17);
+ return tie_t;
+}
+
+static void
+Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 17) >> 17;
+ insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9);
+}
+
+static unsigned
+Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
+ return tie_t;
+}
+
+static void
+Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 14) >> 14;
+ insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
+}
+
+static unsigned
+Field_bitindex_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_bitindex_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
+}
+
+static unsigned
+Field_bitindex_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_bitindex_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
+}
+
+static unsigned
+Field_s3to1_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+ return tie_t;
+}
+
+static void
+Field_s3to1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+}
+
+static unsigned
+Field_s3to1_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+ return tie_t;
+}
+
+static void
+Field_s3to1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+}
+
+static void
+Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
+ uint32 val ATTRIBUTE_UNUSED)
+{
+ /* Do nothing. */
+}
+
+static unsigned
+Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static unsigned
+Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 4;
+}
+
+static unsigned
+Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 8;
+}
+
+static unsigned
+Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 12;
+}
+
+enum xtensa_field_id {
+ FIELD_t,
+ FIELD_bbi4,
+ FIELD_bbi,
+ FIELD_imm12,
+ FIELD_imm8,
+ FIELD_s,
+ FIELD_imm12b,
+ FIELD_imm16,
+ FIELD_m,
+ FIELD_n,
+ FIELD_offset,
+ FIELD_op0,
+ FIELD_op1,
+ FIELD_op2,
+ FIELD_r,
+ FIELD_sa4,
+ FIELD_sae4,
+ FIELD_sae,
+ FIELD_sal,
+ FIELD_sargt,
+ FIELD_sas4,
+ FIELD_sas,
+ FIELD_sr,
+ FIELD_st,
+ FIELD_thi3,
+ FIELD_imm4,
+ FIELD_mn,
+ FIELD_i,
+ FIELD_imm6lo,
+ FIELD_imm6hi,
+ FIELD_imm7lo,
+ FIELD_imm7hi,
+ FIELD_z,
+ FIELD_imm6,
+ FIELD_imm7,
+ FIELD_xt_wbr15_imm,
+ FIELD_xt_wbr18_imm,
+ FIELD_bitindex,
+ FIELD_s3to1,
+ FIELD__ar0,
+ FIELD__ar4,
+ FIELD__ar8,
+ FIELD__ar12
+};
+
+
+/* Functional units. */
+
+#define funcUnits 0
+
+
+/* Register files. */
+
+enum xtensa_regfile_id {
+ REGFILE_AR
+};
+
+static xtensa_regfile_internal regfiles[] = {
+ { "AR", "a", REGFILE_AR, 32, 32 }
+};
+
+
+/* Interfaces. */
+
+static xtensa_interface_internal interfaces[] = {
+ { "IMPWIRE", 32, 0, 0, 'i' }
+};
+
+enum xtensa_interface_id {
+ INTERFACE_IMPWIRE
+};
+
+
+/* Constant tables. */
+
+/* constant table ai4c */
+static const unsigned CONST_TBL_ai4c_0[] = {
+ 0xffffffff,
+ 0x1,
+ 0x2,
+ 0x3,
+ 0x4,
+ 0x5,
+ 0x6,
+ 0x7,
+ 0x8,
+ 0x9,
+ 0xa,
+ 0xb,
+ 0xc,
+ 0xd,
+ 0xe,
+ 0xf,
+ 0
+};
+
+/* constant table b4c */
+static const unsigned CONST_TBL_b4c_0[] = {
+ 0xffffffff,
+ 0x1,
+ 0x2,
+ 0x3,
+ 0x4,
+ 0x5,
+ 0x6,
+ 0x7,
+ 0x8,
+ 0xa,
+ 0xc,
+ 0x10,
+ 0x20,
+ 0x40,
+ 0x80,
+ 0x100,
+ 0
+};
+
+/* constant table b4cu */
+static const unsigned CONST_TBL_b4cu_0[] = {
+ 0x8000,
+ 0x10000,
+ 0x2,
+ 0x3,
+ 0x4,
+ 0x5,
+ 0x6,
+ 0x7,
+ 0x8,
+ 0xa,
+ 0xc,
+ 0x10,
+ 0x20,
+ 0x40,
+ 0x80,
+ 0x100,
+ 0
+};
+
+
+/* Instruction operands. */
+
+static int
+OperandSem_opnd_sem_soffsetx4_decode (uint32 *valp)
+{
+ unsigned soffsetx4_out_0;
+ unsigned soffsetx4_in_0;
+ soffsetx4_in_0 = *valp & 0x3ffff;
+ soffsetx4_out_0 = 0x4 + ((((int) soffsetx4_in_0 << 14) >> 14) << 2);
+ *valp = soffsetx4_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_soffsetx4_encode (uint32 *valp)
+{
+ unsigned soffsetx4_in_0;
+ unsigned soffsetx4_out_0;
+ soffsetx4_out_0 = *valp;
+ soffsetx4_in_0 = ((soffsetx4_out_0 - 0x4) >> 2) & 0x3ffff;
+ *valp = soffsetx4_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm12x8_decode (uint32 *valp)
+{
+ unsigned uimm12x8_out_0;
+ unsigned uimm12x8_in_0;
+ uimm12x8_in_0 = *valp & 0xfff;
+ uimm12x8_out_0 = uimm12x8_in_0 << 3;
+ *valp = uimm12x8_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm12x8_encode (uint32 *valp)
+{
+ unsigned uimm12x8_in_0;
+ unsigned uimm12x8_out_0;
+ uimm12x8_out_0 = *valp;
+ uimm12x8_in_0 = ((uimm12x8_out_0 >> 3) & 0xfff);
+ *valp = uimm12x8_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm4_decode (uint32 *valp)
+{
+ unsigned simm4_out_0;
+ unsigned simm4_in_0;
+ simm4_in_0 = *valp & 0xf;
+ simm4_out_0 = ((int) simm4_in_0 << 28) >> 28;
+ *valp = simm4_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm4_encode (uint32 *valp)
+{
+ unsigned simm4_in_0;
+ unsigned simm4_out_0;
+ simm4_out_0 = *valp;
+ simm4_in_0 = (simm4_out_0 & 0xf);
+ *valp = simm4_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_encode (uint32 *valp)
+{
+ int error;
+ error = (*valp >= 32);
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_AR_0_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_0_encode (uint32 *valp)
+{
+ int error;
+ error = (*valp >= 32);
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_AR_1_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_1_encode (uint32 *valp)
+{
+ int error;
+ error = (*valp >= 32);
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_AR_2_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_2_encode (uint32 *valp)
+{
+ int error;
+ error = (*valp >= 32);
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_AR_3_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_3_encode (uint32 *valp)
+{
+ int error;
+ error = (*valp >= 32);
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_AR_4_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_4_encode (uint32 *valp)
+{
+ int error;
+ error = (*valp >= 32);
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_immrx4_decode (uint32 *valp)
+{
+ unsigned immrx4_out_0;
+ unsigned immrx4_in_0;
+ immrx4_in_0 = *valp & 0xf;
+ immrx4_out_0 = (((0xfffffff) << 4) | immrx4_in_0) << 2;
+ *valp = immrx4_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_immrx4_encode (uint32 *valp)
+{
+ unsigned immrx4_in_0;
+ unsigned immrx4_out_0;
+ immrx4_out_0 = *valp;
+ immrx4_in_0 = ((immrx4_out_0 >> 2) & 0xf);
+ *valp = immrx4_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_lsi4x4_decode (uint32 *valp)
+{
+ unsigned lsi4x4_out_0;
+ unsigned lsi4x4_in_0;
+ lsi4x4_in_0 = *valp & 0xf;
+ lsi4x4_out_0 = lsi4x4_in_0 << 2;
+ *valp = lsi4x4_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_lsi4x4_encode (uint32 *valp)
+{
+ unsigned lsi4x4_in_0;
+ unsigned lsi4x4_out_0;
+ lsi4x4_out_0 = *valp;
+ lsi4x4_in_0 = ((lsi4x4_out_0 >> 2) & 0xf);
+ *valp = lsi4x4_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm7_decode (uint32 *valp)
+{
+ unsigned simm7_out_0;
+ unsigned simm7_in_0;
+ simm7_in_0 = *valp & 0x7f;
+ simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | simm7_in_0;
+ *valp = simm7_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm7_encode (uint32 *valp)
+{
+ unsigned simm7_in_0;
+ unsigned simm7_out_0;
+ simm7_out_0 = *valp;
+ simm7_in_0 = (simm7_out_0 & 0x7f);
+ *valp = simm7_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm6_decode (uint32 *valp)
+{
+ unsigned uimm6_out_0;
+ unsigned uimm6_in_0;
+ uimm6_in_0 = *valp & 0x3f;
+ uimm6_out_0 = 0x4 + (((0) << 6) | uimm6_in_0);
+ *valp = uimm6_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm6_encode (uint32 *valp)
+{
+ unsigned uimm6_in_0;
+ unsigned uimm6_out_0;
+ uimm6_out_0 = *valp;
+ uimm6_in_0 = (uimm6_out_0 - 0x4) & 0x3f;
+ *valp = uimm6_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_ai4const_decode (uint32 *valp)
+{
+ unsigned ai4const_out_0;
+ unsigned ai4const_in_0;
+ ai4const_in_0 = *valp & 0xf;
+ ai4const_out_0 = CONST_TBL_ai4c_0[ai4const_in_0 & 0xf];
+ *valp = ai4const_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_ai4const_encode (uint32 *valp)
+{
+ unsigned ai4const_in_0;
+ unsigned ai4const_out_0;
+ ai4const_out_0 = *valp;
+ switch (ai4const_out_0)
+ {
+ case 0xffffffff: ai4const_in_0 = 0; break;
+ case 0x1: ai4const_in_0 = 0x1; break;
+ case 0x2: ai4const_in_0 = 0x2; break;
+ case 0x3: ai4const_in_0 = 0x3; break;
+ case 0x4: ai4const_in_0 = 0x4; break;
+ case 0x5: ai4const_in_0 = 0x5; break;
+ case 0x6: ai4const_in_0 = 0x6; break;
+ case 0x7: ai4const_in_0 = 0x7; break;
+ case 0x8: ai4const_in_0 = 0x8; break;
+ case 0x9: ai4const_in_0 = 0x9; break;
+ case 0xa: ai4const_in_0 = 0xa; break;
+ case 0xb: ai4const_in_0 = 0xb; break;
+ case 0xc: ai4const_in_0 = 0xc; break;
+ case 0xd: ai4const_in_0 = 0xd; break;
+ case 0xe: ai4const_in_0 = 0xe; break;
+ default: ai4const_in_0 = 0xf; break;
+ }
+ *valp = ai4const_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_b4const_decode (uint32 *valp)
+{
+ unsigned b4const_out_0;
+ unsigned b4const_in_0;
+ b4const_in_0 = *valp & 0xf;
+ b4const_out_0 = CONST_TBL_b4c_0[b4const_in_0 & 0xf];
+ *valp = b4const_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_b4const_encode (uint32 *valp)
+{
+ unsigned b4const_in_0;
+ unsigned b4const_out_0;
+ b4const_out_0 = *valp;
+ switch (b4const_out_0)
+ {
+ case 0xffffffff: b4const_in_0 = 0; break;
+ case 0x1: b4const_in_0 = 0x1; break;
+ case 0x2: b4const_in_0 = 0x2; break;
+ case 0x3: b4const_in_0 = 0x3; break;
+ case 0x4: b4const_in_0 = 0x4; break;
+ case 0x5: b4const_in_0 = 0x5; break;
+ case 0x6: b4const_in_0 = 0x6; break;
+ case 0x7: b4const_in_0 = 0x7; break;
+ case 0x8: b4const_in_0 = 0x8; break;
+ case 0xa: b4const_in_0 = 0x9; break;
+ case 0xc: b4const_in_0 = 0xa; break;
+ case 0x10: b4const_in_0 = 0xb; break;
+ case 0x20: b4const_in_0 = 0xc; break;
+ case 0x40: b4const_in_0 = 0xd; break;
+ case 0x80: b4const_in_0 = 0xe; break;
+ default: b4const_in_0 = 0xf; break;
+ }
+ *valp = b4const_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_b4constu_decode (uint32 *valp)
+{
+ unsigned b4constu_out_0;
+ unsigned b4constu_in_0;
+ b4constu_in_0 = *valp & 0xf;
+ b4constu_out_0 = CONST_TBL_b4cu_0[b4constu_in_0 & 0xf];
+ *valp = b4constu_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_b4constu_encode (uint32 *valp)
+{
+ unsigned b4constu_in_0;
+ unsigned b4constu_out_0;
+ b4constu_out_0 = *valp;
+ switch (b4constu_out_0)
+ {
+ case 0x8000: b4constu_in_0 = 0; break;
+ case 0x10000: b4constu_in_0 = 0x1; break;
+ case 0x2: b4constu_in_0 = 0x2; break;
+ case 0x3: b4constu_in_0 = 0x3; break;
+ case 0x4: b4constu_in_0 = 0x4; break;
+ case 0x5: b4constu_in_0 = 0x5; break;
+ case 0x6: b4constu_in_0 = 0x6; break;
+ case 0x7: b4constu_in_0 = 0x7; break;
+ case 0x8: b4constu_in_0 = 0x8; break;
+ case 0xa: b4constu_in_0 = 0x9; break;
+ case 0xc: b4constu_in_0 = 0xa; break;
+ case 0x10: b4constu_in_0 = 0xb; break;
+ case 0x20: b4constu_in_0 = 0xc; break;
+ case 0x40: b4constu_in_0 = 0xd; break;
+ case 0x80: b4constu_in_0 = 0xe; break;
+ default: b4constu_in_0 = 0xf; break;
+ }
+ *valp = b4constu_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8_decode (uint32 *valp)
+{
+ unsigned uimm8_out_0;
+ unsigned uimm8_in_0;
+ uimm8_in_0 = *valp & 0xff;
+ uimm8_out_0 = uimm8_in_0;
+ *valp = uimm8_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8_encode (uint32 *valp)
+{
+ unsigned uimm8_in_0;
+ unsigned uimm8_out_0;
+ uimm8_out_0 = *valp;
+ uimm8_in_0 = (uimm8_out_0 & 0xff);
+ *valp = uimm8_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8x2_decode (uint32 *valp)
+{
+ unsigned uimm8x2_out_0;
+ unsigned uimm8x2_in_0;
+ uimm8x2_in_0 = *valp & 0xff;
+ uimm8x2_out_0 = uimm8x2_in_0 << 1;
+ *valp = uimm8x2_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8x2_encode (uint32 *valp)
+{
+ unsigned uimm8x2_in_0;
+ unsigned uimm8x2_out_0;
+ uimm8x2_out_0 = *valp;
+ uimm8x2_in_0 = ((uimm8x2_out_0 >> 1) & 0xff);
+ *valp = uimm8x2_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8x4_decode (uint32 *valp)
+{
+ unsigned uimm8x4_out_0;
+ unsigned uimm8x4_in_0;
+ uimm8x4_in_0 = *valp & 0xff;
+ uimm8x4_out_0 = uimm8x4_in_0 << 2;
+ *valp = uimm8x4_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8x4_encode (uint32 *valp)
+{
+ unsigned uimm8x4_in_0;
+ unsigned uimm8x4_out_0;
+ uimm8x4_out_0 = *valp;
+ uimm8x4_in_0 = ((uimm8x4_out_0 >> 2) & 0xff);
+ *valp = uimm8x4_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm4x16_decode (uint32 *valp)
+{
+ unsigned uimm4x16_out_0;
+ unsigned uimm4x16_in_0;
+ uimm4x16_in_0 = *valp & 0xf;
+ uimm4x16_out_0 = uimm4x16_in_0 << 4;
+ *valp = uimm4x16_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm4x16_encode (uint32 *valp)
+{
+ unsigned uimm4x16_in_0;
+ unsigned uimm4x16_out_0;
+ uimm4x16_out_0 = *valp;
+ uimm4x16_in_0 = ((uimm4x16_out_0 >> 4) & 0xf);
+ *valp = uimm4x16_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimmrx4_decode (uint32 *valp)
+{
+ unsigned uimmrx4_out_0;
+ unsigned uimmrx4_in_0;
+ uimmrx4_in_0 = *valp & 0xf;
+ uimmrx4_out_0 = uimmrx4_in_0 << 2;
+ *valp = uimmrx4_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimmrx4_encode (uint32 *valp)
+{
+ unsigned uimmrx4_in_0;
+ unsigned uimmrx4_out_0;
+ uimmrx4_out_0 = *valp;
+ uimmrx4_in_0 = ((uimmrx4_out_0 >> 2) & 0xf);
+ *valp = uimmrx4_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm8_decode (uint32 *valp)
+{
+ unsigned simm8_out_0;
+ unsigned simm8_in_0;
+ simm8_in_0 = *valp & 0xff;
+ simm8_out_0 = ((int) simm8_in_0 << 24) >> 24;
+ *valp = simm8_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm8_encode (uint32 *valp)
+{
+ unsigned simm8_in_0;
+ unsigned simm8_out_0;
+ simm8_out_0 = *valp;
+ simm8_in_0 = (simm8_out_0 & 0xff);
+ *valp = simm8_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm8x256_decode (uint32 *valp)
+{
+ unsigned simm8x256_out_0;
+ unsigned simm8x256_in_0;
+ simm8x256_in_0 = *valp & 0xff;
+ simm8x256_out_0 = (((int) simm8x256_in_0 << 24) >> 24) << 8;
+ *valp = simm8x256_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm8x256_encode (uint32 *valp)
+{
+ unsigned simm8x256_in_0;
+ unsigned simm8x256_out_0;
+ simm8x256_out_0 = *valp;
+ simm8x256_in_0 = ((simm8x256_out_0 >> 8) & 0xff);
+ *valp = simm8x256_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm12b_decode (uint32 *valp)
+{
+ unsigned simm12b_out_0;
+ unsigned simm12b_in_0;
+ simm12b_in_0 = *valp & 0xfff;
+ simm12b_out_0 = ((int) simm12b_in_0 << 20) >> 20;
+ *valp = simm12b_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm12b_encode (uint32 *valp)
+{
+ unsigned simm12b_in_0;
+ unsigned simm12b_out_0;
+ simm12b_out_0 = *valp;
+ simm12b_in_0 = (simm12b_out_0 & 0xfff);
+ *valp = simm12b_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_msalp32_decode (uint32 *valp)
+{
+ unsigned msalp32_out_0;
+ unsigned msalp32_in_0;
+ msalp32_in_0 = *valp & 0x1f;
+ msalp32_out_0 = 0x20 - msalp32_in_0;
+ *valp = msalp32_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_msalp32_encode (uint32 *valp)
+{
+ unsigned msalp32_in_0;
+ unsigned msalp32_out_0;
+ msalp32_out_0 = *valp;
+ msalp32_in_0 = (0x20 - msalp32_out_0) & 0x1f;
+ *valp = msalp32_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_op2p1_decode (uint32 *valp)
+{
+ unsigned op2p1_out_0;
+ unsigned op2p1_in_0;
+ op2p1_in_0 = *valp & 0xf;
+ op2p1_out_0 = op2p1_in_0 + 0x1;
+ *valp = op2p1_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_op2p1_encode (uint32 *valp)
+{
+ unsigned op2p1_in_0;
+ unsigned op2p1_out_0;
+ op2p1_out_0 = *valp;
+ op2p1_in_0 = (op2p1_out_0 - 0x1) & 0xf;
+ *valp = op2p1_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_label8_decode (uint32 *valp)
+{
+ unsigned label8_out_0;
+ unsigned label8_in_0;
+ label8_in_0 = *valp & 0xff;
+ label8_out_0 = 0x4 + (((int) label8_in_0 << 24) >> 24);
+ *valp = label8_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_label8_encode (uint32 *valp)
+{
+ unsigned label8_in_0;
+ unsigned label8_out_0;
+ label8_out_0 = *valp;
+ label8_in_0 = (label8_out_0 - 0x4) & 0xff;
+ *valp = label8_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_label12_decode (uint32 *valp)
+{
+ unsigned label12_out_0;
+ unsigned label12_in_0;
+ label12_in_0 = *valp & 0xfff;
+ label12_out_0 = 0x4 + (((int) label12_in_0 << 20) >> 20);
+ *valp = label12_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_label12_encode (uint32 *valp)
+{
+ unsigned label12_in_0;
+ unsigned label12_out_0;
+ label12_out_0 = *valp;
+ label12_in_0 = (label12_out_0 - 0x4) & 0xfff;
+ *valp = label12_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_soffset_decode (uint32 *valp)
+{
+ unsigned soffset_out_0;
+ unsigned soffset_in_0;
+ soffset_in_0 = *valp & 0x3ffff;
+ soffset_out_0 = 0x4 + (((int) soffset_in_0 << 14) >> 14);
+ *valp = soffset_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_soffset_encode (uint32 *valp)
+{
+ unsigned soffset_in_0;
+ unsigned soffset_out_0;
+ soffset_out_0 = *valp;
+ soffset_in_0 = (soffset_out_0 - 0x4) & 0x3ffff;
+ *valp = soffset_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm16x4_decode (uint32 *valp)
+{
+ unsigned uimm16x4_out_0;
+ unsigned uimm16x4_in_0;
+ uimm16x4_in_0 = *valp & 0xffff;
+ uimm16x4_out_0 = (((0xffff) << 16) | uimm16x4_in_0) << 2;
+ *valp = uimm16x4_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm16x4_encode (uint32 *valp)
+{
+ unsigned uimm16x4_in_0;
+ unsigned uimm16x4_out_0;
+ uimm16x4_out_0 = *valp;
+ uimm16x4_in_0 = (uimm16x4_out_0 >> 2) & 0xffff;
+ *valp = uimm16x4_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_bbi_decode (uint32 *valp)
+{
+ unsigned bbi_out_0;
+ unsigned bbi_in_0;
+ bbi_in_0 = *valp & 0x1f;
+ bbi_out_0 = (0 << 5) | bbi_in_0;
+ *valp = bbi_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_bbi_encode (uint32 *valp)
+{
+ unsigned bbi_in_0;
+ unsigned bbi_out_0;
+ bbi_out_0 = *valp;
+ bbi_in_0 = (bbi_out_0 & 0x1f);
+ *valp = bbi_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_s_decode (uint32 *valp)
+{
+ unsigned s_out_0;
+ unsigned s_in_0;
+ s_in_0 = *valp & 0xf;
+ s_out_0 = (0 << 4) | s_in_0;
+ *valp = s_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_s_encode (uint32 *valp)
+{
+ unsigned s_in_0;
+ unsigned s_out_0;
+ s_out_0 = *valp;
+ s_in_0 = (s_out_0 & 0xf);
+ *valp = s_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_immt_decode (uint32 *valp)
+{
+ unsigned immt_out_0;
+ unsigned immt_in_0;
+ immt_in_0 = *valp & 0xf;
+ immt_out_0 = immt_in_0;
+ *valp = immt_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_immt_encode (uint32 *valp)
+{
+ unsigned immt_in_0;
+ unsigned immt_out_0;
+ immt_out_0 = *valp;
+ immt_in_0 = immt_out_0 & 0xf;
+ *valp = immt_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_tp7_decode (uint32 *valp)
+{
+ unsigned tp7_out_0;
+ unsigned tp7_in_0;
+ tp7_in_0 = *valp & 0xf;
+ tp7_out_0 = tp7_in_0 + 0x7;
+ *valp = tp7_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_tp7_encode (uint32 *valp)
+{
+ unsigned tp7_in_0;
+ unsigned tp7_out_0;
+ tp7_out_0 = *valp;
+ tp7_in_0 = (tp7_out_0 - 0x7) & 0xf;
+ *valp = tp7_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_xt_wbr15_label_decode (uint32 *valp)
+{
+ unsigned xt_wbr15_label_out_0;
+ unsigned xt_wbr15_label_in_0;
+ xt_wbr15_label_in_0 = *valp & 0x7fff;
+ xt_wbr15_label_out_0 = 0x4 + (((int) xt_wbr15_label_in_0 << 17) >> 17);
+ *valp = xt_wbr15_label_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_xt_wbr15_label_encode (uint32 *valp)
+{
+ unsigned xt_wbr15_label_in_0;
+ unsigned xt_wbr15_label_out_0;
+ xt_wbr15_label_out_0 = *valp;
+ xt_wbr15_label_in_0 = (xt_wbr15_label_out_0 - 0x4) & 0x7fff;
+ *valp = xt_wbr15_label_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_xt_wbr18_label_decode (uint32 *valp)
+{
+ unsigned xt_wbr18_label_out_0;
+ unsigned xt_wbr18_label_in_0;
+ xt_wbr18_label_in_0 = *valp & 0x3ffff;
+ xt_wbr18_label_out_0 = 0x4 + (((int) xt_wbr18_label_in_0 << 14) >> 14);
+ *valp = xt_wbr18_label_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_xt_wbr18_label_encode (uint32 *valp)
+{
+ unsigned xt_wbr18_label_in_0;
+ unsigned xt_wbr18_label_out_0;
+ xt_wbr18_label_out_0 = *valp;
+ xt_wbr18_label_in_0 = (xt_wbr18_label_out_0 - 0x4) & 0x3ffff;
+ *valp = xt_wbr18_label_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_bitindex_decode (uint32 *valp)
+{
+ unsigned bitindex_out_0;
+ unsigned bitindex_in_0;
+ bitindex_in_0 = *valp & 0x1f;
+ bitindex_out_0 = (0 << 5) | bitindex_in_0;
+ *valp = bitindex_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_bitindex_encode (uint32 *valp)
+{
+ unsigned bitindex_in_0;
+ unsigned bitindex_out_0;
+ bitindex_out_0 = *valp;
+ bitindex_in_0 = (bitindex_out_0 & 0x1f);
+ *valp = bitindex_in_0;
+ return 0;
+}
+
+static int
+Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= (pc & ~0x3);
+ return 0;
+}
+
+static int
+Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += (pc & ~0x3);
+ return 0;
+}
+
+static int
+Operand_uimm6_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static int
+Operand_label8_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_label8_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static int
+Operand_label12_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_label12_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static int
+Operand_soffset_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_soffset_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static int
+Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= ((pc + 3) & ~0x3);
+ return 0;
+}
+
+static int
+Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += ((pc + 3) & ~0x3);
+ return 0;
+}
+
+static int
+Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static int
+Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static xtensa_operand_internal operands[] = {
+ { "soffsetx4", FIELD_offset, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_soffsetx4_encode, OperandSem_opnd_sem_soffsetx4_decode,
+ Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
+ { "uimm12x8", FIELD_imm12, -1, 0,
+ 0,
+ OperandSem_opnd_sem_uimm12x8_encode, OperandSem_opnd_sem_uimm12x8_decode,
+ 0, 0 },
+ { "simm4", FIELD_mn, -1, 0,
+ 0,
+ OperandSem_opnd_sem_simm4_encode, OperandSem_opnd_sem_simm4_decode,
+ 0, 0 },
+ { "arr", FIELD_r, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+ 0, 0 },
+ { "ars", FIELD_s, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+ 0, 0 },
+ { "*ars_invisible", FIELD_s, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+ 0, 0 },
+ { "art", FIELD_t, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+ 0, 0 },
+ { "ar0", FIELD__ar0, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ OperandSem_opnd_sem_AR_0_encode, OperandSem_opnd_sem_AR_0_decode,
+ 0, 0 },
+ { "ar4", FIELD__ar4, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ OperandSem_opnd_sem_AR_1_encode, OperandSem_opnd_sem_AR_1_decode,
+ 0, 0 },
+ { "ar8", FIELD__ar8, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ OperandSem_opnd_sem_AR_2_encode, OperandSem_opnd_sem_AR_2_decode,
+ 0, 0 },
+ { "ar12", FIELD__ar12, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ OperandSem_opnd_sem_AR_3_encode, OperandSem_opnd_sem_AR_3_decode,
+ 0, 0 },
+ { "ars_entry", FIELD_s, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_AR_4_encode, OperandSem_opnd_sem_AR_4_decode,
+ 0, 0 },
+ { "immrx4", FIELD_r, -1, 0,
+ 0,
+ OperandSem_opnd_sem_immrx4_encode, OperandSem_opnd_sem_immrx4_decode,
+ 0, 0 },
+ { "lsi4x4", FIELD_r, -1, 0,
+ 0,
+ OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode,
+ 0, 0 },
+ { "simm7", FIELD_imm7, -1, 0,
+ 0,
+ OperandSem_opnd_sem_simm7_encode, OperandSem_opnd_sem_simm7_decode,
+ 0, 0 },
+ { "uimm6", FIELD_imm6, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_uimm6_encode, OperandSem_opnd_sem_uimm6_decode,
+ Operand_uimm6_ator, Operand_uimm6_rtoa },
+ { "ai4const", FIELD_t, -1, 0,
+ 0,
+ OperandSem_opnd_sem_ai4const_encode, OperandSem_opnd_sem_ai4const_decode,
+ 0, 0 },
+ { "b4const", FIELD_r, -1, 0,
+ 0,
+ OperandSem_opnd_sem_b4const_encode, OperandSem_opnd_sem_b4const_decode,
+ 0, 0 },
+ { "b4constu", FIELD_r, -1, 0,
+ 0,
+ OperandSem_opnd_sem_b4constu_encode, OperandSem_opnd_sem_b4constu_decode,
+ 0, 0 },
+ { "uimm8", FIELD_imm8, -1, 0,
+ 0,
+ OperandSem_opnd_sem_uimm8_encode, OperandSem_opnd_sem_uimm8_decode,
+ 0, 0 },
+ { "uimm8x2", FIELD_imm8, -1, 0,
+ 0,
+ OperandSem_opnd_sem_uimm8x2_encode, OperandSem_opnd_sem_uimm8x2_decode,
+ 0, 0 },
+ { "uimm8x4", FIELD_imm8, -1, 0,
+ 0,
+ OperandSem_opnd_sem_uimm8x4_encode, OperandSem_opnd_sem_uimm8x4_decode,
+ 0, 0 },
+ { "uimm4x16", FIELD_op2, -1, 0,
+ 0,
+ OperandSem_opnd_sem_uimm4x16_encode, OperandSem_opnd_sem_uimm4x16_decode,
+ 0, 0 },
+ { "uimmrx4", FIELD_r, -1, 0,
+ 0,
+ OperandSem_opnd_sem_uimmrx4_encode, OperandSem_opnd_sem_uimmrx4_decode,
+ 0, 0 },
+ { "simm8", FIELD_imm8, -1, 0,
+ 0,
+ OperandSem_opnd_sem_simm8_encode, OperandSem_opnd_sem_simm8_decode,
+ 0, 0 },
+ { "simm8x256", FIELD_imm8, -1, 0,
+ 0,
+ OperandSem_opnd_sem_simm8x256_encode, OperandSem_opnd_sem_simm8x256_decode,
+ 0, 0 },
+ { "simm12b", FIELD_imm12b, -1, 0,
+ 0,
+ OperandSem_opnd_sem_simm12b_encode, OperandSem_opnd_sem_simm12b_decode,
+ 0, 0 },
+ { "msalp32", FIELD_sal, -1, 0,
+ 0,
+ OperandSem_opnd_sem_msalp32_encode, OperandSem_opnd_sem_msalp32_decode,
+ 0, 0 },
+ { "op2p1", FIELD_op2, -1, 0,
+ 0,
+ OperandSem_opnd_sem_op2p1_encode, OperandSem_opnd_sem_op2p1_decode,
+ 0, 0 },
+ { "label8", FIELD_imm8, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_label8_encode, OperandSem_opnd_sem_label8_decode,
+ Operand_label8_ator, Operand_label8_rtoa },
+ { "label12", FIELD_imm12, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_label12_encode, OperandSem_opnd_sem_label12_decode,
+ Operand_label12_ator, Operand_label12_rtoa },
+ { "soffset", FIELD_offset, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode,
+ Operand_soffset_ator, Operand_soffset_rtoa },
+ { "uimm16x4", FIELD_imm16, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_uimm16x4_encode, OperandSem_opnd_sem_uimm16x4_decode,
+ Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
+ { "bbi", FIELD_bbi, -1, 0,
+ 0,
+ OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
+ 0, 0 },
+ { "sae", FIELD_sae, -1, 0,
+ 0,
+ OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
+ 0, 0 },
+ { "sas", FIELD_sas, -1, 0,
+ 0,
+ OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
+ 0, 0 },
+ { "sargt", FIELD_sargt, -1, 0,
+ 0,
+ OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
+ 0, 0 },
+ { "s", FIELD_s, -1, 0,
+ 0,
+ OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode,
+ 0, 0 },
+ { "immt", FIELD_t, -1, 0,
+ 0,
+ OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode,
+ 0, 0 },
+ { "imms", FIELD_s, -1, 0,
+ 0,
+ OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode,
+ 0, 0 },
+ { "tp7", FIELD_t, -1, 0,
+ 0,
+ OperandSem_opnd_sem_tp7_encode, OperandSem_opnd_sem_tp7_decode,
+ 0, 0 },
+ { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_xt_wbr15_label_encode, OperandSem_opnd_sem_xt_wbr15_label_decode,
+ Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa },
+ { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_xt_wbr18_label_encode, OperandSem_opnd_sem_xt_wbr18_label_decode,
+ Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa },
+ { "bitindex", FIELD_bitindex, -1, 0,
+ 0,
+ OperandSem_opnd_sem_bitindex_encode, OperandSem_opnd_sem_bitindex_decode,
+ 0, 0 },
+ { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 },
+ { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 },
+ { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 },
+ { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 },
+ { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 },
+ { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 },
+ { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 },
+ { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 },
+ { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 },
+ { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 },
+ { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 },
+ { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 },
+ { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 },
+ { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 },
+ { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 },
+ { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 },
+ { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 },
+ { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 },
+ { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 },
+ { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 },
+ { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 },
+ { "s3to1", FIELD_s3to1, -1, 0, 0, 0, 0, 0, 0 }
+};
+
+enum xtensa_operand_id {
+ OPERAND_soffsetx4,
+ OPERAND_uimm12x8,
+ OPERAND_simm4,
+ OPERAND_arr,
+ OPERAND_ars,
+ OPERAND__ars_invisible,
+ OPERAND_art,
+ OPERAND_ar0,
+ OPERAND_ar4,
+ OPERAND_ar8,
+ OPERAND_ar12,
+ OPERAND_ars_entry,
+ OPERAND_immrx4,
+ OPERAND_lsi4x4,
+ OPERAND_simm7,
+ OPERAND_uimm6,
+ OPERAND_ai4const,
+ OPERAND_b4const,
+ OPERAND_b4constu,
+ OPERAND_uimm8,
+ OPERAND_uimm8x2,
+ OPERAND_uimm8x4,
+ OPERAND_uimm4x16,
+ OPERAND_uimmrx4,
+ OPERAND_simm8,
+ OPERAND_simm8x256,
+ OPERAND_simm12b,
+ OPERAND_msalp32,
+ OPERAND_op2p1,
+ OPERAND_label8,
+ OPERAND_label12,
+ OPERAND_soffset,
+ OPERAND_uimm16x4,
+ OPERAND_bbi,
+ OPERAND_sae,
+ OPERAND_sas,
+ OPERAND_sargt,
+ OPERAND_s,
+ OPERAND_immt,
+ OPERAND_imms,
+ OPERAND_tp7,
+ OPERAND_xt_wbr15_label,
+ OPERAND_xt_wbr18_label,
+ OPERAND_bitindex,
+ OPERAND_t,
+ OPERAND_bbi4,
+ OPERAND_imm12,
+ OPERAND_imm8,
+ OPERAND_imm12b,
+ OPERAND_imm16,
+ OPERAND_m,
+ OPERAND_n,
+ OPERAND_offset,
+ OPERAND_op0,
+ OPERAND_op1,
+ OPERAND_op2,
+ OPERAND_r,
+ OPERAND_sa4,
+ OPERAND_sae4,
+ OPERAND_sal,
+ OPERAND_sas4,
+ OPERAND_sr,
+ OPERAND_st,
+ OPERAND_thi3,
+ OPERAND_imm4,
+ OPERAND_mn,
+ OPERAND_i,
+ OPERAND_imm6lo,
+ OPERAND_imm6hi,
+ OPERAND_imm7lo,
+ OPERAND_imm7hi,
+ OPERAND_z,
+ OPERAND_imm6,
+ OPERAND_imm7,
+ OPERAND_xt_wbr15_imm,
+ OPERAND_xt_wbr18_imm,
+ OPERAND_s3to1
+};
+
+
+/* Iclass table. */
+
+static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
+ { { STATE_PSEXCM }, 'o' },
+ { { STATE_EPC1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
+ { { STATE_DEPC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
+ { { OPERAND_soffsetx4 }, 'i' },
+ { { OPERAND_ar12 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
+ { { OPERAND_soffsetx4 }, 'i' },
+ { { OPERAND_ar8 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
+ { { OPERAND_soffsetx4 }, 'i' },
+ { { OPERAND_ar4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ar12 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ar8 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ar4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
+ { { OPERAND_ars_entry }, 's' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm12x8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'i' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSWOE }, 'i' },
+ { { STATE_WindowBase }, 'm' },
+ { { STATE_WindowStart }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
+ { { STATE_WindowBase }, 'i' },
+ { { STATE_WindowStart }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
+ { { OPERAND_simm4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
+ { { STATE_WindowBase }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
+ { { OPERAND__ars_invisible }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
+ { { STATE_WindowBase }, 'm' },
+ { { STATE_WindowStart }, 'm' },
+ { { STATE_PSCALLINC }, 'o' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSWOE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
+ { { STATE_EPC1 }, 'i' },
+ { { STATE_PSEXCM }, 'o' },
+ { { STATE_WindowBase }, 'm' },
+ { { STATE_WindowStart }, 'm' },
+ { { STATE_PSOWB }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_immrx4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_immrx4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
+ { { STATE_WindowBase }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
+ { { STATE_WindowBase }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
+ { { STATE_WindowBase }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
+ { { STATE_WindowStart }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
+ { { STATE_WindowStart }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
+ { { STATE_WindowStart }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ai4const }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm6 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_lsi4x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
+ { { OPERAND_ars }, 'o' },
+ { { OPERAND_simm7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
+ { { OPERAND__ars_invisible }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_lsi4x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_simm8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_simm8x256 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_b4const }, 'i' },
+ { { OPERAND_label8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_bbi }, 'i' },
+ { { OPERAND_label8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_b4constu }, 'i' },
+ { { OPERAND_label8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_label8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_label12 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
+ { { OPERAND_soffsetx4 }, 'i' },
+ { { OPERAND_ar0 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ar0 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_sae }, 'i' },
+ { { OPERAND_op2p1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
+ { { OPERAND_soffset }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_uimm16x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_simm12b }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
+ { { OPERAND_arr }, 'm' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
+ { { OPERAND__ars_invisible }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32nb_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimmrx4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
+ { { STATE_SAR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
+ { { OPERAND_sas }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
+ { { STATE_SAR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
+ { { STATE_SAR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
+ { { STATE_SAR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
+ { { STATE_SAR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_msalp32 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_sargt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_s }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
+ { { STATE_XTSYNC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_s }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
+ { { STATE_PSWOE }, 'i' },
+ { { STATE_PSCALLINC }, 'i' },
+ { { STATE_PSOWB }, 'i' },
+ { { STATE_PSUM }, 'i' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSINTLEVEL }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
+ { { STATE_SAR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
+ { { STATE_SAR }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
+ { { STATE_SAR }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_memctl_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_memctl_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_memctl_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
+ { { STATE_PSWOE }, 'i' },
+ { { STATE_PSCALLINC }, 'i' },
+ { { STATE_PSOWB }, 'i' },
+ { { STATE_PSUM }, 'i' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSINTLEVEL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
+ { { STATE_PSWOE }, 'o' },
+ { { STATE_PSCALLINC }, 'o' },
+ { { STATE_PSOWB }, 'o' },
+ { { STATE_PSUM }, 'o' },
+ { { STATE_PSEXCM }, 'o' },
+ { { STATE_PSINTLEVEL }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
+ { { STATE_PSWOE }, 'm' },
+ { { STATE_PSCALLINC }, 'm' },
+ { { STATE_PSOWB }, 'm' },
+ { { STATE_PSUM }, 'm' },
+ { { STATE_PSEXCM }, 'm' },
+ { { STATE_PSINTLEVEL }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
+ { { STATE_EPC1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
+ { { STATE_EPC1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
+ { { STATE_EPC1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
+ { { STATE_EXCSAVE1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
+ { { STATE_EXCSAVE1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
+ { { STATE_EXCSAVE1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
+ { { STATE_EPC2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
+ { { STATE_EPC2 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
+ { { STATE_EPC2 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
+ { { STATE_EXCSAVE2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
+ { { STATE_EXCSAVE2 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
+ { { STATE_EXCSAVE2 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = {
+ { { STATE_EPC3 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = {
+ { { STATE_EPC3 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = {
+ { { STATE_EPC3 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = {
+ { { STATE_EXCSAVE3 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = {
+ { { STATE_EXCSAVE3 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = {
+ { { STATE_EXCSAVE3 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = {
+ { { STATE_EPC4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = {
+ { { STATE_EPC4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = {
+ { { STATE_EPC4 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = {
+ { { STATE_EXCSAVE4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = {
+ { { STATE_EXCSAVE4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = {
+ { { STATE_EXCSAVE4 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = {
+ { { STATE_EPC5 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = {
+ { { STATE_EPC5 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = {
+ { { STATE_EPC5 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = {
+ { { STATE_EXCSAVE5 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = {
+ { { STATE_EXCSAVE5 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = {
+ { { STATE_EXCSAVE5 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = {
+ { { STATE_EPC6 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = {
+ { { STATE_EPC6 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = {
+ { { STATE_EPC6 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = {
+ { { STATE_EXCSAVE6 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = {
+ { { STATE_EXCSAVE6 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = {
+ { { STATE_EXCSAVE6 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = {
+ { { STATE_EPC7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = {
+ { { STATE_EPC7 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = {
+ { { STATE_EPC7 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = {
+ { { STATE_EXCSAVE7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = {
+ { { STATE_EXCSAVE7 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = {
+ { { STATE_EXCSAVE7 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
+ { { STATE_EPS2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
+ { { STATE_EPS2 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
+ { { STATE_EPS2 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = {
+ { { STATE_EPS3 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = {
+ { { STATE_EPS3 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = {
+ { { STATE_EPS3 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = {
+ { { STATE_EPS4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = {
+ { { STATE_EPS4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = {
+ { { STATE_EPS4 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = {
+ { { STATE_EPS5 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = {
+ { { STATE_EPS5 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = {
+ { { STATE_EPS5 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = {
+ { { STATE_EPS6 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = {
+ { { STATE_EPS6 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = {
+ { { STATE_EPS6 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = {
+ { { STATE_EPS7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = {
+ { { STATE_EPS7 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = {
+ { { STATE_EPS7 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
+ { { STATE_EXCVADDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
+ { { STATE_EXCVADDR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
+ { { STATE_EXCVADDR }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
+ { { STATE_DEPC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
+ { { STATE_DEPC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
+ { { STATE_DEPC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
+ { { STATE_EXCCAUSE }, 'i' },
+ { { STATE_XTSYNC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
+ { { STATE_EXCCAUSE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
+ { { STATE_EXCCAUSE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
+ { { STATE_MISC0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
+ { { STATE_MISC0 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
+ { { STATE_MISC0 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
+ { { STATE_MISC1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
+ { { STATE_MISC1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
+ { { STATE_MISC1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = {
+ { { STATE_VECBASE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = {
+ { { STATE_VECBASE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = {
+ { { STATE_VECBASE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_salt_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_mul16_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_mul32_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
+ { { OPERAND_s }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
+ { { STATE_PSWOE }, 'o' },
+ { { STATE_PSCALLINC }, 'o' },
+ { { STATE_PSOWB }, 'o' },
+ { { STATE_PSUM }, 'o' },
+ { { STATE_PSEXCM }, 'o' },
+ { { STATE_PSINTLEVEL }, 'o' },
+ { { STATE_EPC1 }, 'i' },
+ { { STATE_EPC2 }, 'i' },
+ { { STATE_EPC3 }, 'i' },
+ { { STATE_EPC4 }, 'i' },
+ { { STATE_EPC5 }, 'i' },
+ { { STATE_EPC6 }, 'i' },
+ { { STATE_EPC7 }, 'i' },
+ { { STATE_EPS2 }, 'i' },
+ { { STATE_EPS3 }, 'i' },
+ { { STATE_EPS4 }, 'i' },
+ { { STATE_EPS5 }, 'i' },
+ { { STATE_EPS6 }, 'i' },
+ { { STATE_EPS7 }, 'i' },
+ { { STATE_InOCDMode }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
+ { { OPERAND_s }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
+ { { STATE_PSINTLEVEL }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
+ { { STATE_INTERRUPT }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
+ { { STATE_INTENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
+ { { STATE_INTENABLE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
+ { { STATE_INTENABLE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
+ { { OPERAND_imms }, 'i' },
+ { { OPERAND_immt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSINTLEVEL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
+ { { OPERAND_imms }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSINTLEVEL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = {
+ { { STATE_DBREAKA0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = {
+ { { STATE_DBREAKA0 }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = {
+ { { STATE_DBREAKA0 }, 'm' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = {
+ { { STATE_DBREAKC0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = {
+ { { STATE_DBREAKC0 }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = {
+ { { STATE_DBREAKC0 }, 'm' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = {
+ { { STATE_DBREAKA1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = {
+ { { STATE_DBREAKA1 }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = {
+ { { STATE_DBREAKA1 }, 'm' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = {
+ { { STATE_DBREAKC1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = {
+ { { STATE_DBREAKC1 }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = {
+ { { STATE_DBREAKC1 }, 'm' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = {
+ { { STATE_IBREAKA0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = {
+ { { STATE_IBREAKA0 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = {
+ { { STATE_IBREAKA0 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = {
+ { { STATE_IBREAKA1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = {
+ { { STATE_IBREAKA1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = {
+ { { STATE_IBREAKA1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = {
+ { { STATE_IBREAKENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = {
+ { { STATE_IBREAKENABLE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = {
+ { { STATE_IBREAKENABLE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
+ { { STATE_DEBUGCAUSE }, 'i' },
+ { { STATE_DBNUM }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
+ { { STATE_DEBUGCAUSE }, 'o' },
+ { { STATE_DBNUM }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
+ { { STATE_DEBUGCAUSE }, 'm' },
+ { { STATE_DBNUM }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
+ { { STATE_ICOUNT }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_ICOUNT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_ICOUNT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
+ { { STATE_ICOUNTLEVEL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
+ { { STATE_ICOUNTLEVEL }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
+ { { STATE_ICOUNTLEVEL }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
+ { { STATE_DDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_DDR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_DDR }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_args[] = {
+ { { OPERAND_ars }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_InOCDMode }, 'i' },
+ { { STATE_DDR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_args[] = {
+ { { OPERAND_ars }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_stateArgs[] = {
+ { { STATE_InOCDMode }, 'i' },
+ { { STATE_DDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = {
+ { { OPERAND_imms }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = {
+ { { STATE_InOCDMode }, 'm' },
+ { { STATE_EPC6 }, 'i' },
+ { { STATE_PSWOE }, 'o' },
+ { { STATE_PSCALLINC }, 'o' },
+ { { STATE_PSOWB }, 'o' },
+ { { STATE_PSUM }, 'o' },
+ { { STATE_PSEXCM }, 'o' },
+ { { STATE_PSINTLEVEL }, 'o' },
+ { { STATE_EPS6 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = {
+ { { STATE_InOCDMode }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = {
+ { { STATE_CCOUNT }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_CCOUNT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_CCOUNT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = {
+ { { STATE_CCOMPARE0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = {
+ { { STATE_CCOMPARE0 }, 'o' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = {
+ { { STATE_CCOMPARE0 }, 'm' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = {
+ { { STATE_CCOMPARE1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = {
+ { { STATE_CCOMPARE1 }, 'o' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = {
+ { { STATE_CCOMPARE1 }, 'm' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = {
+ { { STATE_CCOMPARE2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = {
+ { { STATE_CCOMPARE2 }, 'o' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = {
+ { { STATE_CCOMPARE2 }, 'm' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_tp7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = {
+ { { OPERAND_art }, 'm' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = {
+ { { STATE_SCOMPARE1 }, 'i' },
+ { { STATE_XTSYNC }, 'i' },
+ { { STATE_SCOMPARE1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = {
+ { { STATE_SCOMPARE1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = {
+ { { STATE_SCOMPARE1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = {
+ { { STATE_SCOMPARE1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = {
+ { { STATE_ATOMCTL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = {
+ { { STATE_ATOMCTL }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = {
+ { { STATE_ATOMCTL }, 'm' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_div_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eraccess_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eraccess_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eraccess_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rer_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wer_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_rur_expstate_args[] = {
+ { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_expstate_stateArgs[] = {
+ { { STATE_EXPSTATE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_expstate_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_expstate_stateArgs[] = {
+ { { STATE_EXPSTATE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_interface Iclass_iclass_READ_IMPWIRE_intfArgs[] = {
+ INTERFACE_IMPWIRE
+};
+
+static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_args[] = {
+ { { OPERAND_bitindex }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_stateArgs[] = {
+ { { STATE_EXPSTATE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_args[] = {
+ { { OPERAND_bitindex }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_stateArgs[] = {
+ { { STATE_EXPSTATE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_stateArgs[] = {
+ { { STATE_EXPSTATE }, 'm' }
+};
+
+static xtensa_iclass_internal iclasses[] = {
+ { 0, 0 /* xt_iclass_excw */,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_rfe */,
+ 2, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_rfde */,
+ 1, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_syscall */,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_call12_args,
+ 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_call8_args,
+ 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_call4_args,
+ 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_callx12_args,
+ 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_callx8_args,
+ 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_callx4_args,
+ 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_entry_args,
+ 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_movsp_args,
+ 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rotw_args,
+ 1, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_retw_args,
+ 5, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_rfwou */,
+ 5, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_l32e_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s32e_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_windowbase_args,
+ 1, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_windowbase_args,
+ 1, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_windowbase_args,
+ 1, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_windowstart_args,
+ 1, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_windowstart_args,
+ 1, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_windowstart_args,
+ 1, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_add_n_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_addi_n_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_bz6_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_ill_n */,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_loadi4_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_mov_n_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_movi_n_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_nopn */,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_retn_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_storei4_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_addi_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_addmi_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_addsub_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bit_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bsi8_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bsi8b_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bsi8u_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bst8_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_bsz12_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_call0_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_callx0_args,
+ 0, 0, 0, 0 },
+ { 4, Iclass_xt_iclass_exti_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_ill */,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_jump_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_jumpx_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_l16ui_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_l16si_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_l32i_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_l32r_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_l8i_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_movi_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_movz_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_neg_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_nop */,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_return_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_simcall */,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s16i_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s32i_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s32nb_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s8i_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_sar_args,
+ 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_sari_args,
+ 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_shifts_args,
+ 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_shiftst_args,
+ 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_shiftt_args,
+ 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_slli_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_srai_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_srli_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_memw */,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_extw */,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_isync */,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_sync */,
+ 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_rsil_args,
+ 6, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_sar_args,
+ 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_sar_args,
+ 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_sar_args,
+ 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_memctl_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_memctl_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_memctl_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_litbase_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_litbase_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_litbase_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_configid0_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_configid0_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_configid1_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ps_args,
+ 6, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ps_args,
+ 6, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ps_args,
+ 6, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc1_args,
+ 1, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc1_args,
+ 1, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc1_args,
+ 1, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave1_args,
+ 1, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave1_args,
+ 1, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave1_args,
+ 1, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc2_args,
+ 1, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc2_args,
+ 1, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc2_args,
+ 1, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave2_args,
+ 1, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave2_args,
+ 1, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave2_args,
+ 1, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc3_args,
+ 1, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc3_args,
+ 1, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc3_args,
+ 1, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave3_args,
+ 1, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave3_args,
+ 1, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave3_args,
+ 1, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc4_args,
+ 1, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc4_args,
+ 1, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc4_args,
+ 1, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave4_args,
+ 1, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave4_args,
+ 1, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave4_args,
+ 1, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc5_args,
+ 1, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc5_args,
+ 1, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc5_args,
+ 1, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave5_args,
+ 1, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave5_args,
+ 1, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave5_args,
+ 1, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc6_args,
+ 1, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc6_args,
+ 1, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc6_args,
+ 1, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave6_args,
+ 1, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave6_args,
+ 1, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave6_args,
+ 1, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc7_args,
+ 1, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc7_args,
+ 1, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc7_args,
+ 1, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave7_args,
+ 1, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave7_args,
+ 1, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave7_args,
+ 1, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps2_args,
+ 1, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps2_args,
+ 1, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps2_args,
+ 1, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps3_args,
+ 1, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps3_args,
+ 1, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps3_args,
+ 1, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps4_args,
+ 1, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps4_args,
+ 1, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps4_args,
+ 1, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps5_args,
+ 1, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps5_args,
+ 1, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps5_args,
+ 1, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps6_args,
+ 1, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps6_args,
+ 1, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps6_args,
+ 1, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps7_args,
+ 1, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps7_args,
+ 1, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps7_args,
+ 1, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excvaddr_args,
+ 1, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excvaddr_args,
+ 1, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excvaddr_args,
+ 1, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_depc_args,
+ 1, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_depc_args,
+ 1, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_depc_args,
+ 1, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_exccause_args,
+ 2, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_exccause_args,
+ 1, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_exccause_args,
+ 1, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_misc0_args,
+ 1, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_misc0_args,
+ 1, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_misc0_args,
+ 1, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_misc1_args,
+ 1, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_misc1_args,
+ 1, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_misc1_args,
+ 1, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_prid_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_vecbase_args,
+ 1, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_vecbase_args,
+ 1, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_vecbase_args,
+ 1, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_salt_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_mul16_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_mul32_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_rfi_args,
+ 20, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wait_args,
+ 1, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_interrupt_args,
+ 1, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_intset_args,
+ 2, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_intclear_args,
+ 2, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_intenable_args,
+ 1, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_intenable_args,
+ 1, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_intenable_args,
+ 1, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_break_args,
+ 2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_break_n_args,
+ 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_dbreaka0_args,
+ 1, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_dbreaka0_args,
+ 2, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_dbreaka0_args,
+ 2, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_dbreakc0_args,
+ 1, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_dbreakc0_args,
+ 2, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_dbreakc0_args,
+ 2, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_dbreaka1_args,
+ 1, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_dbreaka1_args,
+ 2, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_dbreaka1_args,
+ 2, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_dbreakc1_args,
+ 1, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_dbreakc1_args,
+ 2, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_dbreakc1_args,
+ 2, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ibreaka0_args,
+ 1, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ibreaka0_args,
+ 1, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ibreaka0_args,
+ 1, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ibreaka1_args,
+ 1, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ibreaka1_args,
+ 1, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ibreaka1_args,
+ 1, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ibreakenable_args,
+ 1, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ibreakenable_args,
+ 1, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ibreakenable_args,
+ 1, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_debugcause_args,
+ 2, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_debugcause_args,
+ 2, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_debugcause_args,
+ 2, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_icount_args,
+ 1, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_icount_args,
+ 2, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_icount_args,
+ 2, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_icountlevel_args,
+ 1, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_icountlevel_args,
+ 1, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_icountlevel_args,
+ 1, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ddr_args,
+ 1, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ddr_args,
+ 2, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ddr_args,
+ 2, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_lddr32_p_args,
+ 3, Iclass_xt_iclass_lddr32_p_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_sddr32_p_args,
+ 2, Iclass_xt_iclass_sddr32_p_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rfdo_args,
+ 9, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_rfdd */,
+ 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_mmid_args,
+ 1, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ccount_args,
+ 1, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ccount_args,
+ 2, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ccount_args,
+ 2, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ccompare0_args,
+ 1, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ccompare0_args,
+ 2, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ccompare0_args,
+ 2, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ccompare1_args,
+ 1, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ccompare1_args,
+ 2, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ccompare1_args,
+ 2, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ccompare2_args,
+ 1, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ccompare2_args,
+ 2, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ccompare2_args,
+ 2, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_idtlb_args,
+ 1, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_rdtlb_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_wdtlb_args,
+ 1, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_iitlb_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_ritlb_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_witlb_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_minmax_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_nsa_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_sx_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_l32ai_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s32ri_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s32c1i_args,
+ 3, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_scompare1_args,
+ 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_scompare1_args,
+ 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_scompare1_args,
+ 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_atomctl_args,
+ 1, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_atomctl_args,
+ 2, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_atomctl_args,
+ 2, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_div_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eraccess_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eraccess_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eraccess_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_rer_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_wer_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_rur_expstate_args,
+ 1, Iclass_rur_expstate_stateArgs, 0, 0 },
+ { 1, Iclass_wur_expstate_args,
+ 1, Iclass_wur_expstate_stateArgs, 0, 0 },
+ { 1, Iclass_iclass_READ_IMPWIRE_args,
+ 0, 0, 1, Iclass_iclass_READ_IMPWIRE_intfArgs },
+ { 1, Iclass_iclass_SETB_EXPSTATE_args,
+ 1, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 },
+ { 1, Iclass_iclass_CLRB_EXPSTATE_args,
+ 1, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 },
+ { 2, Iclass_iclass_WRMSK_EXPSTATE_args,
+ 1, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 }
+};
+
+enum xtensa_iclass_id {
+ ICLASS_xt_iclass_excw,
+ ICLASS_xt_iclass_rfe,
+ ICLASS_xt_iclass_rfde,
+ ICLASS_xt_iclass_syscall,
+ ICLASS_xt_iclass_call12,
+ ICLASS_xt_iclass_call8,
+ ICLASS_xt_iclass_call4,
+ ICLASS_xt_iclass_callx12,
+ ICLASS_xt_iclass_callx8,
+ ICLASS_xt_iclass_callx4,
+ ICLASS_xt_iclass_entry,
+ ICLASS_xt_iclass_movsp,
+ ICLASS_xt_iclass_rotw,
+ ICLASS_xt_iclass_retw,
+ ICLASS_xt_iclass_rfwou,
+ ICLASS_xt_iclass_l32e,
+ ICLASS_xt_iclass_s32e,
+ ICLASS_xt_iclass_rsr_windowbase,
+ ICLASS_xt_iclass_wsr_windowbase,
+ ICLASS_xt_iclass_xsr_windowbase,
+ ICLASS_xt_iclass_rsr_windowstart,
+ ICLASS_xt_iclass_wsr_windowstart,
+ ICLASS_xt_iclass_xsr_windowstart,
+ ICLASS_xt_iclass_add_n,
+ ICLASS_xt_iclass_addi_n,
+ ICLASS_xt_iclass_bz6,
+ ICLASS_xt_iclass_ill_n,
+ ICLASS_xt_iclass_loadi4,
+ ICLASS_xt_iclass_mov_n,
+ ICLASS_xt_iclass_movi_n,
+ ICLASS_xt_iclass_nopn,
+ ICLASS_xt_iclass_retn,
+ ICLASS_xt_iclass_storei4,
+ ICLASS_xt_iclass_addi,
+ ICLASS_xt_iclass_addmi,
+ ICLASS_xt_iclass_addsub,
+ ICLASS_xt_iclass_bit,
+ ICLASS_xt_iclass_bsi8,
+ ICLASS_xt_iclass_bsi8b,
+ ICLASS_xt_iclass_bsi8u,
+ ICLASS_xt_iclass_bst8,
+ ICLASS_xt_iclass_bsz12,
+ ICLASS_xt_iclass_call0,
+ ICLASS_xt_iclass_callx0,
+ ICLASS_xt_iclass_exti,
+ ICLASS_xt_iclass_ill,
+ ICLASS_xt_iclass_jump,
+ ICLASS_xt_iclass_jumpx,
+ ICLASS_xt_iclass_l16ui,
+ ICLASS_xt_iclass_l16si,
+ ICLASS_xt_iclass_l32i,
+ ICLASS_xt_iclass_l32r,
+ ICLASS_xt_iclass_l8i,
+ ICLASS_xt_iclass_movi,
+ ICLASS_xt_iclass_movz,
+ ICLASS_xt_iclass_neg,
+ ICLASS_xt_iclass_nop,
+ ICLASS_xt_iclass_return,
+ ICLASS_xt_iclass_simcall,
+ ICLASS_xt_iclass_s16i,
+ ICLASS_xt_iclass_s32i,
+ ICLASS_xt_iclass_s32nb,
+ ICLASS_xt_iclass_s8i,
+ ICLASS_xt_iclass_sar,
+ ICLASS_xt_iclass_sari,
+ ICLASS_xt_iclass_shifts,
+ ICLASS_xt_iclass_shiftst,
+ ICLASS_xt_iclass_shiftt,
+ ICLASS_xt_iclass_slli,
+ ICLASS_xt_iclass_srai,
+ ICLASS_xt_iclass_srli,
+ ICLASS_xt_iclass_memw,
+ ICLASS_xt_iclass_extw,
+ ICLASS_xt_iclass_isync,
+ ICLASS_xt_iclass_sync,
+ ICLASS_xt_iclass_rsil,
+ ICLASS_xt_iclass_rsr_sar,
+ ICLASS_xt_iclass_wsr_sar,
+ ICLASS_xt_iclass_xsr_sar,
+ ICLASS_xt_iclass_rsr_memctl,
+ ICLASS_xt_iclass_wsr_memctl,
+ ICLASS_xt_iclass_xsr_memctl,
+ ICLASS_xt_iclass_rsr_litbase,
+ ICLASS_xt_iclass_wsr_litbase,
+ ICLASS_xt_iclass_xsr_litbase,
+ ICLASS_xt_iclass_rsr_configid0,
+ ICLASS_xt_iclass_wsr_configid0,
+ ICLASS_xt_iclass_rsr_configid1,
+ ICLASS_xt_iclass_rsr_ps,
+ ICLASS_xt_iclass_wsr_ps,
+ ICLASS_xt_iclass_xsr_ps,
+ ICLASS_xt_iclass_rsr_epc1,
+ ICLASS_xt_iclass_wsr_epc1,
+ ICLASS_xt_iclass_xsr_epc1,
+ ICLASS_xt_iclass_rsr_excsave1,
+ ICLASS_xt_iclass_wsr_excsave1,
+ ICLASS_xt_iclass_xsr_excsave1,
+ ICLASS_xt_iclass_rsr_epc2,
+ ICLASS_xt_iclass_wsr_epc2,
+ ICLASS_xt_iclass_xsr_epc2,
+ ICLASS_xt_iclass_rsr_excsave2,
+ ICLASS_xt_iclass_wsr_excsave2,
+ ICLASS_xt_iclass_xsr_excsave2,
+ ICLASS_xt_iclass_rsr_epc3,
+ ICLASS_xt_iclass_wsr_epc3,
+ ICLASS_xt_iclass_xsr_epc3,
+ ICLASS_xt_iclass_rsr_excsave3,
+ ICLASS_xt_iclass_wsr_excsave3,
+ ICLASS_xt_iclass_xsr_excsave3,
+ ICLASS_xt_iclass_rsr_epc4,
+ ICLASS_xt_iclass_wsr_epc4,
+ ICLASS_xt_iclass_xsr_epc4,
+ ICLASS_xt_iclass_rsr_excsave4,
+ ICLASS_xt_iclass_wsr_excsave4,
+ ICLASS_xt_iclass_xsr_excsave4,
+ ICLASS_xt_iclass_rsr_epc5,
+ ICLASS_xt_iclass_wsr_epc5,
+ ICLASS_xt_iclass_xsr_epc5,
+ ICLASS_xt_iclass_rsr_excsave5,
+ ICLASS_xt_iclass_wsr_excsave5,
+ ICLASS_xt_iclass_xsr_excsave5,
+ ICLASS_xt_iclass_rsr_epc6,
+ ICLASS_xt_iclass_wsr_epc6,
+ ICLASS_xt_iclass_xsr_epc6,
+ ICLASS_xt_iclass_rsr_excsave6,
+ ICLASS_xt_iclass_wsr_excsave6,
+ ICLASS_xt_iclass_xsr_excsave6,
+ ICLASS_xt_iclass_rsr_epc7,
+ ICLASS_xt_iclass_wsr_epc7,
+ ICLASS_xt_iclass_xsr_epc7,
+ ICLASS_xt_iclass_rsr_excsave7,
+ ICLASS_xt_iclass_wsr_excsave7,
+ ICLASS_xt_iclass_xsr_excsave7,
+ ICLASS_xt_iclass_rsr_eps2,
+ ICLASS_xt_iclass_wsr_eps2,
+ ICLASS_xt_iclass_xsr_eps2,
+ ICLASS_xt_iclass_rsr_eps3,
+ ICLASS_xt_iclass_wsr_eps3,
+ ICLASS_xt_iclass_xsr_eps3,
+ ICLASS_xt_iclass_rsr_eps4,
+ ICLASS_xt_iclass_wsr_eps4,
+ ICLASS_xt_iclass_xsr_eps4,
+ ICLASS_xt_iclass_rsr_eps5,
+ ICLASS_xt_iclass_wsr_eps5,
+ ICLASS_xt_iclass_xsr_eps5,
+ ICLASS_xt_iclass_rsr_eps6,
+ ICLASS_xt_iclass_wsr_eps6,
+ ICLASS_xt_iclass_xsr_eps6,
+ ICLASS_xt_iclass_rsr_eps7,
+ ICLASS_xt_iclass_wsr_eps7,
+ ICLASS_xt_iclass_xsr_eps7,
+ ICLASS_xt_iclass_rsr_excvaddr,
+ ICLASS_xt_iclass_wsr_excvaddr,
+ ICLASS_xt_iclass_xsr_excvaddr,
+ ICLASS_xt_iclass_rsr_depc,
+ ICLASS_xt_iclass_wsr_depc,
+ ICLASS_xt_iclass_xsr_depc,
+ ICLASS_xt_iclass_rsr_exccause,
+ ICLASS_xt_iclass_wsr_exccause,
+ ICLASS_xt_iclass_xsr_exccause,
+ ICLASS_xt_iclass_rsr_misc0,
+ ICLASS_xt_iclass_wsr_misc0,
+ ICLASS_xt_iclass_xsr_misc0,
+ ICLASS_xt_iclass_rsr_misc1,
+ ICLASS_xt_iclass_wsr_misc1,
+ ICLASS_xt_iclass_xsr_misc1,
+ ICLASS_xt_iclass_rsr_prid,
+ ICLASS_xt_iclass_rsr_vecbase,
+ ICLASS_xt_iclass_wsr_vecbase,
+ ICLASS_xt_iclass_xsr_vecbase,
+ ICLASS_xt_iclass_salt,
+ ICLASS_xt_mul16,
+ ICLASS_xt_mul32,
+ ICLASS_xt_iclass_rfi,
+ ICLASS_xt_iclass_wait,
+ ICLASS_xt_iclass_rsr_interrupt,
+ ICLASS_xt_iclass_wsr_intset,
+ ICLASS_xt_iclass_wsr_intclear,
+ ICLASS_xt_iclass_rsr_intenable,
+ ICLASS_xt_iclass_wsr_intenable,
+ ICLASS_xt_iclass_xsr_intenable,
+ ICLASS_xt_iclass_break,
+ ICLASS_xt_iclass_break_n,
+ ICLASS_xt_iclass_rsr_dbreaka0,
+ ICLASS_xt_iclass_wsr_dbreaka0,
+ ICLASS_xt_iclass_xsr_dbreaka0,
+ ICLASS_xt_iclass_rsr_dbreakc0,
+ ICLASS_xt_iclass_wsr_dbreakc0,
+ ICLASS_xt_iclass_xsr_dbreakc0,
+ ICLASS_xt_iclass_rsr_dbreaka1,
+ ICLASS_xt_iclass_wsr_dbreaka1,
+ ICLASS_xt_iclass_xsr_dbreaka1,
+ ICLASS_xt_iclass_rsr_dbreakc1,
+ ICLASS_xt_iclass_wsr_dbreakc1,
+ ICLASS_xt_iclass_xsr_dbreakc1,
+ ICLASS_xt_iclass_rsr_ibreaka0,
+ ICLASS_xt_iclass_wsr_ibreaka0,
+ ICLASS_xt_iclass_xsr_ibreaka0,
+ ICLASS_xt_iclass_rsr_ibreaka1,
+ ICLASS_xt_iclass_wsr_ibreaka1,
+ ICLASS_xt_iclass_xsr_ibreaka1,
+ ICLASS_xt_iclass_rsr_ibreakenable,
+ ICLASS_xt_iclass_wsr_ibreakenable,
+ ICLASS_xt_iclass_xsr_ibreakenable,
+ ICLASS_xt_iclass_rsr_debugcause,
+ ICLASS_xt_iclass_wsr_debugcause,
+ ICLASS_xt_iclass_xsr_debugcause,
+ ICLASS_xt_iclass_rsr_icount,
+ ICLASS_xt_iclass_wsr_icount,
+ ICLASS_xt_iclass_xsr_icount,
+ ICLASS_xt_iclass_rsr_icountlevel,
+ ICLASS_xt_iclass_wsr_icountlevel,
+ ICLASS_xt_iclass_xsr_icountlevel,
+ ICLASS_xt_iclass_rsr_ddr,
+ ICLASS_xt_iclass_wsr_ddr,
+ ICLASS_xt_iclass_xsr_ddr,
+ ICLASS_xt_iclass_lddr32_p,
+ ICLASS_xt_iclass_sddr32_p,
+ ICLASS_xt_iclass_rfdo,
+ ICLASS_xt_iclass_rfdd,
+ ICLASS_xt_iclass_wsr_mmid,
+ ICLASS_xt_iclass_rsr_ccount,
+ ICLASS_xt_iclass_wsr_ccount,
+ ICLASS_xt_iclass_xsr_ccount,
+ ICLASS_xt_iclass_rsr_ccompare0,
+ ICLASS_xt_iclass_wsr_ccompare0,
+ ICLASS_xt_iclass_xsr_ccompare0,
+ ICLASS_xt_iclass_rsr_ccompare1,
+ ICLASS_xt_iclass_wsr_ccompare1,
+ ICLASS_xt_iclass_xsr_ccompare1,
+ ICLASS_xt_iclass_rsr_ccompare2,
+ ICLASS_xt_iclass_wsr_ccompare2,
+ ICLASS_xt_iclass_xsr_ccompare2,
+ ICLASS_xt_iclass_idtlb,
+ ICLASS_xt_iclass_rdtlb,
+ ICLASS_xt_iclass_wdtlb,
+ ICLASS_xt_iclass_iitlb,
+ ICLASS_xt_iclass_ritlb,
+ ICLASS_xt_iclass_witlb,
+ ICLASS_xt_iclass_minmax,
+ ICLASS_xt_iclass_nsa,
+ ICLASS_xt_iclass_sx,
+ ICLASS_xt_iclass_l32ai,
+ ICLASS_xt_iclass_s32ri,
+ ICLASS_xt_iclass_s32c1i,
+ ICLASS_xt_iclass_rsr_scompare1,
+ ICLASS_xt_iclass_wsr_scompare1,
+ ICLASS_xt_iclass_xsr_scompare1,
+ ICLASS_xt_iclass_rsr_atomctl,
+ ICLASS_xt_iclass_wsr_atomctl,
+ ICLASS_xt_iclass_xsr_atomctl,
+ ICLASS_xt_iclass_div,
+ ICLASS_xt_iclass_rsr_eraccess,
+ ICLASS_xt_iclass_wsr_eraccess,
+ ICLASS_xt_iclass_xsr_eraccess,
+ ICLASS_xt_iclass_rer,
+ ICLASS_xt_iclass_wer,
+ ICLASS_rur_expstate,
+ ICLASS_wur_expstate,
+ ICLASS_iclass_READ_IMPWIRE,
+ ICLASS_iclass_SETB_EXPSTATE,
+ ICLASS_iclass_CLRB_EXPSTATE,
+ ICLASS_iclass_WRMSK_EXPSTATE
+};
+
+
+/* Opcode encodings. */
+
+static void
+Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2080;
+}
+
+static void
+Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3000;
+}
+
+static void
+Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3200;
+}
+
+static void
+Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5000;
+}
+
+static void
+Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x35;
+}
+
+static void
+Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x25;
+}
+
+static void
+Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x15;
+}
+
+static void
+Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf0;
+}
+
+static void
+Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe0;
+}
+
+static void
+Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd0;
+}
+
+static void
+Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x36;
+}
+
+static void
+Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1000;
+}
+
+static void
+Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x408000;
+}
+
+static void
+Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x90;
+}
+
+static void
+Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf01d;
+}
+
+static void
+Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3400;
+}
+
+static void
+Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3500;
+}
+
+static void
+Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x90000;
+}
+
+static void
+Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x490000;
+}
+
+static void
+Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x34800;
+}
+
+static void
+Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x134800;
+}
+
+static void
+Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x614800;
+}
+
+static void
+Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x34900;
+}
+
+static void
+Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x134900;
+}
+
+static void
+Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x614900;
+}
+
+static void
+Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa;
+}
+
+static void
+Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb;
+}
+
+static void
+Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8c;
+}
+
+static void
+Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xcc;
+}
+
+static void
+Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf06d;
+}
+
+static void
+Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8;
+}
+
+static void
+Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd;
+}
+
+static void
+Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc;
+}
+
+static void
+Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf03d;
+}
+
+static void
+Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf00d;
+}
+
+static void
+Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9;
+}
+
+static void
+Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc002;
+}
+
+static void
+Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd002;
+}
+
+static void
+Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x800000;
+}
+
+static void
+Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc00000;
+}
+
+static void
+Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x900000;
+}
+
+static void
+Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa00000;
+}
+
+static void
+Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb00000;
+}
+
+static void
+Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd00000;
+}
+
+static void
+Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe00000;
+}
+
+static void
+Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf00000;
+}
+
+static void
+Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x100000;
+}
+
+static void
+Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200000;
+}
+
+static void
+Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x300000;
+}
+
+static void
+Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x26;
+}
+
+static void
+Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x66;
+}
+
+static void
+Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe6;
+}
+
+static void
+Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa6;
+}
+
+static void
+Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6007;
+}
+
+static void
+Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe007;
+}
+
+static void
+Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf6;
+}
+
+static void
+Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb6;
+}
+
+static void
+Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1007;
+}
+
+static void
+Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9007;
+}
+
+static void
+Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa007;
+}
+
+static void
+Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2007;
+}
+
+static void
+Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb007;
+}
+
+static void
+Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3007;
+}
+
+static void
+Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8007;
+}
+
+static void
+Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7;
+}
+
+static void
+Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4007;
+}
+
+static void
+Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc007;
+}
+
+static void
+Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5007;
+}
+
+static void
+Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd007;
+}
+
+static void
+Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x16;
+}
+
+static void
+Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x56;
+}
+
+static void
+Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd6;
+}
+
+static void
+Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x96;
+}
+
+static void
+Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5;
+}
+
+static void
+Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc0;
+}
+
+static void
+Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40000;
+}
+
+static void
+Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0;
+}
+
+static void
+Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6;
+}
+
+static void
+Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa0;
+}
+
+static void
+Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1002;
+}
+
+static void
+Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9002;
+}
+
+static void
+Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2002;
+}
+
+static void
+Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1;
+}
+
+static void
+Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2;
+}
+
+static void
+Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa002;
+}
+
+static void
+Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x830000;
+}
+
+static void
+Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x930000;
+}
+
+static void
+Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa30000;
+}
+
+static void
+Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb30000;
+}
+
+static void
+Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x600000;
+}
+
+static void
+Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x600100;
+}
+
+static void
+Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x20f0;
+}
+
+static void
+Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x80;
+}
+
+static void
+Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5100;
+}
+
+static void
+Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5002;
+}
+
+static void
+Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6002;
+}
+
+static void
+Opcode_s32nb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x590000;
+}
+
+static void
+Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4002;
+}
+
+static void
+Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400000;
+}
+
+static void
+Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x401000;
+}
+
+static void
+Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x402000;
+}
+
+static void
+Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x403000;
+}
+
+static void
+Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x404000;
+}
+
+static void
+Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa10000;
+}
+
+static void
+Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x810000;
+}
+
+static void
+Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x910000;
+}
+
+static void
+Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb10000;
+}
+
+static void
+Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x10000;
+}
+
+static void
+Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x210000;
+}
+
+static void
+Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x410000;
+}
+
+static void
+Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x20c0;
+}
+
+static void
+Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x20d0;
+}
+
+static void
+Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2000;
+}
+
+static void
+Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2010;
+}
+
+static void
+Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2020;
+}
+
+static void
+Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2030;
+}
+
+static void
+Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6000;
+}
+
+static void
+Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30300;
+}
+
+static void
+Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x130300;
+}
+
+static void
+Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x610300;
+}
+
+static void
+Opcode_rsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x36100;
+}
+
+static void
+Opcode_wsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x136100;
+}
+
+static void
+Opcode_xsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x616100;
+}
+
+static void
+Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30500;
+}
+
+static void
+Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x130500;
+}
+
+static void
+Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x610500;
+}
+
+static void
+Opcode_rsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b000;
+}
+
+static void
+Opcode_wsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b000;
+}
+
+static void
+Opcode_rsr_configid1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d000;
+}
+
+static void
+Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e600;
+}
+
+static void
+Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e600;
+}
+
+static void
+Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61e600;
+}
+
+static void
+Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b100;
+}
+
+static void
+Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b100;
+}
+
+static void
+Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61b100;
+}
+
+static void
+Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d100;
+}
+
+static void
+Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13d100;
+}
+
+static void
+Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61d100;
+}
+
+static void
+Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b200;
+}
+
+static void
+Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b200;
+}
+
+static void
+Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61b200;
+}
+
+static void
+Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d200;
+}
+
+static void
+Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13d200;
+}
+
+static void
+Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61d200;
+}
+
+static void
+Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b300;
+}
+
+static void
+Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b300;
+}
+
+static void
+Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61b300;
+}
+
+static void
+Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d300;
+}
+
+static void
+Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13d300;
+}
+
+static void
+Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61d300;
+}
+
+static void
+Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b400;
+}
+
+static void
+Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b400;
+}
+
+static void
+Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61b400;
+}
+
+static void
+Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d400;
+}
+
+static void
+Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13d400;
+}
+
+static void
+Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61d400;
+}
+
+static void
+Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b500;
+}
+
+static void
+Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b500;
+}
+
+static void
+Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61b500;
+}
+
+static void
+Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d500;
+}
+
+static void
+Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13d500;
+}
+
+static void
+Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61d500;
+}
+
+static void
+Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b600;
+}
+
+static void
+Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b600;
+}
+
+static void
+Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61b600;
+}
+
+static void
+Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d600;
+}
+
+static void
+Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13d600;
+}
+
+static void
+Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61d600;
+}
+
+static void
+Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b700;
+}
+
+static void
+Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b700;
+}
+
+static void
+Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61b700;
+}
+
+static void
+Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d700;
+}
+
+static void
+Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13d700;
+}
+
+static void
+Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61d700;
+}
+
+static void
+Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c200;
+}
+
+static void
+Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13c200;
+}
+
+static void
+Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61c200;
+}
+
+static void
+Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c300;
+}
+
+static void
+Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13c300;
+}
+
+static void
+Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61c300;
+}
+
+static void
+Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c400;
+}
+
+static void
+Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13c400;
+}
+
+static void
+Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61c400;
+}
+
+static void
+Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c500;
+}
+
+static void
+Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13c500;
+}
+
+static void
+Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61c500;
+}
+
+static void
+Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c600;
+}
+
+static void
+Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13c600;
+}
+
+static void
+Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61c600;
+}
+
+static void
+Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c700;
+}
+
+static void
+Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13c700;
+}
+
+static void
+Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61c700;
+}
+
+static void
+Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3ee00;
+}
+
+static void
+Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13ee00;
+}
+
+static void
+Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61ee00;
+}
+
+static void
+Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c000;
+}
+
+static void
+Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13c000;
+}
+
+static void
+Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61c000;
+}
+
+static void
+Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e800;
+}
+
+static void
+Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e800;
+}
+
+static void
+Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61e800;
+}
+
+static void
+Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3f400;
+}
+
+static void
+Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13f400;
+}
+
+static void
+Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61f400;
+}
+
+static void
+Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3f500;
+}
+
+static void
+Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13f500;
+}
+
+static void
+Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61f500;
+}
+
+static void
+Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3eb00;
+}
+
+static void
+Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e700;
+}
+
+static void
+Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e700;
+}
+
+static void
+Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61e700;
+}
+
+static void
+Opcode_salt_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x720000;
+}
+
+static void
+Opcode_saltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x620000;
+}
+
+static void
+Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc10000;
+}
+
+static void
+Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd10000;
+}
+
+static void
+Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x820000;
+}
+
+static void
+Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3010;
+}
+
+static void
+Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7000;
+}
+
+static void
+Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e200;
+}
+
+static void
+Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e200;
+}
+
+static void
+Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e300;
+}
+
+static void
+Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e400;
+}
+
+static void
+Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e400;
+}
+
+static void
+Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61e400;
+}
+
+static void
+Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000;
+}
+
+static void
+Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf02d;
+}
+
+static void
+Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x39000;
+}
+
+static void
+Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x139000;
+}
+
+static void
+Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x619000;
+}
+
+static void
+Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3a000;
+}
+
+static void
+Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13a000;
+}
+
+static void
+Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61a000;
+}
+
+static void
+Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x39100;
+}
+
+static void
+Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x139100;
+}
+
+static void
+Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x619100;
+}
+
+static void
+Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3a100;
+}
+
+static void
+Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13a100;
+}
+
+static void
+Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61a100;
+}
+
+static void
+Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x38000;
+}
+
+static void
+Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x138000;
+}
+
+static void
+Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x618000;
+}
+
+static void
+Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x38100;
+}
+
+static void
+Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x138100;
+}
+
+static void
+Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x618100;
+}
+
+static void
+Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x36000;
+}
+
+static void
+Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x136000;
+}
+
+static void
+Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x616000;
+}
+
+static void
+Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e900;
+}
+
+static void
+Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e900;
+}
+
+static void
+Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61e900;
+}
+
+static void
+Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3ec00;
+}
+
+static void
+Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13ec00;
+}
+
+static void
+Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61ec00;
+}
+
+static void
+Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3ed00;
+}
+
+static void
+Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13ed00;
+}
+
+static void
+Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61ed00;
+}
+
+static void
+Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x36800;
+}
+
+static void
+Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x136800;
+}
+
+static void
+Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x616800;
+}
+
+static void
+Opcode_lddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x70e0;
+}
+
+static void
+Opcode_sddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x70f0;
+}
+
+static void
+Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf1e000;
+}
+
+static void
+Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf1e010;
+}
+
+static void
+Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x135900;
+}
+
+static void
+Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3ea00;
+}
+
+static void
+Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13ea00;
+}
+
+static void
+Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61ea00;
+}
+
+static void
+Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3f000;
+}
+
+static void
+Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13f000;
+}
+
+static void
+Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61f000;
+}
+
+static void
+Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3f100;
+}
+
+static void
+Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13f100;
+}
+
+static void
+Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61f100;
+}
+
+static void
+Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3f200;
+}
+
+static void
+Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13f200;
+}
+
+static void
+Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61f200;
+}
+
+static void
+Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50c000;
+}
+
+static void
+Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50d000;
+}
+
+static void
+Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50b000;
+}
+
+static void
+Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50f000;
+}
+
+static void
+Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50e000;
+}
+
+static void
+Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x504000;
+}
+
+static void
+Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x505000;
+}
+
+static void
+Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x503000;
+}
+
+static void
+Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x507000;
+}
+
+static void
+Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x506000;
+}
+
+static void
+Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x430000;
+}
+
+static void
+Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x530000;
+}
+
+static void
+Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x630000;
+}
+
+static void
+Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x730000;
+}
+
+static void
+Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40e000;
+}
+
+static void
+Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40f000;
+}
+
+static void
+Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x230000;
+}
+
+static void
+Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb002;
+}
+
+static void
+Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf002;
+}
+
+static void
+Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe002;
+}
+
+static void
+Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30c00;
+}
+
+static void
+Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x130c00;
+}
+
+static void
+Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x610c00;
+}
+
+static void
+Opcode_rsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x36300;
+}
+
+static void
+Opcode_wsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x136300;
+}
+
+static void
+Opcode_xsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x616300;
+}
+
+static void
+Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc20000;
+}
+
+static void
+Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd20000;
+}
+
+static void
+Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe20000;
+}
+
+static void
+Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf20000;
+}
+
+static void
+Opcode_rsr_eraccess_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x35f00;
+}
+
+static void
+Opcode_wsr_eraccess_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x135f00;
+}
+
+static void
+Opcode_xsr_eraccess_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x615f00;
+}
+
+static void
+Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x406000;
+}
+
+static void
+Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x407000;
+}
+
+static void
+Opcode_rur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe30e60;
+}
+
+static void
+Opcode_wur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf3e600;
+}
+
+static void
+Opcode_read_impwire_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe0000;
+}
+
+static void
+Opcode_setb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe1000;
+}
+
+static void
+Opcode_clrb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe1200;
+}
+
+static void
+Opcode_wrmsk_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe2000;
+}
+
+static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = {
+ Opcode_excw_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = {
+ Opcode_rfe_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = {
+ Opcode_rfde_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = {
+ Opcode_syscall_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = {
+ Opcode_call12_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = {
+ Opcode_call8_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = {
+ Opcode_call4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = {
+ Opcode_callx12_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = {
+ Opcode_callx8_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = {
+ Opcode_callx4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = {
+ Opcode_entry_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = {
+ Opcode_movsp_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = {
+ Opcode_rotw_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = {
+ Opcode_retw_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = {
+ 0, 0, Opcode_retw_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = {
+ Opcode_rfwo_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = {
+ Opcode_rfwu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = {
+ Opcode_l32e_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = {
+ Opcode_s32e_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = {
+ Opcode_rsr_windowbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = {
+ Opcode_wsr_windowbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = {
+ Opcode_xsr_windowbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = {
+ Opcode_rsr_windowstart_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = {
+ Opcode_wsr_windowstart_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = {
+ Opcode_xsr_windowstart_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = {
+ 0, Opcode_add_n_Slot_inst16a_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = {
+ 0, Opcode_addi_n_Slot_inst16a_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = {
+ 0, 0, Opcode_beqz_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = {
+ 0, 0, Opcode_bnez_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = {
+ 0, 0, Opcode_ill_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = {
+ 0, Opcode_l32i_n_Slot_inst16a_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = {
+ 0, 0, Opcode_mov_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = {
+ 0, 0, Opcode_movi_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = {
+ 0, 0, Opcode_nop_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = {
+ 0, 0, Opcode_ret_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = {
+ 0, Opcode_s32i_n_Slot_inst16a_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = {
+ Opcode_addi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = {
+ Opcode_addmi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = {
+ Opcode_add_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = {
+ Opcode_sub_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = {
+ Opcode_addx2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = {
+ Opcode_addx4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = {
+ Opcode_addx8_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = {
+ Opcode_subx2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = {
+ Opcode_subx4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = {
+ Opcode_subx8_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = {
+ Opcode_and_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = {
+ Opcode_or_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = {
+ Opcode_xor_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = {
+ Opcode_beqi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = {
+ Opcode_bnei_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = {
+ Opcode_bgei_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = {
+ Opcode_blti_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = {
+ Opcode_bbci_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = {
+ Opcode_bbsi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = {
+ Opcode_bgeui_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = {
+ Opcode_bltui_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = {
+ Opcode_beq_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = {
+ Opcode_bne_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = {
+ Opcode_bge_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = {
+ Opcode_blt_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = {
+ Opcode_bgeu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = {
+ Opcode_bltu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = {
+ Opcode_bany_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = {
+ Opcode_bnone_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = {
+ Opcode_ball_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = {
+ Opcode_bnall_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = {
+ Opcode_bbc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = {
+ Opcode_bbs_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = {
+ Opcode_beqz_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = {
+ Opcode_bnez_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = {
+ Opcode_bgez_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = {
+ Opcode_bltz_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = {
+ Opcode_call0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = {
+ Opcode_callx0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = {
+ Opcode_extui_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = {
+ Opcode_ill_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = {
+ Opcode_j_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = {
+ Opcode_jx_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = {
+ Opcode_l16ui_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = {
+ Opcode_l16si_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = {
+ Opcode_l32i_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = {
+ Opcode_l32r_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = {
+ Opcode_l8ui_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = {
+ Opcode_movi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = {
+ Opcode_moveqz_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = {
+ Opcode_movnez_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = {
+ Opcode_movltz_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = {
+ Opcode_movgez_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = {
+ Opcode_neg_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = {
+ Opcode_abs_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = {
+ Opcode_nop_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = {
+ Opcode_ret_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = {
+ Opcode_simcall_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = {
+ Opcode_s16i_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = {
+ Opcode_s32i_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s32nb_encode_fns[] = {
+ Opcode_s32nb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = {
+ Opcode_s8i_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = {
+ Opcode_ssr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = {
+ Opcode_ssl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = {
+ Opcode_ssa8l_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = {
+ Opcode_ssa8b_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = {
+ Opcode_ssai_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = {
+ Opcode_sll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = {
+ Opcode_src_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = {
+ Opcode_srl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = {
+ Opcode_sra_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = {
+ Opcode_slli_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = {
+ Opcode_srai_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = {
+ Opcode_srli_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = {
+ Opcode_memw_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = {
+ Opcode_extw_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = {
+ Opcode_isync_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = {
+ Opcode_rsync_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = {
+ Opcode_esync_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = {
+ Opcode_dsync_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = {
+ Opcode_rsil_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = {
+ Opcode_rsr_sar_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = {
+ Opcode_wsr_sar_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = {
+ Opcode_xsr_sar_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_memctl_encode_fns[] = {
+ Opcode_rsr_memctl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_memctl_encode_fns[] = {
+ Opcode_wsr_memctl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_memctl_encode_fns[] = {
+ Opcode_xsr_memctl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = {
+ Opcode_rsr_litbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = {
+ Opcode_wsr_litbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = {
+ Opcode_xsr_litbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_configid0_encode_fns[] = {
+ Opcode_rsr_configid0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_configid0_encode_fns[] = {
+ Opcode_wsr_configid0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_configid1_encode_fns[] = {
+ Opcode_rsr_configid1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = {
+ Opcode_rsr_ps_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = {
+ Opcode_wsr_ps_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = {
+ Opcode_xsr_ps_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = {
+ Opcode_rsr_epc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = {
+ Opcode_wsr_epc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = {
+ Opcode_xsr_epc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = {
+ Opcode_rsr_excsave1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = {
+ Opcode_wsr_excsave1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = {
+ Opcode_xsr_excsave1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = {
+ Opcode_rsr_epc2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = {
+ Opcode_wsr_epc2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = {
+ Opcode_xsr_epc2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = {
+ Opcode_rsr_excsave2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = {
+ Opcode_wsr_excsave2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = {
+ Opcode_xsr_excsave2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = {
+ Opcode_rsr_epc3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = {
+ Opcode_wsr_epc3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = {
+ Opcode_xsr_epc3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = {
+ Opcode_rsr_excsave3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = {
+ Opcode_wsr_excsave3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = {
+ Opcode_xsr_excsave3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = {
+ Opcode_rsr_epc4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = {
+ Opcode_wsr_epc4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = {
+ Opcode_xsr_epc4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = {
+ Opcode_rsr_excsave4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = {
+ Opcode_wsr_excsave4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = {
+ Opcode_xsr_excsave4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = {
+ Opcode_rsr_epc5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = {
+ Opcode_wsr_epc5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = {
+ Opcode_xsr_epc5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = {
+ Opcode_rsr_excsave5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = {
+ Opcode_wsr_excsave5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = {
+ Opcode_xsr_excsave5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = {
+ Opcode_rsr_epc6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = {
+ Opcode_wsr_epc6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = {
+ Opcode_xsr_epc6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = {
+ Opcode_rsr_excsave6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = {
+ Opcode_wsr_excsave6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = {
+ Opcode_xsr_excsave6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = {
+ Opcode_rsr_epc7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = {
+ Opcode_wsr_epc7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = {
+ Opcode_xsr_epc7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = {
+ Opcode_rsr_excsave7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = {
+ Opcode_wsr_excsave7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = {
+ Opcode_xsr_excsave7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = {
+ Opcode_rsr_eps2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = {
+ Opcode_wsr_eps2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = {
+ Opcode_xsr_eps2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = {
+ Opcode_rsr_eps3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = {
+ Opcode_wsr_eps3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = {
+ Opcode_xsr_eps3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = {
+ Opcode_rsr_eps4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = {
+ Opcode_wsr_eps4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = {
+ Opcode_xsr_eps4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = {
+ Opcode_rsr_eps5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = {
+ Opcode_wsr_eps5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = {
+ Opcode_xsr_eps5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = {
+ Opcode_rsr_eps6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = {
+ Opcode_wsr_eps6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = {
+ Opcode_xsr_eps6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = {
+ Opcode_rsr_eps7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = {
+ Opcode_wsr_eps7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = {
+ Opcode_xsr_eps7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = {
+ Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = {
+ Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = {
+ Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = {
+ Opcode_rsr_depc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = {
+ Opcode_wsr_depc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = {
+ Opcode_xsr_depc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = {
+ Opcode_rsr_exccause_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = {
+ Opcode_wsr_exccause_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = {
+ Opcode_xsr_exccause_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = {
+ Opcode_rsr_misc0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = {
+ Opcode_wsr_misc0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = {
+ Opcode_xsr_misc0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = {
+ Opcode_rsr_misc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = {
+ Opcode_wsr_misc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = {
+ Opcode_xsr_misc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = {
+ Opcode_rsr_prid_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = {
+ Opcode_rsr_vecbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = {
+ Opcode_wsr_vecbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = {
+ Opcode_xsr_vecbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_salt_encode_fns[] = {
+ Opcode_salt_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_saltu_encode_fns[] = {
+ Opcode_saltu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = {
+ Opcode_mul16u_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = {
+ Opcode_mul16s_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = {
+ Opcode_mull_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = {
+ Opcode_rfi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = {
+ Opcode_waiti_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = {
+ Opcode_rsr_interrupt_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = {
+ Opcode_wsr_intset_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = {
+ Opcode_wsr_intclear_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = {
+ Opcode_rsr_intenable_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = {
+ Opcode_wsr_intenable_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = {
+ Opcode_xsr_intenable_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = {
+ Opcode_break_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = {
+ 0, 0, Opcode_break_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = {
+ Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = {
+ Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = {
+ Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = {
+ Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = {
+ Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = {
+ Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = {
+ Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = {
+ Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = {
+ Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = {
+ Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = {
+ Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = {
+ Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = {
+ Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = {
+ Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = {
+ Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = {
+ Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = {
+ Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = {
+ Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = {
+ Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = {
+ Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = {
+ Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = {
+ Opcode_rsr_debugcause_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = {
+ Opcode_wsr_debugcause_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = {
+ Opcode_xsr_debugcause_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = {
+ Opcode_rsr_icount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = {
+ Opcode_wsr_icount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = {
+ Opcode_xsr_icount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = {
+ Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = {
+ Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = {
+ Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = {
+ Opcode_rsr_ddr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = {
+ Opcode_wsr_ddr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = {
+ Opcode_xsr_ddr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_lddr32_p_encode_fns[] = {
+ Opcode_lddr32_p_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sddr32_p_encode_fns[] = {
+ Opcode_sddr32_p_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = {
+ Opcode_rfdo_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = {
+ Opcode_rfdd_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = {
+ Opcode_wsr_mmid_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = {
+ Opcode_rsr_ccount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = {
+ Opcode_wsr_ccount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = {
+ Opcode_xsr_ccount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = {
+ Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = {
+ Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = {
+ Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = {
+ Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = {
+ Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = {
+ Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = {
+ Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = {
+ Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = {
+ Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = {
+ Opcode_idtlb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = {
+ Opcode_pdtlb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = {
+ Opcode_rdtlb0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = {
+ Opcode_rdtlb1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = {
+ Opcode_wdtlb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = {
+ Opcode_iitlb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = {
+ Opcode_pitlb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = {
+ Opcode_ritlb0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = {
+ Opcode_ritlb1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = {
+ Opcode_witlb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = {
+ Opcode_min_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = {
+ Opcode_max_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = {
+ Opcode_minu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = {
+ Opcode_maxu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = {
+ Opcode_nsa_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = {
+ Opcode_nsau_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = {
+ Opcode_sext_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = {
+ Opcode_l32ai_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = {
+ Opcode_s32ri_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = {
+ Opcode_s32c1i_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = {
+ Opcode_rsr_scompare1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = {
+ Opcode_wsr_scompare1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = {
+ Opcode_xsr_scompare1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = {
+ Opcode_rsr_atomctl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = {
+ Opcode_wsr_atomctl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = {
+ Opcode_xsr_atomctl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = {
+ Opcode_quou_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = {
+ Opcode_quos_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = {
+ Opcode_remu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = {
+ Opcode_rems_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_eraccess_encode_fns[] = {
+ Opcode_rsr_eraccess_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_eraccess_encode_fns[] = {
+ Opcode_wsr_eraccess_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_eraccess_encode_fns[] = {
+ Opcode_xsr_eraccess_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = {
+ Opcode_rer_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = {
+ Opcode_wer_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rur_expstate_encode_fns[] = {
+ Opcode_rur_expstate_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wur_expstate_encode_fns[] = {
+ Opcode_wur_expstate_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_read_impwire_encode_fns[] = {
+ Opcode_read_impwire_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_setb_expstate_encode_fns[] = {
+ Opcode_setb_expstate_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_clrb_expstate_encode_fns[] = {
+ Opcode_clrb_expstate_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wrmsk_expstate_encode_fns[] = {
+ Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0
+};
+
+
+
+
+
+/* Opcode table. */
+
+static xtensa_opcode_internal opcodes[] = {
+ { "excw", ICLASS_xt_iclass_excw,
+ 0,
+ Opcode_excw_encode_fns, 0, 0 },
+ { "rfe", ICLASS_xt_iclass_rfe,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfe_encode_fns, 0, 0 },
+ { "rfde", ICLASS_xt_iclass_rfde,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfde_encode_fns, 0, 0 },
+ { "syscall", ICLASS_xt_iclass_syscall,
+ 0,
+ Opcode_syscall_encode_fns, 0, 0 },
+ { "call12", ICLASS_xt_iclass_call12,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_call12_encode_fns, 0, 0 },
+ { "call8", ICLASS_xt_iclass_call8,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_call8_encode_fns, 0, 0 },
+ { "call4", ICLASS_xt_iclass_call4,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_call4_encode_fns, 0, 0 },
+ { "callx12", ICLASS_xt_iclass_callx12,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_callx12_encode_fns, 0, 0 },
+ { "callx8", ICLASS_xt_iclass_callx8,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_callx8_encode_fns, 0, 0 },
+ { "callx4", ICLASS_xt_iclass_callx4,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_callx4_encode_fns, 0, 0 },
+ { "entry", ICLASS_xt_iclass_entry,
+ 0,
+ Opcode_entry_encode_fns, 0, 0 },
+ { "movsp", ICLASS_xt_iclass_movsp,
+ 0,
+ Opcode_movsp_encode_fns, 0, 0 },
+ { "rotw", ICLASS_xt_iclass_rotw,
+ 0,
+ Opcode_rotw_encode_fns, 0, 0 },
+ { "retw", ICLASS_xt_iclass_retw,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_retw_encode_fns, 0, 0 },
+ { "retw.n", ICLASS_xt_iclass_retw,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_retw_n_encode_fns, 0, 0 },
+ { "rfwo", ICLASS_xt_iclass_rfwou,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfwo_encode_fns, 0, 0 },
+ { "rfwu", ICLASS_xt_iclass_rfwou,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfwu_encode_fns, 0, 0 },
+ { "l32e", ICLASS_xt_iclass_l32e,
+ 0,
+ Opcode_l32e_encode_fns, 0, 0 },
+ { "s32e", ICLASS_xt_iclass_s32e,
+ 0,
+ Opcode_s32e_encode_fns, 0, 0 },
+ { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase,
+ 0,
+ Opcode_rsr_windowbase_encode_fns, 0, 0 },
+ { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase,
+ 0,
+ Opcode_wsr_windowbase_encode_fns, 0, 0 },
+ { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase,
+ 0,
+ Opcode_xsr_windowbase_encode_fns, 0, 0 },
+ { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart,
+ 0,
+ Opcode_rsr_windowstart_encode_fns, 0, 0 },
+ { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart,
+ 0,
+ Opcode_wsr_windowstart_encode_fns, 0, 0 },
+ { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart,
+ 0,
+ Opcode_xsr_windowstart_encode_fns, 0, 0 },
+ { "add.n", ICLASS_xt_iclass_add_n,
+ 0,
+ Opcode_add_n_encode_fns, 0, 0 },
+ { "addi.n", ICLASS_xt_iclass_addi_n,
+ 0,
+ Opcode_addi_n_encode_fns, 0, 0 },
+ { "beqz.n", ICLASS_xt_iclass_bz6,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_beqz_n_encode_fns, 0, 0 },
+ { "bnez.n", ICLASS_xt_iclass_bz6,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bnez_n_encode_fns, 0, 0 },
+ { "ill.n", ICLASS_xt_iclass_ill_n,
+ 0,
+ Opcode_ill_n_encode_fns, 0, 0 },
+ { "l32i.n", ICLASS_xt_iclass_loadi4,
+ 0,
+ Opcode_l32i_n_encode_fns, 0, 0 },
+ { "mov.n", ICLASS_xt_iclass_mov_n,
+ 0,
+ Opcode_mov_n_encode_fns, 0, 0 },
+ { "movi.n", ICLASS_xt_iclass_movi_n,
+ 0,
+ Opcode_movi_n_encode_fns, 0, 0 },
+ { "nop.n", ICLASS_xt_iclass_nopn,
+ 0,
+ Opcode_nop_n_encode_fns, 0, 0 },
+ { "ret.n", ICLASS_xt_iclass_retn,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_ret_n_encode_fns, 0, 0 },
+ { "s32i.n", ICLASS_xt_iclass_storei4,
+ 0,
+ Opcode_s32i_n_encode_fns, 0, 0 },
+ { "addi", ICLASS_xt_iclass_addi,
+ 0,
+ Opcode_addi_encode_fns, 0, 0 },
+ { "addmi", ICLASS_xt_iclass_addmi,
+ 0,
+ Opcode_addmi_encode_fns, 0, 0 },
+ { "add", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_add_encode_fns, 0, 0 },
+ { "sub", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_sub_encode_fns, 0, 0 },
+ { "addx2", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_addx2_encode_fns, 0, 0 },
+ { "addx4", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_addx4_encode_fns, 0, 0 },
+ { "addx8", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_addx8_encode_fns, 0, 0 },
+ { "subx2", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_subx2_encode_fns, 0, 0 },
+ { "subx4", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_subx4_encode_fns, 0, 0 },
+ { "subx8", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_subx8_encode_fns, 0, 0 },
+ { "and", ICLASS_xt_iclass_bit,
+ 0,
+ Opcode_and_encode_fns, 0, 0 },
+ { "or", ICLASS_xt_iclass_bit,
+ 0,
+ Opcode_or_encode_fns, 0, 0 },
+ { "xor", ICLASS_xt_iclass_bit,
+ 0,
+ Opcode_xor_encode_fns, 0, 0 },
+ { "beqi", ICLASS_xt_iclass_bsi8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_beqi_encode_fns, 0, 0 },
+ { "bnei", ICLASS_xt_iclass_bsi8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bnei_encode_fns, 0, 0 },
+ { "bgei", ICLASS_xt_iclass_bsi8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bgei_encode_fns, 0, 0 },
+ { "blti", ICLASS_xt_iclass_bsi8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_blti_encode_fns, 0, 0 },
+ { "bbci", ICLASS_xt_iclass_bsi8b,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bbci_encode_fns, 0, 0 },
+ { "bbsi", ICLASS_xt_iclass_bsi8b,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bbsi_encode_fns, 0, 0 },
+ { "bgeui", ICLASS_xt_iclass_bsi8u,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bgeui_encode_fns, 0, 0 },
+ { "bltui", ICLASS_xt_iclass_bsi8u,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bltui_encode_fns, 0, 0 },
+ { "beq", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_beq_encode_fns, 0, 0 },
+ { "bne", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bne_encode_fns, 0, 0 },
+ { "bge", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bge_encode_fns, 0, 0 },
+ { "blt", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_blt_encode_fns, 0, 0 },
+ { "bgeu", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bgeu_encode_fns, 0, 0 },
+ { "bltu", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bltu_encode_fns, 0, 0 },
+ { "bany", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bany_encode_fns, 0, 0 },
+ { "bnone", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bnone_encode_fns, 0, 0 },
+ { "ball", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_ball_encode_fns, 0, 0 },
+ { "bnall", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bnall_encode_fns, 0, 0 },
+ { "bbc", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bbc_encode_fns, 0, 0 },
+ { "bbs", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bbs_encode_fns, 0, 0 },
+ { "beqz", ICLASS_xt_iclass_bsz12,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_beqz_encode_fns, 0, 0 },
+ { "bnez", ICLASS_xt_iclass_bsz12,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bnez_encode_fns, 0, 0 },
+ { "bgez", ICLASS_xt_iclass_bsz12,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bgez_encode_fns, 0, 0 },
+ { "bltz", ICLASS_xt_iclass_bsz12,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bltz_encode_fns, 0, 0 },
+ { "call0", ICLASS_xt_iclass_call0,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_call0_encode_fns, 0, 0 },
+ { "callx0", ICLASS_xt_iclass_callx0,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_callx0_encode_fns, 0, 0 },
+ { "extui", ICLASS_xt_iclass_exti,
+ 0,
+ Opcode_extui_encode_fns, 0, 0 },
+ { "ill", ICLASS_xt_iclass_ill,
+ 0,
+ Opcode_ill_encode_fns, 0, 0 },
+ { "j", ICLASS_xt_iclass_jump,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_j_encode_fns, 0, 0 },
+ { "jx", ICLASS_xt_iclass_jumpx,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_jx_encode_fns, 0, 0 },
+ { "l16ui", ICLASS_xt_iclass_l16ui,
+ 0,
+ Opcode_l16ui_encode_fns, 0, 0 },
+ { "l16si", ICLASS_xt_iclass_l16si,
+ 0,
+ Opcode_l16si_encode_fns, 0, 0 },
+ { "l32i", ICLASS_xt_iclass_l32i,
+ 0,
+ Opcode_l32i_encode_fns, 0, 0 },
+ { "l32r", ICLASS_xt_iclass_l32r,
+ 0,
+ Opcode_l32r_encode_fns, 0, 0 },
+ { "l8ui", ICLASS_xt_iclass_l8i,
+ 0,
+ Opcode_l8ui_encode_fns, 0, 0 },
+ { "movi", ICLASS_xt_iclass_movi,
+ 0,
+ Opcode_movi_encode_fns, 0, 0 },
+ { "moveqz", ICLASS_xt_iclass_movz,
+ 0,
+ Opcode_moveqz_encode_fns, 0, 0 },
+ { "movnez", ICLASS_xt_iclass_movz,
+ 0,
+ Opcode_movnez_encode_fns, 0, 0 },
+ { "movltz", ICLASS_xt_iclass_movz,
+ 0,
+ Opcode_movltz_encode_fns, 0, 0 },
+ { "movgez", ICLASS_xt_iclass_movz,
+ 0,
+ Opcode_movgez_encode_fns, 0, 0 },
+ { "neg", ICLASS_xt_iclass_neg,
+ 0,
+ Opcode_neg_encode_fns, 0, 0 },
+ { "abs", ICLASS_xt_iclass_neg,
+ 0,
+ Opcode_abs_encode_fns, 0, 0 },
+ { "nop", ICLASS_xt_iclass_nop,
+ 0,
+ Opcode_nop_encode_fns, 0, 0 },
+ { "ret", ICLASS_xt_iclass_return,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_ret_encode_fns, 0, 0 },
+ { "simcall", ICLASS_xt_iclass_simcall,
+ 0,
+ Opcode_simcall_encode_fns, 0, 0 },
+ { "s16i", ICLASS_xt_iclass_s16i,
+ 0,
+ Opcode_s16i_encode_fns, 0, 0 },
+ { "s32i", ICLASS_xt_iclass_s32i,
+ 0,
+ Opcode_s32i_encode_fns, 0, 0 },
+ { "s32nb", ICLASS_xt_iclass_s32nb,
+ 0,
+ Opcode_s32nb_encode_fns, 0, 0 },
+ { "s8i", ICLASS_xt_iclass_s8i,
+ 0,
+ Opcode_s8i_encode_fns, 0, 0 },
+ { "ssr", ICLASS_xt_iclass_sar,
+ 0,
+ Opcode_ssr_encode_fns, 0, 0 },
+ { "ssl", ICLASS_xt_iclass_sar,
+ 0,
+ Opcode_ssl_encode_fns, 0, 0 },
+ { "ssa8l", ICLASS_xt_iclass_sar,
+ 0,
+ Opcode_ssa8l_encode_fns, 0, 0 },
+ { "ssa8b", ICLASS_xt_iclass_sar,
+ 0,
+ Opcode_ssa8b_encode_fns, 0, 0 },
+ { "ssai", ICLASS_xt_iclass_sari,
+ 0,
+ Opcode_ssai_encode_fns, 0, 0 },
+ { "sll", ICLASS_xt_iclass_shifts,
+ 0,
+ Opcode_sll_encode_fns, 0, 0 },
+ { "src", ICLASS_xt_iclass_shiftst,
+ 0,
+ Opcode_src_encode_fns, 0, 0 },
+ { "srl", ICLASS_xt_iclass_shiftt,
+ 0,
+ Opcode_srl_encode_fns, 0, 0 },
+ { "sra", ICLASS_xt_iclass_shiftt,
+ 0,
+ Opcode_sra_encode_fns, 0, 0 },
+ { "slli", ICLASS_xt_iclass_slli,
+ 0,
+ Opcode_slli_encode_fns, 0, 0 },
+ { "srai", ICLASS_xt_iclass_srai,
+ 0,
+ Opcode_srai_encode_fns, 0, 0 },
+ { "srli", ICLASS_xt_iclass_srli,
+ 0,
+ Opcode_srli_encode_fns, 0, 0 },
+ { "memw", ICLASS_xt_iclass_memw,
+ 0,
+ Opcode_memw_encode_fns, 0, 0 },
+ { "extw", ICLASS_xt_iclass_extw,
+ 0,
+ Opcode_extw_encode_fns, 0, 0 },
+ { "isync", ICLASS_xt_iclass_isync,
+ 0,
+ Opcode_isync_encode_fns, 0, 0 },
+ { "rsync", ICLASS_xt_iclass_sync,
+ 0,
+ Opcode_rsync_encode_fns, 0, 0 },
+ { "esync", ICLASS_xt_iclass_sync,
+ 0,
+ Opcode_esync_encode_fns, 0, 0 },
+ { "dsync", ICLASS_xt_iclass_sync,
+ 0,
+ Opcode_dsync_encode_fns, 0, 0 },
+ { "rsil", ICLASS_xt_iclass_rsil,
+ 0,
+ Opcode_rsil_encode_fns, 0, 0 },
+ { "rsr.sar", ICLASS_xt_iclass_rsr_sar,
+ 0,
+ Opcode_rsr_sar_encode_fns, 0, 0 },
+ { "wsr.sar", ICLASS_xt_iclass_wsr_sar,
+ 0,
+ Opcode_wsr_sar_encode_fns, 0, 0 },
+ { "xsr.sar", ICLASS_xt_iclass_xsr_sar,
+ 0,
+ Opcode_xsr_sar_encode_fns, 0, 0 },
+ { "rsr.memctl", ICLASS_xt_iclass_rsr_memctl,
+ 0,
+ Opcode_rsr_memctl_encode_fns, 0, 0 },
+ { "wsr.memctl", ICLASS_xt_iclass_wsr_memctl,
+ 0,
+ Opcode_wsr_memctl_encode_fns, 0, 0 },
+ { "xsr.memctl", ICLASS_xt_iclass_xsr_memctl,
+ 0,
+ Opcode_xsr_memctl_encode_fns, 0, 0 },
+ { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase,
+ 0,
+ Opcode_rsr_litbase_encode_fns, 0, 0 },
+ { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase,
+ 0,
+ Opcode_wsr_litbase_encode_fns, 0, 0 },
+ { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase,
+ 0,
+ Opcode_xsr_litbase_encode_fns, 0, 0 },
+ { "rsr.configid0", ICLASS_xt_iclass_rsr_configid0,
+ 0,
+ Opcode_rsr_configid0_encode_fns, 0, 0 },
+ { "wsr.configid0", ICLASS_xt_iclass_wsr_configid0,
+ 0,
+ Opcode_wsr_configid0_encode_fns, 0, 0 },
+ { "rsr.configid1", ICLASS_xt_iclass_rsr_configid1,
+ 0,
+ Opcode_rsr_configid1_encode_fns, 0, 0 },
+ { "rsr.ps", ICLASS_xt_iclass_rsr_ps,
+ 0,
+ Opcode_rsr_ps_encode_fns, 0, 0 },
+ { "wsr.ps", ICLASS_xt_iclass_wsr_ps,
+ 0,
+ Opcode_wsr_ps_encode_fns, 0, 0 },
+ { "xsr.ps", ICLASS_xt_iclass_xsr_ps,
+ 0,
+ Opcode_xsr_ps_encode_fns, 0, 0 },
+ { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1,
+ 0,
+ Opcode_rsr_epc1_encode_fns, 0, 0 },
+ { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1,
+ 0,
+ Opcode_wsr_epc1_encode_fns, 0, 0 },
+ { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1,
+ 0,
+ Opcode_xsr_epc1_encode_fns, 0, 0 },
+ { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1,
+ 0,
+ Opcode_rsr_excsave1_encode_fns, 0, 0 },
+ { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1,
+ 0,
+ Opcode_wsr_excsave1_encode_fns, 0, 0 },
+ { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1,
+ 0,
+ Opcode_xsr_excsave1_encode_fns, 0, 0 },
+ { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2,
+ 0,
+ Opcode_rsr_epc2_encode_fns, 0, 0 },
+ { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2,
+ 0,
+ Opcode_wsr_epc2_encode_fns, 0, 0 },
+ { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2,
+ 0,
+ Opcode_xsr_epc2_encode_fns, 0, 0 },
+ { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2,
+ 0,
+ Opcode_rsr_excsave2_encode_fns, 0, 0 },
+ { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2,
+ 0,
+ Opcode_wsr_excsave2_encode_fns, 0, 0 },
+ { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2,
+ 0,
+ Opcode_xsr_excsave2_encode_fns, 0, 0 },
+ { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3,
+ 0,
+ Opcode_rsr_epc3_encode_fns, 0, 0 },
+ { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3,
+ 0,
+ Opcode_wsr_epc3_encode_fns, 0, 0 },
+ { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3,
+ 0,
+ Opcode_xsr_epc3_encode_fns, 0, 0 },
+ { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3,
+ 0,
+ Opcode_rsr_excsave3_encode_fns, 0, 0 },
+ { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3,
+ 0,
+ Opcode_wsr_excsave3_encode_fns, 0, 0 },
+ { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3,
+ 0,
+ Opcode_xsr_excsave3_encode_fns, 0, 0 },
+ { "rsr.epc4", ICLASS_xt_iclass_rsr_epc4,
+ 0,
+ Opcode_rsr_epc4_encode_fns, 0, 0 },
+ { "wsr.epc4", ICLASS_xt_iclass_wsr_epc4,
+ 0,
+ Opcode_wsr_epc4_encode_fns, 0, 0 },
+ { "xsr.epc4", ICLASS_xt_iclass_xsr_epc4,
+ 0,
+ Opcode_xsr_epc4_encode_fns, 0, 0 },
+ { "rsr.excsave4", ICLASS_xt_iclass_rsr_excsave4,
+ 0,
+ Opcode_rsr_excsave4_encode_fns, 0, 0 },
+ { "wsr.excsave4", ICLASS_xt_iclass_wsr_excsave4,
+ 0,
+ Opcode_wsr_excsave4_encode_fns, 0, 0 },
+ { "xsr.excsave4", ICLASS_xt_iclass_xsr_excsave4,
+ 0,
+ Opcode_xsr_excsave4_encode_fns, 0, 0 },
+ { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5,
+ 0,
+ Opcode_rsr_epc5_encode_fns, 0, 0 },
+ { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5,
+ 0,
+ Opcode_wsr_epc5_encode_fns, 0, 0 },
+ { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5,
+ 0,
+ Opcode_xsr_epc5_encode_fns, 0, 0 },
+ { "rsr.excsave5", ICLASS_xt_iclass_rsr_excsave5,
+ 0,
+ Opcode_rsr_excsave5_encode_fns, 0, 0 },
+ { "wsr.excsave5", ICLASS_xt_iclass_wsr_excsave5,
+ 0,
+ Opcode_wsr_excsave5_encode_fns, 0, 0 },
+ { "xsr.excsave5", ICLASS_xt_iclass_xsr_excsave5,
+ 0,
+ Opcode_xsr_excsave5_encode_fns, 0, 0 },
+ { "rsr.epc6", ICLASS_xt_iclass_rsr_epc6,
+ 0,
+ Opcode_rsr_epc6_encode_fns, 0, 0 },
+ { "wsr.epc6", ICLASS_xt_iclass_wsr_epc6,
+ 0,
+ Opcode_wsr_epc6_encode_fns, 0, 0 },
+ { "xsr.epc6", ICLASS_xt_iclass_xsr_epc6,
+ 0,
+ Opcode_xsr_epc6_encode_fns, 0, 0 },
+ { "rsr.excsave6", ICLASS_xt_iclass_rsr_excsave6,
+ 0,
+ Opcode_rsr_excsave6_encode_fns, 0, 0 },
+ { "wsr.excsave6", ICLASS_xt_iclass_wsr_excsave6,
+ 0,
+ Opcode_wsr_excsave6_encode_fns, 0, 0 },
+ { "xsr.excsave6", ICLASS_xt_iclass_xsr_excsave6,
+ 0,
+ Opcode_xsr_excsave6_encode_fns, 0, 0 },
+ { "rsr.epc7", ICLASS_xt_iclass_rsr_epc7,
+ 0,
+ Opcode_rsr_epc7_encode_fns, 0, 0 },
+ { "wsr.epc7", ICLASS_xt_iclass_wsr_epc7,
+ 0,
+ Opcode_wsr_epc7_encode_fns, 0, 0 },
+ { "xsr.epc7", ICLASS_xt_iclass_xsr_epc7,
+ 0,
+ Opcode_xsr_epc7_encode_fns, 0, 0 },
+ { "rsr.excsave7", ICLASS_xt_iclass_rsr_excsave7,
+ 0,
+ Opcode_rsr_excsave7_encode_fns, 0, 0 },
+ { "wsr.excsave7", ICLASS_xt_iclass_wsr_excsave7,
+ 0,
+ Opcode_wsr_excsave7_encode_fns, 0, 0 },
+ { "xsr.excsave7", ICLASS_xt_iclass_xsr_excsave7,
+ 0,
+ Opcode_xsr_excsave7_encode_fns, 0, 0 },
+ { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2,
+ 0,
+ Opcode_rsr_eps2_encode_fns, 0, 0 },
+ { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2,
+ 0,
+ Opcode_wsr_eps2_encode_fns, 0, 0 },
+ { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2,
+ 0,
+ Opcode_xsr_eps2_encode_fns, 0, 0 },
+ { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3,
+ 0,
+ Opcode_rsr_eps3_encode_fns, 0, 0 },
+ { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3,
+ 0,
+ Opcode_wsr_eps3_encode_fns, 0, 0 },
+ { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3,
+ 0,
+ Opcode_xsr_eps3_encode_fns, 0, 0 },
+ { "rsr.eps4", ICLASS_xt_iclass_rsr_eps4,
+ 0,
+ Opcode_rsr_eps4_encode_fns, 0, 0 },
+ { "wsr.eps4", ICLASS_xt_iclass_wsr_eps4,
+ 0,
+ Opcode_wsr_eps4_encode_fns, 0, 0 },
+ { "xsr.eps4", ICLASS_xt_iclass_xsr_eps4,
+ 0,
+ Opcode_xsr_eps4_encode_fns, 0, 0 },
+ { "rsr.eps5", ICLASS_xt_iclass_rsr_eps5,
+ 0,
+ Opcode_rsr_eps5_encode_fns, 0, 0 },
+ { "wsr.eps5", ICLASS_xt_iclass_wsr_eps5,
+ 0,
+ Opcode_wsr_eps5_encode_fns, 0, 0 },
+ { "xsr.eps5", ICLASS_xt_iclass_xsr_eps5,
+ 0,
+ Opcode_xsr_eps5_encode_fns, 0, 0 },
+ { "rsr.eps6", ICLASS_xt_iclass_rsr_eps6,
+ 0,
+ Opcode_rsr_eps6_encode_fns, 0, 0 },
+ { "wsr.eps6", ICLASS_xt_iclass_wsr_eps6,
+ 0,
+ Opcode_wsr_eps6_encode_fns, 0, 0 },
+ { "xsr.eps6", ICLASS_xt_iclass_xsr_eps6,
+ 0,
+ Opcode_xsr_eps6_encode_fns, 0, 0 },
+ { "rsr.eps7", ICLASS_xt_iclass_rsr_eps7,
+ 0,
+ Opcode_rsr_eps7_encode_fns, 0, 0 },
+ { "wsr.eps7", ICLASS_xt_iclass_wsr_eps7,
+ 0,
+ Opcode_wsr_eps7_encode_fns, 0, 0 },
+ { "xsr.eps7", ICLASS_xt_iclass_xsr_eps7,
+ 0,
+ Opcode_xsr_eps7_encode_fns, 0, 0 },
+ { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr,
+ 0,
+ Opcode_rsr_excvaddr_encode_fns, 0, 0 },
+ { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr,
+ 0,
+ Opcode_wsr_excvaddr_encode_fns, 0, 0 },
+ { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr,
+ 0,
+ Opcode_xsr_excvaddr_encode_fns, 0, 0 },
+ { "rsr.depc", ICLASS_xt_iclass_rsr_depc,
+ 0,
+ Opcode_rsr_depc_encode_fns, 0, 0 },
+ { "wsr.depc", ICLASS_xt_iclass_wsr_depc,
+ 0,
+ Opcode_wsr_depc_encode_fns, 0, 0 },
+ { "xsr.depc", ICLASS_xt_iclass_xsr_depc,
+ 0,
+ Opcode_xsr_depc_encode_fns, 0, 0 },
+ { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause,
+ 0,
+ Opcode_rsr_exccause_encode_fns, 0, 0 },
+ { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause,
+ 0,
+ Opcode_wsr_exccause_encode_fns, 0, 0 },
+ { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause,
+ 0,
+ Opcode_xsr_exccause_encode_fns, 0, 0 },
+ { "rsr.misc0", ICLASS_xt_iclass_rsr_misc0,
+ 0,
+ Opcode_rsr_misc0_encode_fns, 0, 0 },
+ { "wsr.misc0", ICLASS_xt_iclass_wsr_misc0,
+ 0,
+ Opcode_wsr_misc0_encode_fns, 0, 0 },
+ { "xsr.misc0", ICLASS_xt_iclass_xsr_misc0,
+ 0,
+ Opcode_xsr_misc0_encode_fns, 0, 0 },
+ { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1,
+ 0,
+ Opcode_rsr_misc1_encode_fns, 0, 0 },
+ { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1,
+ 0,
+ Opcode_wsr_misc1_encode_fns, 0, 0 },
+ { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1,
+ 0,
+ Opcode_xsr_misc1_encode_fns, 0, 0 },
+ { "rsr.prid", ICLASS_xt_iclass_rsr_prid,
+ 0,
+ Opcode_rsr_prid_encode_fns, 0, 0 },
+ { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase,
+ 0,
+ Opcode_rsr_vecbase_encode_fns, 0, 0 },
+ { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase,
+ 0,
+ Opcode_wsr_vecbase_encode_fns, 0, 0 },
+ { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase,
+ 0,
+ Opcode_xsr_vecbase_encode_fns, 0, 0 },
+ { "salt", ICLASS_xt_iclass_salt,
+ 0,
+ Opcode_salt_encode_fns, 0, 0 },
+ { "saltu", ICLASS_xt_iclass_salt,
+ 0,
+ Opcode_saltu_encode_fns, 0, 0 },
+ { "mul16u", ICLASS_xt_mul16,
+ 0,
+ Opcode_mul16u_encode_fns, 0, 0 },
+ { "mul16s", ICLASS_xt_mul16,
+ 0,
+ Opcode_mul16s_encode_fns, 0, 0 },
+ { "mull", ICLASS_xt_mul32,
+ 0,
+ Opcode_mull_encode_fns, 0, 0 },
+ { "rfi", ICLASS_xt_iclass_rfi,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfi_encode_fns, 0, 0 },
+ { "waiti", ICLASS_xt_iclass_wait,
+ 0,
+ Opcode_waiti_encode_fns, 0, 0 },
+ { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt,
+ 0,
+ Opcode_rsr_interrupt_encode_fns, 0, 0 },
+ { "wsr.intset", ICLASS_xt_iclass_wsr_intset,
+ 0,
+ Opcode_wsr_intset_encode_fns, 0, 0 },
+ { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear,
+ 0,
+ Opcode_wsr_intclear_encode_fns, 0, 0 },
+ { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable,
+ 0,
+ Opcode_rsr_intenable_encode_fns, 0, 0 },
+ { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable,
+ 0,
+ Opcode_wsr_intenable_encode_fns, 0, 0 },
+ { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable,
+ 0,
+ Opcode_xsr_intenable_encode_fns, 0, 0 },
+ { "break", ICLASS_xt_iclass_break,
+ 0,
+ Opcode_break_encode_fns, 0, 0 },
+ { "break.n", ICLASS_xt_iclass_break_n,
+ 0,
+ Opcode_break_n_encode_fns, 0, 0 },
+ { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0,
+ 0,
+ Opcode_rsr_dbreaka0_encode_fns, 0, 0 },
+ { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0,
+ 0,
+ Opcode_wsr_dbreaka0_encode_fns, 0, 0 },
+ { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0,
+ 0,
+ Opcode_xsr_dbreaka0_encode_fns, 0, 0 },
+ { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0,
+ 0,
+ Opcode_rsr_dbreakc0_encode_fns, 0, 0 },
+ { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0,
+ 0,
+ Opcode_wsr_dbreakc0_encode_fns, 0, 0 },
+ { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0,
+ 0,
+ Opcode_xsr_dbreakc0_encode_fns, 0, 0 },
+ { "rsr.dbreaka1", ICLASS_xt_iclass_rsr_dbreaka1,
+ 0,
+ Opcode_rsr_dbreaka1_encode_fns, 0, 0 },
+ { "wsr.dbreaka1", ICLASS_xt_iclass_wsr_dbreaka1,
+ 0,
+ Opcode_wsr_dbreaka1_encode_fns, 0, 0 },
+ { "xsr.dbreaka1", ICLASS_xt_iclass_xsr_dbreaka1,
+ 0,
+ Opcode_xsr_dbreaka1_encode_fns, 0, 0 },
+ { "rsr.dbreakc1", ICLASS_xt_iclass_rsr_dbreakc1,
+ 0,
+ Opcode_rsr_dbreakc1_encode_fns, 0, 0 },
+ { "wsr.dbreakc1", ICLASS_xt_iclass_wsr_dbreakc1,
+ 0,
+ Opcode_wsr_dbreakc1_encode_fns, 0, 0 },
+ { "xsr.dbreakc1", ICLASS_xt_iclass_xsr_dbreakc1,
+ 0,
+ Opcode_xsr_dbreakc1_encode_fns, 0, 0 },
+ { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0,
+ 0,
+ Opcode_rsr_ibreaka0_encode_fns, 0, 0 },
+ { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0,
+ 0,
+ Opcode_wsr_ibreaka0_encode_fns, 0, 0 },
+ { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0,
+ 0,
+ Opcode_xsr_ibreaka0_encode_fns, 0, 0 },
+ { "rsr.ibreaka1", ICLASS_xt_iclass_rsr_ibreaka1,
+ 0,
+ Opcode_rsr_ibreaka1_encode_fns, 0, 0 },
+ { "wsr.ibreaka1", ICLASS_xt_iclass_wsr_ibreaka1,
+ 0,
+ Opcode_wsr_ibreaka1_encode_fns, 0, 0 },
+ { "xsr.ibreaka1", ICLASS_xt_iclass_xsr_ibreaka1,
+ 0,
+ Opcode_xsr_ibreaka1_encode_fns, 0, 0 },
+ { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable,
+ 0,
+ Opcode_rsr_ibreakenable_encode_fns, 0, 0 },
+ { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable,
+ 0,
+ Opcode_wsr_ibreakenable_encode_fns, 0, 0 },
+ { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable,
+ 0,
+ Opcode_xsr_ibreakenable_encode_fns, 0, 0 },
+ { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause,
+ 0,
+ Opcode_rsr_debugcause_encode_fns, 0, 0 },
+ { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause,
+ 0,
+ Opcode_wsr_debugcause_encode_fns, 0, 0 },
+ { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause,
+ 0,
+ Opcode_xsr_debugcause_encode_fns, 0, 0 },
+ { "rsr.icount", ICLASS_xt_iclass_rsr_icount,
+ 0,
+ Opcode_rsr_icount_encode_fns, 0, 0 },
+ { "wsr.icount", ICLASS_xt_iclass_wsr_icount,
+ 0,
+ Opcode_wsr_icount_encode_fns, 0, 0 },
+ { "xsr.icount", ICLASS_xt_iclass_xsr_icount,
+ 0,
+ Opcode_xsr_icount_encode_fns, 0, 0 },
+ { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel,
+ 0,
+ Opcode_rsr_icountlevel_encode_fns, 0, 0 },
+ { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel,
+ 0,
+ Opcode_wsr_icountlevel_encode_fns, 0, 0 },
+ { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel,
+ 0,
+ Opcode_xsr_icountlevel_encode_fns, 0, 0 },
+ { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr,
+ 0,
+ Opcode_rsr_ddr_encode_fns, 0, 0 },
+ { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr,
+ 0,
+ Opcode_wsr_ddr_encode_fns, 0, 0 },
+ { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr,
+ 0,
+ Opcode_xsr_ddr_encode_fns, 0, 0 },
+ { "lddr32.p", ICLASS_xt_iclass_lddr32_p,
+ 0,
+ Opcode_lddr32_p_encode_fns, 0, 0 },
+ { "sddr32.p", ICLASS_xt_iclass_sddr32_p,
+ 0,
+ Opcode_sddr32_p_encode_fns, 0, 0 },
+ { "rfdo", ICLASS_xt_iclass_rfdo,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfdo_encode_fns, 0, 0 },
+ { "rfdd", ICLASS_xt_iclass_rfdd,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfdd_encode_fns, 0, 0 },
+ { "wsr.mmid", ICLASS_xt_iclass_wsr_mmid,
+ 0,
+ Opcode_wsr_mmid_encode_fns, 0, 0 },
+ { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount,
+ 0,
+ Opcode_rsr_ccount_encode_fns, 0, 0 },
+ { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount,
+ 0,
+ Opcode_wsr_ccount_encode_fns, 0, 0 },
+ { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount,
+ 0,
+ Opcode_xsr_ccount_encode_fns, 0, 0 },
+ { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0,
+ 0,
+ Opcode_rsr_ccompare0_encode_fns, 0, 0 },
+ { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0,
+ 0,
+ Opcode_wsr_ccompare0_encode_fns, 0, 0 },
+ { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0,
+ 0,
+ Opcode_xsr_ccompare0_encode_fns, 0, 0 },
+ { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1,
+ 0,
+ Opcode_rsr_ccompare1_encode_fns, 0, 0 },
+ { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1,
+ 0,
+ Opcode_wsr_ccompare1_encode_fns, 0, 0 },
+ { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1,
+ 0,
+ Opcode_xsr_ccompare1_encode_fns, 0, 0 },
+ { "rsr.ccompare2", ICLASS_xt_iclass_rsr_ccompare2,
+ 0,
+ Opcode_rsr_ccompare2_encode_fns, 0, 0 },
+ { "wsr.ccompare2", ICLASS_xt_iclass_wsr_ccompare2,
+ 0,
+ Opcode_wsr_ccompare2_encode_fns, 0, 0 },
+ { "xsr.ccompare2", ICLASS_xt_iclass_xsr_ccompare2,
+ 0,
+ Opcode_xsr_ccompare2_encode_fns, 0, 0 },
+ { "idtlb", ICLASS_xt_iclass_idtlb,
+ 0,
+ Opcode_idtlb_encode_fns, 0, 0 },
+ { "pdtlb", ICLASS_xt_iclass_rdtlb,
+ 0,
+ Opcode_pdtlb_encode_fns, 0, 0 },
+ { "rdtlb0", ICLASS_xt_iclass_rdtlb,
+ 0,
+ Opcode_rdtlb0_encode_fns, 0, 0 },
+ { "rdtlb1", ICLASS_xt_iclass_rdtlb,
+ 0,
+ Opcode_rdtlb1_encode_fns, 0, 0 },
+ { "wdtlb", ICLASS_xt_iclass_wdtlb,
+ 0,
+ Opcode_wdtlb_encode_fns, 0, 0 },
+ { "iitlb", ICLASS_xt_iclass_iitlb,
+ 0,
+ Opcode_iitlb_encode_fns, 0, 0 },
+ { "pitlb", ICLASS_xt_iclass_ritlb,
+ 0,
+ Opcode_pitlb_encode_fns, 0, 0 },
+ { "ritlb0", ICLASS_xt_iclass_ritlb,
+ 0,
+ Opcode_ritlb0_encode_fns, 0, 0 },
+ { "ritlb1", ICLASS_xt_iclass_ritlb,
+ 0,
+ Opcode_ritlb1_encode_fns, 0, 0 },
+ { "witlb", ICLASS_xt_iclass_witlb,
+ 0,
+ Opcode_witlb_encode_fns, 0, 0 },
+ { "min", ICLASS_xt_iclass_minmax,
+ 0,
+ Opcode_min_encode_fns, 0, 0 },
+ { "max", ICLASS_xt_iclass_minmax,
+ 0,
+ Opcode_max_encode_fns, 0, 0 },
+ { "minu", ICLASS_xt_iclass_minmax,
+ 0,
+ Opcode_minu_encode_fns, 0, 0 },
+ { "maxu", ICLASS_xt_iclass_minmax,
+ 0,
+ Opcode_maxu_encode_fns, 0, 0 },
+ { "nsa", ICLASS_xt_iclass_nsa,
+ 0,
+ Opcode_nsa_encode_fns, 0, 0 },
+ { "nsau", ICLASS_xt_iclass_nsa,
+ 0,
+ Opcode_nsau_encode_fns, 0, 0 },
+ { "sext", ICLASS_xt_iclass_sx,
+ 0,
+ Opcode_sext_encode_fns, 0, 0 },
+ { "l32ai", ICLASS_xt_iclass_l32ai,
+ 0,
+ Opcode_l32ai_encode_fns, 0, 0 },
+ { "s32ri", ICLASS_xt_iclass_s32ri,
+ 0,
+ Opcode_s32ri_encode_fns, 0, 0 },
+ { "s32c1i", ICLASS_xt_iclass_s32c1i,
+ 0,
+ Opcode_s32c1i_encode_fns, 0, 0 },
+ { "rsr.scompare1", ICLASS_xt_iclass_rsr_scompare1,
+ 0,
+ Opcode_rsr_scompare1_encode_fns, 0, 0 },
+ { "wsr.scompare1", ICLASS_xt_iclass_wsr_scompare1,
+ 0,
+ Opcode_wsr_scompare1_encode_fns, 0, 0 },
+ { "xsr.scompare1", ICLASS_xt_iclass_xsr_scompare1,
+ 0,
+ Opcode_xsr_scompare1_encode_fns, 0, 0 },
+ { "rsr.atomctl", ICLASS_xt_iclass_rsr_atomctl,
+ 0,
+ Opcode_rsr_atomctl_encode_fns, 0, 0 },
+ { "wsr.atomctl", ICLASS_xt_iclass_wsr_atomctl,
+ 0,
+ Opcode_wsr_atomctl_encode_fns, 0, 0 },
+ { "xsr.atomctl", ICLASS_xt_iclass_xsr_atomctl,
+ 0,
+ Opcode_xsr_atomctl_encode_fns, 0, 0 },
+ { "quou", ICLASS_xt_iclass_div,
+ 0,
+ Opcode_quou_encode_fns, 0, 0 },
+ { "quos", ICLASS_xt_iclass_div,
+ 0,
+ Opcode_quos_encode_fns, 0, 0 },
+ { "remu", ICLASS_xt_iclass_div,
+ 0,
+ Opcode_remu_encode_fns, 0, 0 },
+ { "rems", ICLASS_xt_iclass_div,
+ 0,
+ Opcode_rems_encode_fns, 0, 0 },
+ { "rsr.eraccess", ICLASS_xt_iclass_rsr_eraccess,
+ 0,
+ Opcode_rsr_eraccess_encode_fns, 0, 0 },
+ { "wsr.eraccess", ICLASS_xt_iclass_wsr_eraccess,
+ 0,
+ Opcode_wsr_eraccess_encode_fns, 0, 0 },
+ { "xsr.eraccess", ICLASS_xt_iclass_xsr_eraccess,
+ 0,
+ Opcode_xsr_eraccess_encode_fns, 0, 0 },
+ { "rer", ICLASS_xt_iclass_rer,
+ 0,
+ Opcode_rer_encode_fns, 0, 0 },
+ { "wer", ICLASS_xt_iclass_wer,
+ 0,
+ Opcode_wer_encode_fns, 0, 0 },
+ { "rur.expstate", ICLASS_rur_expstate,
+ 0,
+ Opcode_rur_expstate_encode_fns, 0, 0 },
+ { "wur.expstate", ICLASS_wur_expstate,
+ 0,
+ Opcode_wur_expstate_encode_fns, 0, 0 },
+ { "read_impwire", ICLASS_iclass_READ_IMPWIRE,
+ 0,
+ Opcode_read_impwire_encode_fns, 0, 0 },
+ { "setb_expstate", ICLASS_iclass_SETB_EXPSTATE,
+ 0,
+ Opcode_setb_expstate_encode_fns, 0, 0 },
+ { "clrb_expstate", ICLASS_iclass_CLRB_EXPSTATE,
+ 0,
+ Opcode_clrb_expstate_encode_fns, 0, 0 },
+ { "wrmsk_expstate", ICLASS_iclass_WRMSK_EXPSTATE,
+ 0,
+ Opcode_wrmsk_expstate_encode_fns, 0, 0 }
+};
+
+enum xtensa_opcode_id {
+ OPCODE_EXCW,
+ OPCODE_RFE,
+ OPCODE_RFDE,
+ OPCODE_SYSCALL,
+ OPCODE_CALL12,
+ OPCODE_CALL8,
+ OPCODE_CALL4,
+ OPCODE_CALLX12,
+ OPCODE_CALLX8,
+ OPCODE_CALLX4,
+ OPCODE_ENTRY,
+ OPCODE_MOVSP,
+ OPCODE_ROTW,
+ OPCODE_RETW,
+ OPCODE_RETW_N,
+ OPCODE_RFWO,
+ OPCODE_RFWU,
+ OPCODE_L32E,
+ OPCODE_S32E,
+ OPCODE_RSR_WINDOWBASE,
+ OPCODE_WSR_WINDOWBASE,
+ OPCODE_XSR_WINDOWBASE,
+ OPCODE_RSR_WINDOWSTART,
+ OPCODE_WSR_WINDOWSTART,
+ OPCODE_XSR_WINDOWSTART,
+ OPCODE_ADD_N,
+ OPCODE_ADDI_N,
+ OPCODE_BEQZ_N,
+ OPCODE_BNEZ_N,
+ OPCODE_ILL_N,
+ OPCODE_L32I_N,
+ OPCODE_MOV_N,
+ OPCODE_MOVI_N,
+ OPCODE_NOP_N,
+ OPCODE_RET_N,
+ OPCODE_S32I_N,
+ OPCODE_ADDI,
+ OPCODE_ADDMI,
+ OPCODE_ADD,
+ OPCODE_SUB,
+ OPCODE_ADDX2,
+ OPCODE_ADDX4,
+ OPCODE_ADDX8,
+ OPCODE_SUBX2,
+ OPCODE_SUBX4,
+ OPCODE_SUBX8,
+ OPCODE_AND,
+ OPCODE_OR,
+ OPCODE_XOR,
+ OPCODE_BEQI,
+ OPCODE_BNEI,
+ OPCODE_BGEI,
+ OPCODE_BLTI,
+ OPCODE_BBCI,
+ OPCODE_BBSI,
+ OPCODE_BGEUI,
+ OPCODE_BLTUI,
+ OPCODE_BEQ,
+ OPCODE_BNE,
+ OPCODE_BGE,
+ OPCODE_BLT,
+ OPCODE_BGEU,
+ OPCODE_BLTU,
+ OPCODE_BANY,
+ OPCODE_BNONE,
+ OPCODE_BALL,
+ OPCODE_BNALL,
+ OPCODE_BBC,
+ OPCODE_BBS,
+ OPCODE_BEQZ,
+ OPCODE_BNEZ,
+ OPCODE_BGEZ,
+ OPCODE_BLTZ,
+ OPCODE_CALL0,
+ OPCODE_CALLX0,
+ OPCODE_EXTUI,
+ OPCODE_ILL,
+ OPCODE_J,
+ OPCODE_JX,
+ OPCODE_L16UI,
+ OPCODE_L16SI,
+ OPCODE_L32I,
+ OPCODE_L32R,
+ OPCODE_L8UI,
+ OPCODE_MOVI,
+ OPCODE_MOVEQZ,
+ OPCODE_MOVNEZ,
+ OPCODE_MOVLTZ,
+ OPCODE_MOVGEZ,
+ OPCODE_NEG,
+ OPCODE_ABS,
+ OPCODE_NOP,
+ OPCODE_RET,
+ OPCODE_SIMCALL,
+ OPCODE_S16I,
+ OPCODE_S32I,
+ OPCODE_S32NB,
+ OPCODE_S8I,
+ OPCODE_SSR,
+ OPCODE_SSL,
+ OPCODE_SSA8L,
+ OPCODE_SSA8B,
+ OPCODE_SSAI,
+ OPCODE_SLL,
+ OPCODE_SRC,
+ OPCODE_SRL,
+ OPCODE_SRA,
+ OPCODE_SLLI,
+ OPCODE_SRAI,
+ OPCODE_SRLI,
+ OPCODE_MEMW,
+ OPCODE_EXTW,
+ OPCODE_ISYNC,
+ OPCODE_RSYNC,
+ OPCODE_ESYNC,
+ OPCODE_DSYNC,
+ OPCODE_RSIL,
+ OPCODE_RSR_SAR,
+ OPCODE_WSR_SAR,
+ OPCODE_XSR_SAR,
+ OPCODE_RSR_MEMCTL,
+ OPCODE_WSR_MEMCTL,
+ OPCODE_XSR_MEMCTL,
+ OPCODE_RSR_LITBASE,
+ OPCODE_WSR_LITBASE,
+ OPCODE_XSR_LITBASE,
+ OPCODE_RSR_CONFIGID0,
+ OPCODE_WSR_CONFIGID0,
+ OPCODE_RSR_CONFIGID1,
+ OPCODE_RSR_PS,
+ OPCODE_WSR_PS,
+ OPCODE_XSR_PS,
+ OPCODE_RSR_EPC1,
+ OPCODE_WSR_EPC1,
+ OPCODE_XSR_EPC1,
+ OPCODE_RSR_EXCSAVE1,
+ OPCODE_WSR_EXCSAVE1,
+ OPCODE_XSR_EXCSAVE1,
+ OPCODE_RSR_EPC2,
+ OPCODE_WSR_EPC2,
+ OPCODE_XSR_EPC2,
+ OPCODE_RSR_EXCSAVE2,
+ OPCODE_WSR_EXCSAVE2,
+ OPCODE_XSR_EXCSAVE2,
+ OPCODE_RSR_EPC3,
+ OPCODE_WSR_EPC3,
+ OPCODE_XSR_EPC3,
+ OPCODE_RSR_EXCSAVE3,
+ OPCODE_WSR_EXCSAVE3,
+ OPCODE_XSR_EXCSAVE3,
+ OPCODE_RSR_EPC4,
+ OPCODE_WSR_EPC4,
+ OPCODE_XSR_EPC4,
+ OPCODE_RSR_EXCSAVE4,
+ OPCODE_WSR_EXCSAVE4,
+ OPCODE_XSR_EXCSAVE4,
+ OPCODE_RSR_EPC5,
+ OPCODE_WSR_EPC5,
+ OPCODE_XSR_EPC5,
+ OPCODE_RSR_EXCSAVE5,
+ OPCODE_WSR_EXCSAVE5,
+ OPCODE_XSR_EXCSAVE5,
+ OPCODE_RSR_EPC6,
+ OPCODE_WSR_EPC6,
+ OPCODE_XSR_EPC6,
+ OPCODE_RSR_EXCSAVE6,
+ OPCODE_WSR_EXCSAVE6,
+ OPCODE_XSR_EXCSAVE6,
+ OPCODE_RSR_EPC7,
+ OPCODE_WSR_EPC7,
+ OPCODE_XSR_EPC7,
+ OPCODE_RSR_EXCSAVE7,
+ OPCODE_WSR_EXCSAVE7,
+ OPCODE_XSR_EXCSAVE7,
+ OPCODE_RSR_EPS2,
+ OPCODE_WSR_EPS2,
+ OPCODE_XSR_EPS2,
+ OPCODE_RSR_EPS3,
+ OPCODE_WSR_EPS3,
+ OPCODE_XSR_EPS3,
+ OPCODE_RSR_EPS4,
+ OPCODE_WSR_EPS4,
+ OPCODE_XSR_EPS4,
+ OPCODE_RSR_EPS5,
+ OPCODE_WSR_EPS5,
+ OPCODE_XSR_EPS5,
+ OPCODE_RSR_EPS6,
+ OPCODE_WSR_EPS6,
+ OPCODE_XSR_EPS6,
+ OPCODE_RSR_EPS7,
+ OPCODE_WSR_EPS7,
+ OPCODE_XSR_EPS7,
+ OPCODE_RSR_EXCVADDR,
+ OPCODE_WSR_EXCVADDR,
+ OPCODE_XSR_EXCVADDR,
+ OPCODE_RSR_DEPC,
+ OPCODE_WSR_DEPC,
+ OPCODE_XSR_DEPC,
+ OPCODE_RSR_EXCCAUSE,
+ OPCODE_WSR_EXCCAUSE,
+ OPCODE_XSR_EXCCAUSE,
+ OPCODE_RSR_MISC0,
+ OPCODE_WSR_MISC0,
+ OPCODE_XSR_MISC0,
+ OPCODE_RSR_MISC1,
+ OPCODE_WSR_MISC1,
+ OPCODE_XSR_MISC1,
+ OPCODE_RSR_PRID,
+ OPCODE_RSR_VECBASE,
+ OPCODE_WSR_VECBASE,
+ OPCODE_XSR_VECBASE,
+ OPCODE_SALT,
+ OPCODE_SALTU,
+ OPCODE_MUL16U,
+ OPCODE_MUL16S,
+ OPCODE_MULL,
+ OPCODE_RFI,
+ OPCODE_WAITI,
+ OPCODE_RSR_INTERRUPT,
+ OPCODE_WSR_INTSET,
+ OPCODE_WSR_INTCLEAR,
+ OPCODE_RSR_INTENABLE,
+ OPCODE_WSR_INTENABLE,
+ OPCODE_XSR_INTENABLE,
+ OPCODE_BREAK,
+ OPCODE_BREAK_N,
+ OPCODE_RSR_DBREAKA0,
+ OPCODE_WSR_DBREAKA0,
+ OPCODE_XSR_DBREAKA0,
+ OPCODE_RSR_DBREAKC0,
+ OPCODE_WSR_DBREAKC0,
+ OPCODE_XSR_DBREAKC0,
+ OPCODE_RSR_DBREAKA1,
+ OPCODE_WSR_DBREAKA1,
+ OPCODE_XSR_DBREAKA1,
+ OPCODE_RSR_DBREAKC1,
+ OPCODE_WSR_DBREAKC1,
+ OPCODE_XSR_DBREAKC1,
+ OPCODE_RSR_IBREAKA0,
+ OPCODE_WSR_IBREAKA0,
+ OPCODE_XSR_IBREAKA0,
+ OPCODE_RSR_IBREAKA1,
+ OPCODE_WSR_IBREAKA1,
+ OPCODE_XSR_IBREAKA1,
+ OPCODE_RSR_IBREAKENABLE,
+ OPCODE_WSR_IBREAKENABLE,
+ OPCODE_XSR_IBREAKENABLE,
+ OPCODE_RSR_DEBUGCAUSE,
+ OPCODE_WSR_DEBUGCAUSE,
+ OPCODE_XSR_DEBUGCAUSE,
+ OPCODE_RSR_ICOUNT,
+ OPCODE_WSR_ICOUNT,
+ OPCODE_XSR_ICOUNT,
+ OPCODE_RSR_ICOUNTLEVEL,
+ OPCODE_WSR_ICOUNTLEVEL,
+ OPCODE_XSR_ICOUNTLEVEL,
+ OPCODE_RSR_DDR,
+ OPCODE_WSR_DDR,
+ OPCODE_XSR_DDR,
+ OPCODE_LDDR32_P,
+ OPCODE_SDDR32_P,
+ OPCODE_RFDO,
+ OPCODE_RFDD,
+ OPCODE_WSR_MMID,
+ OPCODE_RSR_CCOUNT,
+ OPCODE_WSR_CCOUNT,
+ OPCODE_XSR_CCOUNT,
+ OPCODE_RSR_CCOMPARE0,
+ OPCODE_WSR_CCOMPARE0,
+ OPCODE_XSR_CCOMPARE0,
+ OPCODE_RSR_CCOMPARE1,
+ OPCODE_WSR_CCOMPARE1,
+ OPCODE_XSR_CCOMPARE1,
+ OPCODE_RSR_CCOMPARE2,
+ OPCODE_WSR_CCOMPARE2,
+ OPCODE_XSR_CCOMPARE2,
+ OPCODE_IDTLB,
+ OPCODE_PDTLB,
+ OPCODE_RDTLB0,
+ OPCODE_RDTLB1,
+ OPCODE_WDTLB,
+ OPCODE_IITLB,
+ OPCODE_PITLB,
+ OPCODE_RITLB0,
+ OPCODE_RITLB1,
+ OPCODE_WITLB,
+ OPCODE_MIN,
+ OPCODE_MAX,
+ OPCODE_MINU,
+ OPCODE_MAXU,
+ OPCODE_NSA,
+ OPCODE_NSAU,
+ OPCODE_SEXT,
+ OPCODE_L32AI,
+ OPCODE_S32RI,
+ OPCODE_S32C1I,
+ OPCODE_RSR_SCOMPARE1,
+ OPCODE_WSR_SCOMPARE1,
+ OPCODE_XSR_SCOMPARE1,
+ OPCODE_RSR_ATOMCTL,
+ OPCODE_WSR_ATOMCTL,
+ OPCODE_XSR_ATOMCTL,
+ OPCODE_QUOU,
+ OPCODE_QUOS,
+ OPCODE_REMU,
+ OPCODE_REMS,
+ OPCODE_RSR_ERACCESS,
+ OPCODE_WSR_ERACCESS,
+ OPCODE_XSR_ERACCESS,
+ OPCODE_RER,
+ OPCODE_WER,
+ OPCODE_RUR_EXPSTATE,
+ OPCODE_WUR_EXPSTATE,
+ OPCODE_READ_IMPWIRE,
+ OPCODE_SETB_EXPSTATE,
+ OPCODE_CLRB_EXPSTATE,
+ OPCODE_WRMSK_EXPSTATE
+};
+
+
+/* Slot-specific opcode decode functions. */
+
+static int
+Slot_inst_decode (const xtensa_insnbuf insn)
+{
+ if (Field_op0_Slot_inst_get (insn) == 0)
+ {
+ if (Field_op1_Slot_inst_get (insn) == 0)
+ {
+ if (Field_op2_Slot_inst_get (insn) == 0)
+ {
+ if (Field_r_Slot_inst_get (insn) == 0)
+ {
+ if (Field_m_Slot_inst_get (insn) == 0 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_n_Slot_inst_get (insn) == 0)
+ return OPCODE_ILL;
+ if (Field_m_Slot_inst_get (insn) == 2)
+ {
+ if (Field_n_Slot_inst_get (insn) == 0)
+ return OPCODE_RET;
+ if (Field_n_Slot_inst_get (insn) == 1)
+ return OPCODE_RETW;
+ if (Field_n_Slot_inst_get (insn) == 2)
+ return OPCODE_JX;
+ }
+ if (Field_m_Slot_inst_get (insn) == 3)
+ {
+ if (Field_n_Slot_inst_get (insn) == 0)
+ return OPCODE_CALLX0;
+ if (Field_n_Slot_inst_get (insn) == 1)
+ return OPCODE_CALLX4;
+ if (Field_n_Slot_inst_get (insn) == 2)
+ return OPCODE_CALLX8;
+ if (Field_n_Slot_inst_get (insn) == 3)
+ return OPCODE_CALLX12;
+ }
+ }
+ if (Field_r_Slot_inst_get (insn) == 1)
+ return OPCODE_MOVSP;
+ if (Field_r_Slot_inst_get (insn) == 2)
+ {
+ if (Field_s_Slot_inst_get (insn) == 0)
+ {
+ if (Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_ISYNC;
+ if (Field_t_Slot_inst_get (insn) == 1)
+ return OPCODE_RSYNC;
+ if (Field_t_Slot_inst_get (insn) == 2)
+ return OPCODE_ESYNC;
+ if (Field_t_Slot_inst_get (insn) == 3)
+ return OPCODE_DSYNC;
+ if (Field_t_Slot_inst_get (insn) == 8)
+ return OPCODE_EXCW;
+ if (Field_t_Slot_inst_get (insn) == 12)
+ return OPCODE_MEMW;
+ if (Field_t_Slot_inst_get (insn) == 13)
+ return OPCODE_EXTW;
+ if (Field_t_Slot_inst_get (insn) == 15)
+ return OPCODE_NOP;
+ }
+ }
+ if (Field_r_Slot_inst_get (insn) == 3)
+ {
+ if (Field_t_Slot_inst_get (insn) == 0)
+ {
+ if (Field_s_Slot_inst_get (insn) == 0)
+ return OPCODE_RFE;
+ if (Field_s_Slot_inst_get (insn) == 2)
+ return OPCODE_RFDE;
+ if (Field_s_Slot_inst_get (insn) == 4)
+ return OPCODE_RFWO;
+ if (Field_s_Slot_inst_get (insn) == 5)
+ return OPCODE_RFWU;
+ }
+ if (Field_t_Slot_inst_get (insn) == 1)
+ return OPCODE_RFI;
+ }
+ if (Field_r_Slot_inst_get (insn) == 4)
+ return OPCODE_BREAK;
+ if (Field_r_Slot_inst_get (insn) == 5)
+ {
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_SYSCALL;
+ if (Field_s_Slot_inst_get (insn) == 1 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_SIMCALL;
+ }
+ if (Field_r_Slot_inst_get (insn) == 6)
+ return OPCODE_RSIL;
+ if (Field_r_Slot_inst_get (insn) == 7 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_WAITI;
+ if (Field_r_Slot_inst_get (insn) == 7)
+ {
+ if (Field_t_Slot_inst_get (insn) == 14)
+ return OPCODE_LDDR32_P;
+ if (Field_t_Slot_inst_get (insn) == 15)
+ return OPCODE_SDDR32_P;
+ }
+ }
+ if (Field_op2_Slot_inst_get (insn) == 1)
+ return OPCODE_AND;
+ if (Field_op2_Slot_inst_get (insn) == 2)
+ return OPCODE_OR;
+ if (Field_op2_Slot_inst_get (insn) == 3)
+ return OPCODE_XOR;
+ if (Field_op2_Slot_inst_get (insn) == 4)
+ {
+ if (Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_SSR;
+ if (Field_r_Slot_inst_get (insn) == 1 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_SSL;
+ if (Field_r_Slot_inst_get (insn) == 2 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_SSA8L;
+ if (Field_r_Slot_inst_get (insn) == 3 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_SSA8B;
+ if (Field_r_Slot_inst_get (insn) == 4 &&
+ Field_thi3_Slot_inst_get (insn) == 0)
+ return OPCODE_SSAI;
+ if (Field_r_Slot_inst_get (insn) == 6)
+ return OPCODE_RER;
+ if (Field_r_Slot_inst_get (insn) == 7)
+ return OPCODE_WER;
+ if (Field_r_Slot_inst_get (insn) == 8 &&
+ Field_s_Slot_inst_get (insn) == 0)
+ return OPCODE_ROTW;
+ if (Field_r_Slot_inst_get (insn) == 14)
+ return OPCODE_NSA;
+ if (Field_r_Slot_inst_get (insn) == 15)
+ return OPCODE_NSAU;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 5)
+ {
+ if (Field_r_Slot_inst_get (insn) == 3)
+ return OPCODE_RITLB0;
+ if (Field_r_Slot_inst_get (insn) == 4 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_IITLB;
+ if (Field_r_Slot_inst_get (insn) == 5)
+ return OPCODE_PITLB;
+ if (Field_r_Slot_inst_get (insn) == 6)
+ return OPCODE_WITLB;
+ if (Field_r_Slot_inst_get (insn) == 7)
+ return OPCODE_RITLB1;
+ if (Field_r_Slot_inst_get (insn) == 11)
+ return OPCODE_RDTLB0;
+ if (Field_r_Slot_inst_get (insn) == 12 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_IDTLB;
+ if (Field_r_Slot_inst_get (insn) == 13)
+ return OPCODE_PDTLB;
+ if (Field_r_Slot_inst_get (insn) == 14)
+ return OPCODE_WDTLB;
+ if (Field_r_Slot_inst_get (insn) == 15)
+ return OPCODE_RDTLB1;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 6)
+ {
+ if (Field_s_Slot_inst_get (insn) == 0)
+ return OPCODE_NEG;
+ if (Field_s_Slot_inst_get (insn) == 1)
+ return OPCODE_ABS;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 8)
+ return OPCODE_ADD;
+ if (Field_op2_Slot_inst_get (insn) == 9)
+ return OPCODE_ADDX2;
+ if (Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_ADDX4;
+ if (Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_ADDX8;
+ if (Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_SUB;
+ if (Field_op2_Slot_inst_get (insn) == 13)
+ return OPCODE_SUBX2;
+ if (Field_op2_Slot_inst_get (insn) == 14)
+ return OPCODE_SUBX4;
+ if (Field_op2_Slot_inst_get (insn) == 15)
+ return OPCODE_SUBX8;
+ }
+ if (Field_op1_Slot_inst_get (insn) == 1)
+ {
+ if ((Field_op2_Slot_inst_get (insn) == 0 ||
+ Field_op2_Slot_inst_get (insn) == 1))
+ return OPCODE_SLLI;
+ if ((Field_op2_Slot_inst_get (insn) == 2 ||
+ Field_op2_Slot_inst_get (insn) == 3))
+ return OPCODE_SRAI;
+ if (Field_op2_Slot_inst_get (insn) == 4)
+ return OPCODE_SRLI;
+ if (Field_op2_Slot_inst_get (insn) == 6)
+ {
+ if (Field_sr_Slot_inst_get (insn) == 3)
+ return OPCODE_XSR_SAR;
+ if (Field_sr_Slot_inst_get (insn) == 5)
+ return OPCODE_XSR_LITBASE;
+ if (Field_sr_Slot_inst_get (insn) == 12)
+ return OPCODE_XSR_SCOMPARE1;
+ if (Field_sr_Slot_inst_get (insn) == 72)
+ return OPCODE_XSR_WINDOWBASE;
+ if (Field_sr_Slot_inst_get (insn) == 73)
+ return OPCODE_XSR_WINDOWSTART;
+ if (Field_sr_Slot_inst_get (insn) == 95)
+ return OPCODE_XSR_ERACCESS;
+ if (Field_sr_Slot_inst_get (insn) == 96)
+ return OPCODE_XSR_IBREAKENABLE;
+ if (Field_sr_Slot_inst_get (insn) == 97)
+ return OPCODE_XSR_MEMCTL;
+ if (Field_sr_Slot_inst_get (insn) == 99)
+ return OPCODE_XSR_ATOMCTL;
+ if (Field_sr_Slot_inst_get (insn) == 104)
+ return OPCODE_XSR_DDR;
+ if (Field_sr_Slot_inst_get (insn) == 128)
+ return OPCODE_XSR_IBREAKA0;
+ if (Field_sr_Slot_inst_get (insn) == 129)
+ return OPCODE_XSR_IBREAKA1;
+ if (Field_sr_Slot_inst_get (insn) == 144)
+ return OPCODE_XSR_DBREAKA0;
+ if (Field_sr_Slot_inst_get (insn) == 145)
+ return OPCODE_XSR_DBREAKA1;
+ if (Field_sr_Slot_inst_get (insn) == 160)
+ return OPCODE_XSR_DBREAKC0;
+ if (Field_sr_Slot_inst_get (insn) == 161)
+ return OPCODE_XSR_DBREAKC1;
+ if (Field_sr_Slot_inst_get (insn) == 177)
+ return OPCODE_XSR_EPC1;
+ if (Field_sr_Slot_inst_get (insn) == 178)
+ return OPCODE_XSR_EPC2;
+ if (Field_sr_Slot_inst_get (insn) == 179)
+ return OPCODE_XSR_EPC3;
+ if (Field_sr_Slot_inst_get (insn) == 180)
+ return OPCODE_XSR_EPC4;
+ if (Field_sr_Slot_inst_get (insn) == 181)
+ return OPCODE_XSR_EPC5;
+ if (Field_sr_Slot_inst_get (insn) == 182)
+ return OPCODE_XSR_EPC6;
+ if (Field_sr_Slot_inst_get (insn) == 183)
+ return OPCODE_XSR_EPC7;
+ if (Field_sr_Slot_inst_get (insn) == 192)
+ return OPCODE_XSR_DEPC;
+ if (Field_sr_Slot_inst_get (insn) == 194)
+ return OPCODE_XSR_EPS2;
+ if (Field_sr_Slot_inst_get (insn) == 195)
+ return OPCODE_XSR_EPS3;
+ if (Field_sr_Slot_inst_get (insn) == 196)
+ return OPCODE_XSR_EPS4;
+ if (Field_sr_Slot_inst_get (insn) == 197)
+ return OPCODE_XSR_EPS5;
+ if (Field_sr_Slot_inst_get (insn) == 198)
+ return OPCODE_XSR_EPS6;
+ if (Field_sr_Slot_inst_get (insn) == 199)
+ return OPCODE_XSR_EPS7;
+ if (Field_sr_Slot_inst_get (insn) == 209)
+ return OPCODE_XSR_EXCSAVE1;
+ if (Field_sr_Slot_inst_get (insn) == 210)
+ return OPCODE_XSR_EXCSAVE2;
+ if (Field_sr_Slot_inst_get (insn) == 211)
+ return OPCODE_XSR_EXCSAVE3;
+ if (Field_sr_Slot_inst_get (insn) == 212)
+ return OPCODE_XSR_EXCSAVE4;
+ if (Field_sr_Slot_inst_get (insn) == 213)
+ return OPCODE_XSR_EXCSAVE5;
+ if (Field_sr_Slot_inst_get (insn) == 214)
+ return OPCODE_XSR_EXCSAVE6;
+ if (Field_sr_Slot_inst_get (insn) == 215)
+ return OPCODE_XSR_EXCSAVE7;
+ if (Field_sr_Slot_inst_get (insn) == 228)
+ return OPCODE_XSR_INTENABLE;
+ if (Field_sr_Slot_inst_get (insn) == 230)
+ return OPCODE_XSR_PS;
+ if (Field_sr_Slot_inst_get (insn) == 231)
+ return OPCODE_XSR_VECBASE;
+ if (Field_sr_Slot_inst_get (insn) == 232)
+ return OPCODE_XSR_EXCCAUSE;
+ if (Field_sr_Slot_inst_get (insn) == 233)
+ return OPCODE_XSR_DEBUGCAUSE;
+ if (Field_sr_Slot_inst_get (insn) == 234)
+ return OPCODE_XSR_CCOUNT;
+ if (Field_sr_Slot_inst_get (insn) == 236)
+ return OPCODE_XSR_ICOUNT;
+ if (Field_sr_Slot_inst_get (insn) == 237)
+ return OPCODE_XSR_ICOUNTLEVEL;
+ if (Field_sr_Slot_inst_get (insn) == 238)
+ return OPCODE_XSR_EXCVADDR;
+ if (Field_sr_Slot_inst_get (insn) == 240)
+ return OPCODE_XSR_CCOMPARE0;
+ if (Field_sr_Slot_inst_get (insn) == 241)
+ return OPCODE_XSR_CCOMPARE1;
+ if (Field_sr_Slot_inst_get (insn) == 242)
+ return OPCODE_XSR_CCOMPARE2;
+ if (Field_sr_Slot_inst_get (insn) == 244)
+ return OPCODE_XSR_MISC0;
+ if (Field_sr_Slot_inst_get (insn) == 245)
+ return OPCODE_XSR_MISC1;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 8)
+ return OPCODE_SRC;
+ if (Field_op2_Slot_inst_get (insn) == 9 &&
+ Field_s_Slot_inst_get (insn) == 0)
+ return OPCODE_SRL;
+ if (Field_op2_Slot_inst_get (insn) == 10 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_SLL;
+ if (Field_op2_Slot_inst_get (insn) == 11 &&
+ Field_s_Slot_inst_get (insn) == 0)
+ return OPCODE_SRA;
+ if (Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_MUL16U;
+ if (Field_op2_Slot_inst_get (insn) == 13)
+ return OPCODE_MUL16S;
+ if (Field_op2_Slot_inst_get (insn) == 15)
+ {
+ if (Field_r_Slot_inst_get (insn) == 14 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_RFDO;
+ if (Field_r_Slot_inst_get (insn) == 14 &&
+ Field_t_Slot_inst_get (insn) == 1)
+ return OPCODE_RFDD;
+ }
+ }
+ if (Field_op1_Slot_inst_get (insn) == 2)
+ {
+ if (Field_op2_Slot_inst_get (insn) == 6)
+ return OPCODE_SALTU;
+ if (Field_op2_Slot_inst_get (insn) == 7)
+ return OPCODE_SALT;
+ if (Field_op2_Slot_inst_get (insn) == 8)
+ return OPCODE_MULL;
+ if (Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_QUOU;
+ if (Field_op2_Slot_inst_get (insn) == 13)
+ return OPCODE_QUOS;
+ if (Field_op2_Slot_inst_get (insn) == 14)
+ return OPCODE_REMU;
+ if (Field_op2_Slot_inst_get (insn) == 15)
+ return OPCODE_REMS;
+ }
+ if (Field_op1_Slot_inst_get (insn) == 3)
+ {
+ if (Field_op2_Slot_inst_get (insn) == 0)
+ {
+ if (Field_sr_Slot_inst_get (insn) == 3)
+ return OPCODE_RSR_SAR;
+ if (Field_sr_Slot_inst_get (insn) == 5)
+ return OPCODE_RSR_LITBASE;
+ if (Field_sr_Slot_inst_get (insn) == 12)
+ return OPCODE_RSR_SCOMPARE1;
+ if (Field_sr_Slot_inst_get (insn) == 72)
+ return OPCODE_RSR_WINDOWBASE;
+ if (Field_sr_Slot_inst_get (insn) == 73)
+ return OPCODE_RSR_WINDOWSTART;
+ if (Field_sr_Slot_inst_get (insn) == 95)
+ return OPCODE_RSR_ERACCESS;
+ if (Field_sr_Slot_inst_get (insn) == 96)
+ return OPCODE_RSR_IBREAKENABLE;
+ if (Field_sr_Slot_inst_get (insn) == 97)
+ return OPCODE_RSR_MEMCTL;
+ if (Field_sr_Slot_inst_get (insn) == 99)
+ return OPCODE_RSR_ATOMCTL;
+ if (Field_sr_Slot_inst_get (insn) == 104)
+ return OPCODE_RSR_DDR;
+ if (Field_sr_Slot_inst_get (insn) == 128)
+ return OPCODE_RSR_IBREAKA0;
+ if (Field_sr_Slot_inst_get (insn) == 129)
+ return OPCODE_RSR_IBREAKA1;
+ if (Field_sr_Slot_inst_get (insn) == 144)
+ return OPCODE_RSR_DBREAKA0;
+ if (Field_sr_Slot_inst_get (insn) == 145)
+ return OPCODE_RSR_DBREAKA1;
+ if (Field_sr_Slot_inst_get (insn) == 160)
+ return OPCODE_RSR_DBREAKC0;
+ if (Field_sr_Slot_inst_get (insn) == 161)
+ return OPCODE_RSR_DBREAKC1;
+ if (Field_sr_Slot_inst_get (insn) == 176)
+ return OPCODE_RSR_CONFIGID0;
+ if (Field_sr_Slot_inst_get (insn) == 177)
+ return OPCODE_RSR_EPC1;
+ if (Field_sr_Slot_inst_get (insn) == 178)
+ return OPCODE_RSR_EPC2;
+ if (Field_sr_Slot_inst_get (insn) == 179)
+ return OPCODE_RSR_EPC3;
+ if (Field_sr_Slot_inst_get (insn) == 180)
+ return OPCODE_RSR_EPC4;
+ if (Field_sr_Slot_inst_get (insn) == 181)
+ return OPCODE_RSR_EPC5;
+ if (Field_sr_Slot_inst_get (insn) == 182)
+ return OPCODE_RSR_EPC6;
+ if (Field_sr_Slot_inst_get (insn) == 183)
+ return OPCODE_RSR_EPC7;
+ if (Field_sr_Slot_inst_get (insn) == 192)
+ return OPCODE_RSR_DEPC;
+ if (Field_sr_Slot_inst_get (insn) == 194)
+ return OPCODE_RSR_EPS2;
+ if (Field_sr_Slot_inst_get (insn) == 195)
+ return OPCODE_RSR_EPS3;
+ if (Field_sr_Slot_inst_get (insn) == 196)
+ return OPCODE_RSR_EPS4;
+ if (Field_sr_Slot_inst_get (insn) == 197)
+ return OPCODE_RSR_EPS5;
+ if (Field_sr_Slot_inst_get (insn) == 198)
+ return OPCODE_RSR_EPS6;
+ if (Field_sr_Slot_inst_get (insn) == 199)
+ return OPCODE_RSR_EPS7;
+ if (Field_sr_Slot_inst_get (insn) == 208)
+ return OPCODE_RSR_CONFIGID1;
+ if (Field_sr_Slot_inst_get (insn) == 209)
+ return OPCODE_RSR_EXCSAVE1;
+ if (Field_sr_Slot_inst_get (insn) == 210)
+ return OPCODE_RSR_EXCSAVE2;
+ if (Field_sr_Slot_inst_get (insn) == 211)
+ return OPCODE_RSR_EXCSAVE3;
+ if (Field_sr_Slot_inst_get (insn) == 212)
+ return OPCODE_RSR_EXCSAVE4;
+ if (Field_sr_Slot_inst_get (insn) == 213)
+ return OPCODE_RSR_EXCSAVE5;
+ if (Field_sr_Slot_inst_get (insn) == 214)
+ return OPCODE_RSR_EXCSAVE6;
+ if (Field_sr_Slot_inst_get (insn) == 215)
+ return OPCODE_RSR_EXCSAVE7;
+ if (Field_sr_Slot_inst_get (insn) == 226)
+ return OPCODE_RSR_INTERRUPT;
+ if (Field_sr_Slot_inst_get (insn) == 228)
+ return OPCODE_RSR_INTENABLE;
+ if (Field_sr_Slot_inst_get (insn) == 230)
+ return OPCODE_RSR_PS;
+ if (Field_sr_Slot_inst_get (insn) == 231)
+ return OPCODE_RSR_VECBASE;
+ if (Field_sr_Slot_inst_get (insn) == 232)
+ return OPCODE_RSR_EXCCAUSE;
+ if (Field_sr_Slot_inst_get (insn) == 233)
+ return OPCODE_RSR_DEBUGCAUSE;
+ if (Field_sr_Slot_inst_get (insn) == 234)
+ return OPCODE_RSR_CCOUNT;
+ if (Field_sr_Slot_inst_get (insn) == 235)
+ return OPCODE_RSR_PRID;
+ if (Field_sr_Slot_inst_get (insn) == 236)
+ return OPCODE_RSR_ICOUNT;
+ if (Field_sr_Slot_inst_get (insn) == 237)
+ return OPCODE_RSR_ICOUNTLEVEL;
+ if (Field_sr_Slot_inst_get (insn) == 238)
+ return OPCODE_RSR_EXCVADDR;
+ if (Field_sr_Slot_inst_get (insn) == 240)
+ return OPCODE_RSR_CCOMPARE0;
+ if (Field_sr_Slot_inst_get (insn) == 241)
+ return OPCODE_RSR_CCOMPARE1;
+ if (Field_sr_Slot_inst_get (insn) == 242)
+ return OPCODE_RSR_CCOMPARE2;
+ if (Field_sr_Slot_inst_get (insn) == 244)
+ return OPCODE_RSR_MISC0;
+ if (Field_sr_Slot_inst_get (insn) == 245)
+ return OPCODE_RSR_MISC1;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 1)
+ {
+ if (Field_sr_Slot_inst_get (insn) == 3)
+ return OPCODE_WSR_SAR;
+ if (Field_sr_Slot_inst_get (insn) == 5)
+ return OPCODE_WSR_LITBASE;
+ if (Field_sr_Slot_inst_get (insn) == 12)
+ return OPCODE_WSR_SCOMPARE1;
+ if (Field_sr_Slot_inst_get (insn) == 72)
+ return OPCODE_WSR_WINDOWBASE;
+ if (Field_sr_Slot_inst_get (insn) == 73)
+ return OPCODE_WSR_WINDOWSTART;
+ if (Field_sr_Slot_inst_get (insn) == 89)
+ return OPCODE_WSR_MMID;
+ if (Field_sr_Slot_inst_get (insn) == 95)
+ return OPCODE_WSR_ERACCESS;
+ if (Field_sr_Slot_inst_get (insn) == 96)
+ return OPCODE_WSR_IBREAKENABLE;
+ if (Field_sr_Slot_inst_get (insn) == 97)
+ return OPCODE_WSR_MEMCTL;
+ if (Field_sr_Slot_inst_get (insn) == 99)
+ return OPCODE_WSR_ATOMCTL;
+ if (Field_sr_Slot_inst_get (insn) == 104)
+ return OPCODE_WSR_DDR;
+ if (Field_sr_Slot_inst_get (insn) == 128)
+ return OPCODE_WSR_IBREAKA0;
+ if (Field_sr_Slot_inst_get (insn) == 129)
+ return OPCODE_WSR_IBREAKA1;
+ if (Field_sr_Slot_inst_get (insn) == 144)
+ return OPCODE_WSR_DBREAKA0;
+ if (Field_sr_Slot_inst_get (insn) == 145)
+ return OPCODE_WSR_DBREAKA1;
+ if (Field_sr_Slot_inst_get (insn) == 160)
+ return OPCODE_WSR_DBREAKC0;
+ if (Field_sr_Slot_inst_get (insn) == 161)
+ return OPCODE_WSR_DBREAKC1;
+ if (Field_sr_Slot_inst_get (insn) == 176)
+ return OPCODE_WSR_CONFIGID0;
+ if (Field_sr_Slot_inst_get (insn) == 177)
+ return OPCODE_WSR_EPC1;
+ if (Field_sr_Slot_inst_get (insn) == 178)
+ return OPCODE_WSR_EPC2;
+ if (Field_sr_Slot_inst_get (insn) == 179)
+ return OPCODE_WSR_EPC3;
+ if (Field_sr_Slot_inst_get (insn) == 180)
+ return OPCODE_WSR_EPC4;
+ if (Field_sr_Slot_inst_get (insn) == 181)
+ return OPCODE_WSR_EPC5;
+ if (Field_sr_Slot_inst_get (insn) == 182)
+ return OPCODE_WSR_EPC6;
+ if (Field_sr_Slot_inst_get (insn) == 183)
+ return OPCODE_WSR_EPC7;
+ if (Field_sr_Slot_inst_get (insn) == 192)
+ return OPCODE_WSR_DEPC;
+ if (Field_sr_Slot_inst_get (insn) == 194)
+ return OPCODE_WSR_EPS2;
+ if (Field_sr_Slot_inst_get (insn) == 195)
+ return OPCODE_WSR_EPS3;
+ if (Field_sr_Slot_inst_get (insn) == 196)
+ return OPCODE_WSR_EPS4;
+ if (Field_sr_Slot_inst_get (insn) == 197)
+ return OPCODE_WSR_EPS5;
+ if (Field_sr_Slot_inst_get (insn) == 198)
+ return OPCODE_WSR_EPS6;
+ if (Field_sr_Slot_inst_get (insn) == 199)
+ return OPCODE_WSR_EPS7;
+ if (Field_sr_Slot_inst_get (insn) == 209)
+ return OPCODE_WSR_EXCSAVE1;
+ if (Field_sr_Slot_inst_get (insn) == 210)
+ return OPCODE_WSR_EXCSAVE2;
+ if (Field_sr_Slot_inst_get (insn) == 211)
+ return OPCODE_WSR_EXCSAVE3;
+ if (Field_sr_Slot_inst_get (insn) == 212)
+ return OPCODE_WSR_EXCSAVE4;
+ if (Field_sr_Slot_inst_get (insn) == 213)
+ return OPCODE_WSR_EXCSAVE5;
+ if (Field_sr_Slot_inst_get (insn) == 214)
+ return OPCODE_WSR_EXCSAVE6;
+ if (Field_sr_Slot_inst_get (insn) == 215)
+ return OPCODE_WSR_EXCSAVE7;
+ if (Field_sr_Slot_inst_get (insn) == 226)
+ return OPCODE_WSR_INTSET;
+ if (Field_sr_Slot_inst_get (insn) == 227)
+ return OPCODE_WSR_INTCLEAR;
+ if (Field_sr_Slot_inst_get (insn) == 228)
+ return OPCODE_WSR_INTENABLE;
+ if (Field_sr_Slot_inst_get (insn) == 230)
+ return OPCODE_WSR_PS;
+ if (Field_sr_Slot_inst_get (insn) == 231)
+ return OPCODE_WSR_VECBASE;
+ if (Field_sr_Slot_inst_get (insn) == 232)
+ return OPCODE_WSR_EXCCAUSE;
+ if (Field_sr_Slot_inst_get (insn) == 233)
+ return OPCODE_WSR_DEBUGCAUSE;
+ if (Field_sr_Slot_inst_get (insn) == 234)
+ return OPCODE_WSR_CCOUNT;
+ if (Field_sr_Slot_inst_get (insn) == 236)
+ return OPCODE_WSR_ICOUNT;
+ if (Field_sr_Slot_inst_get (insn) == 237)
+ return OPCODE_WSR_ICOUNTLEVEL;
+ if (Field_sr_Slot_inst_get (insn) == 238)
+ return OPCODE_WSR_EXCVADDR;
+ if (Field_sr_Slot_inst_get (insn) == 240)
+ return OPCODE_WSR_CCOMPARE0;
+ if (Field_sr_Slot_inst_get (insn) == 241)
+ return OPCODE_WSR_CCOMPARE1;
+ if (Field_sr_Slot_inst_get (insn) == 242)
+ return OPCODE_WSR_CCOMPARE2;
+ if (Field_sr_Slot_inst_get (insn) == 244)
+ return OPCODE_WSR_MISC0;
+ if (Field_sr_Slot_inst_get (insn) == 245)
+ return OPCODE_WSR_MISC1;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 2)
+ return OPCODE_SEXT;
+ if (Field_op2_Slot_inst_get (insn) == 4)
+ return OPCODE_MIN;
+ if (Field_op2_Slot_inst_get (insn) == 5)
+ return OPCODE_MAX;
+ if (Field_op2_Slot_inst_get (insn) == 6)
+ return OPCODE_MINU;
+ if (Field_op2_Slot_inst_get (insn) == 7)
+ return OPCODE_MAXU;
+ if (Field_op2_Slot_inst_get (insn) == 8)
+ return OPCODE_MOVEQZ;
+ if (Field_op2_Slot_inst_get (insn) == 9)
+ return OPCODE_MOVNEZ;
+ if (Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_MOVLTZ;
+ if (Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_MOVGEZ;
+ if (Field_op2_Slot_inst_get (insn) == 14)
+ {
+ if (Field_st_Slot_inst_get (insn) == 230)
+ return OPCODE_RUR_EXPSTATE;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 15)
+ {
+ if (Field_sr_Slot_inst_get (insn) == 230)
+ return OPCODE_WUR_EXPSTATE;
+ }
+ }
+ if ((Field_op1_Slot_inst_get (insn) == 4 ||
+ Field_op1_Slot_inst_get (insn) == 5))
+ return OPCODE_EXTUI;
+ if (Field_op1_Slot_inst_get (insn) == 9)
+ {
+ if (Field_op2_Slot_inst_get (insn) == 0)
+ return OPCODE_L32E;
+ if (Field_op2_Slot_inst_get (insn) == 4)
+ return OPCODE_S32E;
+ if (Field_op2_Slot_inst_get (insn) == 5)
+ return OPCODE_S32NB;
+ }
+ if (Field_r_Slot_inst_get (insn) == 0 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_op2_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 14)
+ return OPCODE_READ_IMPWIRE;
+ if (Field_r_Slot_inst_get (insn) == 1 &&
+ Field_s3to1_Slot_inst_get (insn) == 0 &&
+ Field_op2_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 14)
+ return OPCODE_SETB_EXPSTATE;
+ if (Field_r_Slot_inst_get (insn) == 1 &&
+ Field_s3to1_Slot_inst_get (insn) == 1 &&
+ Field_op2_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 14)
+ return OPCODE_CLRB_EXPSTATE;
+ if (Field_r_Slot_inst_get (insn) == 2 &&
+ Field_op2_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 14)
+ return OPCODE_WRMSK_EXPSTATE;
+ }
+ if (Field_op0_Slot_inst_get (insn) == 1)
+ return OPCODE_L32R;
+ if (Field_op0_Slot_inst_get (insn) == 2)
+ {
+ if (Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_L8UI;
+ if (Field_r_Slot_inst_get (insn) == 1)
+ return OPCODE_L16UI;
+ if (Field_r_Slot_inst_get (insn) == 2)
+ return OPCODE_L32I;
+ if (Field_r_Slot_inst_get (insn) == 4)
+ return OPCODE_S8I;
+ if (Field_r_Slot_inst_get (insn) == 5)
+ return OPCODE_S16I;
+ if (Field_r_Slot_inst_get (insn) == 6)
+ return OPCODE_S32I;
+ if (Field_r_Slot_inst_get (insn) == 9)
+ return OPCODE_L16SI;
+ if (Field_r_Slot_inst_get (insn) == 10)
+ return OPCODE_MOVI;
+ if (Field_r_Slot_inst_get (insn) == 11)
+ return OPCODE_L32AI;
+ if (Field_r_Slot_inst_get (insn) == 12)
+ return OPCODE_ADDI;
+ if (Field_r_Slot_inst_get (insn) == 13)
+ return OPCODE_ADDMI;
+ if (Field_r_Slot_inst_get (insn) == 14)
+ return OPCODE_S32C1I;
+ if (Field_r_Slot_inst_get (insn) == 15)
+ return OPCODE_S32RI;
+ }
+ if (Field_op0_Slot_inst_get (insn) == 5)
+ {
+ if (Field_n_Slot_inst_get (insn) == 0)
+ return OPCODE_CALL0;
+ if (Field_n_Slot_inst_get (insn) == 1)
+ return OPCODE_CALL4;
+ if (Field_n_Slot_inst_get (insn) == 2)
+ return OPCODE_CALL8;
+ if (Field_n_Slot_inst_get (insn) == 3)
+ return OPCODE_CALL12;
+ }
+ if (Field_op0_Slot_inst_get (insn) == 6)
+ {
+ if (Field_n_Slot_inst_get (insn) == 0)
+ return OPCODE_J;
+ if (Field_n_Slot_inst_get (insn) == 1)
+ {
+ if (Field_m_Slot_inst_get (insn) == 0)
+ return OPCODE_BEQZ;
+ if (Field_m_Slot_inst_get (insn) == 1)
+ return OPCODE_BNEZ;
+ if (Field_m_Slot_inst_get (insn) == 2)
+ return OPCODE_BLTZ;
+ if (Field_m_Slot_inst_get (insn) == 3)
+ return OPCODE_BGEZ;
+ }
+ if (Field_n_Slot_inst_get (insn) == 2)
+ {
+ if (Field_m_Slot_inst_get (insn) == 0)
+ return OPCODE_BEQI;
+ if (Field_m_Slot_inst_get (insn) == 1)
+ return OPCODE_BNEI;
+ if (Field_m_Slot_inst_get (insn) == 2)
+ return OPCODE_BLTI;
+ if (Field_m_Slot_inst_get (insn) == 3)
+ return OPCODE_BGEI;
+ }
+ if (Field_n_Slot_inst_get (insn) == 3)
+ {
+ if (Field_m_Slot_inst_get (insn) == 0)
+ return OPCODE_ENTRY;
+ if (Field_m_Slot_inst_get (insn) == 2)
+ return OPCODE_BLTUI;
+ if (Field_m_Slot_inst_get (insn) == 3)
+ return OPCODE_BGEUI;
+ }
+ }
+ if (Field_op0_Slot_inst_get (insn) == 7)
+ {
+ if (Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_BNONE;
+ if (Field_r_Slot_inst_get (insn) == 1)
+ return OPCODE_BEQ;
+ if (Field_r_Slot_inst_get (insn) == 2)
+ return OPCODE_BLT;
+ if (Field_r_Slot_inst_get (insn) == 3)
+ return OPCODE_BLTU;
+ if (Field_r_Slot_inst_get (insn) == 4)
+ return OPCODE_BALL;
+ if (Field_r_Slot_inst_get (insn) == 5)
+ return OPCODE_BBC;
+ if ((Field_r_Slot_inst_get (insn) == 6 ||
+ Field_r_Slot_inst_get (insn) == 7))
+ return OPCODE_BBCI;
+ if (Field_r_Slot_inst_get (insn) == 8)
+ return OPCODE_BANY;
+ if (Field_r_Slot_inst_get (insn) == 9)
+ return OPCODE_BNE;
+ if (Field_r_Slot_inst_get (insn) == 10)
+ return OPCODE_BGE;
+ if (Field_r_Slot_inst_get (insn) == 11)
+ return OPCODE_BGEU;
+ if (Field_r_Slot_inst_get (insn) == 12)
+ return OPCODE_BNALL;
+ if (Field_r_Slot_inst_get (insn) == 13)
+ return OPCODE_BBS;
+ if ((Field_r_Slot_inst_get (insn) == 14 ||
+ Field_r_Slot_inst_get (insn) == 15))
+ return OPCODE_BBSI;
+ }
+ return XTENSA_UNDEFINED;
+}
+
+static int
+Slot_inst16b_decode (const xtensa_insnbuf insn)
+{
+ if (Field_op0_Slot_inst16b_get (insn) == 12)
+ {
+ if (Field_i_Slot_inst16b_get (insn) == 0)
+ return OPCODE_MOVI_N;
+ if (Field_i_Slot_inst16b_get (insn) == 1)
+ {
+ if (Field_z_Slot_inst16b_get (insn) == 0)
+ return OPCODE_BEQZ_N;
+ if (Field_z_Slot_inst16b_get (insn) == 1)
+ return OPCODE_BNEZ_N;
+ }
+ }
+ if (Field_op0_Slot_inst16b_get (insn) == 13)
+ {
+ if (Field_r_Slot_inst16b_get (insn) == 0)
+ return OPCODE_MOV_N;
+ if (Field_r_Slot_inst16b_get (insn) == 15)
+ {
+ if (Field_t_Slot_inst16b_get (insn) == 0)
+ return OPCODE_RET_N;
+ if (Field_t_Slot_inst16b_get (insn) == 1)
+ return OPCODE_RETW_N;
+ if (Field_t_Slot_inst16b_get (insn) == 2)
+ return OPCODE_BREAK_N;
+ if (Field_t_Slot_inst16b_get (insn) == 3 &&
+ Field_s_Slot_inst16b_get (insn) == 0)
+ return OPCODE_NOP_N;
+ if (Field_t_Slot_inst16b_get (insn) == 6 &&
+ Field_s_Slot_inst16b_get (insn) == 0)
+ return OPCODE_ILL_N;
+ }
+ }
+ return XTENSA_UNDEFINED;
+}
+
+static int
+Slot_inst16a_decode (const xtensa_insnbuf insn)
+{
+ if (Field_op0_Slot_inst16a_get (insn) == 8)
+ return OPCODE_L32I_N;
+ if (Field_op0_Slot_inst16a_get (insn) == 9)
+ return OPCODE_S32I_N;
+ if (Field_op0_Slot_inst16a_get (insn) == 10)
+ return OPCODE_ADD_N;
+ if (Field_op0_Slot_inst16a_get (insn) == 11)
+ return OPCODE_ADDI_N;
+ return XTENSA_UNDEFINED;
+}
+
+
+/* Instruction slots. */
+
+static void
+Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn,
+ xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = (insn[0] & 0xffffff);
+}
+
+static void
+Slot_x24_Format_inst_0_set (xtensa_insnbuf insn,
+ const xtensa_insnbuf slotbuf)
+{
+ insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff);
+}
+
+static void
+Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn,
+ xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = (insn[0] & 0xffff);
+}
+
+static void
+Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn,
+ const xtensa_insnbuf slotbuf)
+{
+ insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
+}
+
+static void
+Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn,
+ xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = (insn[0] & 0xffff);
+}
+
+static void
+Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn,
+ const xtensa_insnbuf slotbuf)
+{
+ insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
+}
+
+static xtensa_get_field_fn
+Slot_inst_get_field_fns[] = {
+ Field_t_Slot_inst_get,
+ Field_bbi4_Slot_inst_get,
+ Field_bbi_Slot_inst_get,
+ Field_imm12_Slot_inst_get,
+ Field_imm8_Slot_inst_get,
+ Field_s_Slot_inst_get,
+ Field_imm12b_Slot_inst_get,
+ Field_imm16_Slot_inst_get,
+ Field_m_Slot_inst_get,
+ Field_n_Slot_inst_get,
+ Field_offset_Slot_inst_get,
+ Field_op0_Slot_inst_get,
+ Field_op1_Slot_inst_get,
+ Field_op2_Slot_inst_get,
+ Field_r_Slot_inst_get,
+ Field_sa4_Slot_inst_get,
+ Field_sae4_Slot_inst_get,
+ Field_sae_Slot_inst_get,
+ Field_sal_Slot_inst_get,
+ Field_sargt_Slot_inst_get,
+ Field_sas4_Slot_inst_get,
+ Field_sas_Slot_inst_get,
+ Field_sr_Slot_inst_get,
+ Field_st_Slot_inst_get,
+ Field_thi3_Slot_inst_get,
+ Field_imm4_Slot_inst_get,
+ Field_mn_Slot_inst_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_xt_wbr15_imm_Slot_inst_get,
+ Field_xt_wbr18_imm_Slot_inst_get,
+ Field_bitindex_Slot_inst_get,
+ Field_s3to1_Slot_inst_get,
+ Implicit_Field_ar0_get,
+ Implicit_Field_ar4_get,
+ Implicit_Field_ar8_get,
+ Implicit_Field_ar12_get
+};
+
+static xtensa_set_field_fn
+Slot_inst_set_field_fns[] = {
+ Field_t_Slot_inst_set,
+ Field_bbi4_Slot_inst_set,
+ Field_bbi_Slot_inst_set,
+ Field_imm12_Slot_inst_set,
+ Field_imm8_Slot_inst_set,
+ Field_s_Slot_inst_set,
+ Field_imm12b_Slot_inst_set,
+ Field_imm16_Slot_inst_set,
+ Field_m_Slot_inst_set,
+ Field_n_Slot_inst_set,
+ Field_offset_Slot_inst_set,
+ Field_op0_Slot_inst_set,
+ Field_op1_Slot_inst_set,
+ Field_op2_Slot_inst_set,
+ Field_r_Slot_inst_set,
+ Field_sa4_Slot_inst_set,
+ Field_sae4_Slot_inst_set,
+ Field_sae_Slot_inst_set,
+ Field_sal_Slot_inst_set,
+ Field_sargt_Slot_inst_set,
+ Field_sas4_Slot_inst_set,
+ Field_sas_Slot_inst_set,
+ Field_sr_Slot_inst_set,
+ Field_st_Slot_inst_set,
+ Field_thi3_Slot_inst_set,
+ Field_imm4_Slot_inst_set,
+ Field_mn_Slot_inst_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_xt_wbr15_imm_Slot_inst_set,
+ Field_xt_wbr18_imm_Slot_inst_set,
+ Field_bitindex_Slot_inst_set,
+ Field_s3to1_Slot_inst_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set
+};
+
+static xtensa_get_field_fn
+Slot_inst16a_get_field_fns[] = {
+ Field_t_Slot_inst16a_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_s_Slot_inst16a_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_op0_Slot_inst16a_get,
+ 0,
+ 0,
+ Field_r_Slot_inst16a_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_sr_Slot_inst16a_get,
+ Field_st_Slot_inst16a_get,
+ 0,
+ Field_imm4_Slot_inst16a_get,
+ 0,
+ Field_i_Slot_inst16a_get,
+ Field_imm6lo_Slot_inst16a_get,
+ Field_imm6hi_Slot_inst16a_get,
+ Field_imm7lo_Slot_inst16a_get,
+ Field_imm7hi_Slot_inst16a_get,
+ Field_z_Slot_inst16a_get,
+ Field_imm6_Slot_inst16a_get,
+ Field_imm7_Slot_inst16a_get,
+ 0,
+ 0,
+ Field_bitindex_Slot_inst16a_get,
+ Field_s3to1_Slot_inst16a_get,
+ Implicit_Field_ar0_get,
+ Implicit_Field_ar4_get,
+ Implicit_Field_ar8_get,
+ Implicit_Field_ar12_get
+};
+
+static xtensa_set_field_fn
+Slot_inst16a_set_field_fns[] = {
+ Field_t_Slot_inst16a_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_s_Slot_inst16a_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_op0_Slot_inst16a_set,
+ 0,
+ 0,
+ Field_r_Slot_inst16a_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_sr_Slot_inst16a_set,
+ Field_st_Slot_inst16a_set,
+ 0,
+ Field_imm4_Slot_inst16a_set,
+ 0,
+ Field_i_Slot_inst16a_set,
+ Field_imm6lo_Slot_inst16a_set,
+ Field_imm6hi_Slot_inst16a_set,
+ Field_imm7lo_Slot_inst16a_set,
+ Field_imm7hi_Slot_inst16a_set,
+ Field_z_Slot_inst16a_set,
+ Field_imm6_Slot_inst16a_set,
+ Field_imm7_Slot_inst16a_set,
+ 0,
+ 0,
+ Field_bitindex_Slot_inst16a_set,
+ Field_s3to1_Slot_inst16a_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set
+};
+
+static xtensa_get_field_fn
+Slot_inst16b_get_field_fns[] = {
+ Field_t_Slot_inst16b_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_s_Slot_inst16b_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_op0_Slot_inst16b_get,
+ 0,
+ 0,
+ Field_r_Slot_inst16b_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_sr_Slot_inst16b_get,
+ Field_st_Slot_inst16b_get,
+ 0,
+ Field_imm4_Slot_inst16b_get,
+ 0,
+ Field_i_Slot_inst16b_get,
+ Field_imm6lo_Slot_inst16b_get,
+ Field_imm6hi_Slot_inst16b_get,
+ Field_imm7lo_Slot_inst16b_get,
+ Field_imm7hi_Slot_inst16b_get,
+ Field_z_Slot_inst16b_get,
+ Field_imm6_Slot_inst16b_get,
+ Field_imm7_Slot_inst16b_get,
+ 0,
+ 0,
+ Field_bitindex_Slot_inst16b_get,
+ Field_s3to1_Slot_inst16b_get,
+ Implicit_Field_ar0_get,
+ Implicit_Field_ar4_get,
+ Implicit_Field_ar8_get,
+ Implicit_Field_ar12_get
+};
+
+static xtensa_set_field_fn
+Slot_inst16b_set_field_fns[] = {
+ Field_t_Slot_inst16b_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_s_Slot_inst16b_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_op0_Slot_inst16b_set,
+ 0,
+ 0,
+ Field_r_Slot_inst16b_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_sr_Slot_inst16b_set,
+ Field_st_Slot_inst16b_set,
+ 0,
+ Field_imm4_Slot_inst16b_set,
+ 0,
+ Field_i_Slot_inst16b_set,
+ Field_imm6lo_Slot_inst16b_set,
+ Field_imm6hi_Slot_inst16b_set,
+ Field_imm7lo_Slot_inst16b_set,
+ Field_imm7hi_Slot_inst16b_set,
+ Field_z_Slot_inst16b_set,
+ Field_imm6_Slot_inst16b_set,
+ Field_imm7_Slot_inst16b_set,
+ 0,
+ 0,
+ Field_bitindex_Slot_inst16b_set,
+ Field_s3to1_Slot_inst16b_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set
+};
+
+static xtensa_slot_internal slots[] = {
+ { "Inst", "x24", 0,
+ Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set,
+ Slot_inst_get_field_fns, Slot_inst_set_field_fns,
+ Slot_inst_decode, "nop" },
+ { "Inst16a", "x16a", 0,
+ Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set,
+ Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns,
+ Slot_inst16a_decode, "" },
+ { "Inst16b", "x16b", 0,
+ Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set,
+ Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns,
+ Slot_inst16b_decode, "nop.n" }
+};
+
+
+/* Instruction formats. */
+
+static void
+Format_x24_encode (xtensa_insnbuf insn)
+{
+ insn[0] = 0;
+}
+
+static void
+Format_x16a_encode (xtensa_insnbuf insn)
+{
+ insn[0] = 0x8;
+}
+
+static void
+Format_x16b_encode (xtensa_insnbuf insn)
+{
+ insn[0] = 0xc;
+}
+
+static int Format_x24_slots[] = { 0 };
+
+static int Format_x16a_slots[] = { 1 };
+
+static int Format_x16b_slots[] = { 2 };
+
+static xtensa_format_internal formats[] = {
+ { "x24", 3, Format_x24_encode, 1, Format_x24_slots },
+ { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots },
+ { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots }
+};
+
+
+static int
+format_decoder (const xtensa_insnbuf insn)
+{
+ if ((insn[0] & 0x8) == 0)
+ return 0; /* x24 */
+ if ((insn[0] & 0xc) == 0x8)
+ return 1; /* x16a */
+ if ((insn[0] & 0xe) == 0xc)
+ return 2; /* x16b */
+ return -1;
+}
+
+static int length_table[256] = {
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1
+};
+
+static int
+length_decoder (const unsigned char *insn)
+{
+ int l = insn[0];
+ return length_table[l];
+}
+
+
+/* Top-level ISA structure. */
+
+xtensa_isa_internal xtensa_modules = {
+ 0 /* little-endian */,
+ 3 /* insn_size */, 0,
+ 3, formats, format_decoder, length_decoder,
+ 3, slots,
+ 43 /* num_fields */,
+ 77, operands,
+ 263, iclasses,
+ 317, opcodes, 0,
+ 1, regfiles,
+ NUM_STATES, states, 0,
+ NUM_SYSREGS, sysregs, 0,
+ { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 },
+ 1, interfaces, 0,
+ 0, funcUnits, 0
+};
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index d9404aa..f300c02 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -503,10 +503,15 @@
#ifdef TARGET_WORDS_BIGENDIAN
#define XTENSA_DEFAULT_CPU_MODEL "fsf"
+#define XTENSA_DEFAULT_CPU_NOMMU_MODEL "fsf"
#else
#define XTENSA_DEFAULT_CPU_MODEL "dc232b"
+#define XTENSA_DEFAULT_CPU_NOMMU_MODEL "de212"
#endif
-#define XTENSA_DEFAULT_CPU_TYPE XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_MODEL)
+#define XTENSA_DEFAULT_CPU_TYPE \
+ XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_MODEL)
+#define XTENSA_DEFAULT_CPU_NOMMU_TYPE \
+ XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_NOMMU_MODEL)
#define cpu_init(cpu_model) cpu_generic_init(TYPE_XTENSA_CPU, cpu_model)
diff --git a/target/xtensa/overlay_tool.h b/target/xtensa/overlay_tool.h
index 12bde44..589dd62 100644
--- a/target/xtensa/overlay_tool.h
+++ b/target/xtensa/overlay_tool.h
@@ -342,24 +342,24 @@
.dtlb = TLB_TEMPLATE
#ifndef XCHAL_SYSROM0_PADDR
-#define XCHAL_SYSROM0_PADDR 0x60000000
+#define XCHAL_SYSROM0_PADDR 0x50000000
#define XCHAL_SYSROM0_SIZE 0x04000000
#endif
#ifndef XCHAL_SYSRAM0_PADDR
-#define XCHAL_SYSRAM0_PADDR 0x50000000
+#define XCHAL_SYSRAM0_PADDR 0x60000000
#define XCHAL_SYSRAM0_SIZE 0x04000000
#endif
#else
#ifndef XCHAL_SYSROM0_PADDR
-#define XCHAL_SYSROM0_PADDR 0x60000000
+#define XCHAL_SYSROM0_PADDR 0x50000000
#define XCHAL_SYSROM0_SIZE 0x04000000
#endif
#ifndef XCHAL_SYSRAM0_PADDR
-#define XCHAL_SYSRAM0_PADDR 0x50000000
+#define XCHAL_SYSRAM0_PADDR 0x60000000
#define XCHAL_SYSRAM0_SIZE 0x04000000
#endif
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index bec9efc..671d934 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -942,7 +942,7 @@
unsigned char b[MAX_INSN_LENGTH] = {cpu_ldub_code(env, dc->pc)};
unsigned len = xtensa_op0_insn_len(dc, b[0]);
xtensa_format fmt;
- unsigned slot, slots;
+ int slot, slots;
unsigned i;
if (len == XTENSA_UNDEFINED) {
@@ -969,7 +969,7 @@
slots = xtensa_format_num_slots(isa, fmt);
for (slot = 0; slot < slots; ++slot) {
xtensa_opcode opc;
- unsigned opnd, vopnd, opnds;
+ int opnd, vopnd, opnds;
uint32_t raw_arg[MAX_OPCODE_ARGS];
uint32_t arg[MAX_OPCODE_ARGS];
XtensaOpcodeOps *ops;
diff --git a/tests/.gitignore b/tests/.gitignore
index 74e55d7..e5c744b 100644
--- a/tests/.gitignore
+++ b/tests/.gitignore
@@ -18,6 +18,7 @@
test-aio-multithread
test-arm-mptimer
test-base64
+test-bdrv-drain
test-bitops
test-bitcnt
test-blockjob
diff --git a/tests/ahci-test.c b/tests/ahci-test.c
index cb84edc..3934e62 100644
--- a/tests/ahci-test.c
+++ b/tests/ahci-test.c
@@ -1578,9 +1578,9 @@
QDict *rsp;
fd = prepare_iso(iso_size, &tx, &iso);
- ahci = ahci_boot_and_enable("-drive if=none,id=drive0,file=%s,format=raw "
+ ahci = ahci_boot_and_enable("-blockdev node-name=drive0,driver=file,filename=%s "
"-M q35 "
- "-device ide-cd,drive=drive0 ", iso);
+ "-device ide-cd,id=cd0,drive=drive0 ", iso);
port = ahci_port_select(ahci);
ahci_atapi_eject(ahci, port);
@@ -1591,13 +1591,13 @@
/* Remove media */
qmp_async("{'execute': 'blockdev-open-tray', "
- "'arguments': {'device': 'drive0'}}");
+ "'arguments': {'id': 'cd0'}}");
atapi_wait_tray(true);
rsp = qmp_receive();
QDECREF(rsp);
- qmp_discard_response("{'execute': 'x-blockdev-remove-medium', "
- "'arguments': {'device': 'drive0'}}");
+ qmp_discard_response("{'execute': 'blockdev-remove-medium', "
+ "'arguments': {'id': 'cd0'}}");
/* Test the tray without a medium */
ahci_atapi_load(ahci, port);
@@ -1612,13 +1612,13 @@
"'driver': 'raw', "
"'file': { 'driver': 'file', "
"'filename': %s }}}", iso);
- qmp_discard_response("{'execute': 'x-blockdev-insert-medium',"
- "'arguments': { 'device': 'drive0', "
+ qmp_discard_response("{'execute': 'blockdev-insert-medium',"
+ "'arguments': { 'id': 'cd0', "
"'node-name': 'node0' }}");
/* Again, the event shows up first */
qmp_async("{'execute': 'blockdev-close-tray', "
- "'arguments': {'device': 'drive0'}}");
+ "'arguments': {'id': 'cd0'}}");
atapi_wait_tray(false);
rsp = qmp_receive();
QDECREF(rsp);
diff --git a/tests/qemu-iotests/020 b/tests/qemu-iotests/020
index cefe3a8..eac5080 100755
--- a/tests/qemu-iotests/020
+++ b/tests/qemu-iotests/020
@@ -42,18 +42,12 @@
# Any format supporting backing files
_supported_fmt qcow qcow2 vmdk qed
-_supported_proto generic
-_unsupported_proto vxhs
+_supported_proto file
_supported_os Linux
_unsupported_imgopts "subformat=monolithicFlat" \
"subformat=twoGbMaxExtentFlat" \
"subformat=twoGbMaxExtentSparse"
-# NFS does not support bdrv_reopen_prepare thus qemu-img commit fails.
-if [ "$IMGPROTO" = "nfs" ]; then
- _notrun "image protocol $IMGPROTO does not support bdrv_commit"
-fi
-
TEST_OFFSETS="0 4294967296"
TEST_IMG_SAVE="$TEST_IMG"
@@ -117,10 +111,12 @@
echo 'Testing failing commit'
echo
+TEST_IMG="$TEST_IMG.base" _make_test_img 1M
+
# Create an image with a null backing file to which committing will fail (with
# ENOSPC so we can distinguish the result from some generic EIO which may be
# generated anywhere in the block layer)
-_make_test_img -b "json:{'driver': 'raw',
+_make_test_img -b "json:{'driver': '$IMGFMT',
'file': {
'driver': 'blkdebug',
'inject-error': [{
@@ -129,14 +125,15 @@
'once': true
}],
'image': {
- 'driver': 'null-co'
+ 'driver': 'file',
+ 'filename': '$TEST_IMG.base'
}}}"
# Just write anything so committing will not be a no-op
$QEMU_IO -c 'writev 0 64k' "$TEST_IMG" | _filter_qemu_io
$QEMU_IMG commit "$TEST_IMG"
-_cleanup_test_img
+_cleanup
# success, all done
echo "*** done"
diff --git a/tests/qemu-iotests/020.out b/tests/qemu-iotests/020.out
index 165b70a..4b722b2 100644
--- a/tests/qemu-iotests/020.out
+++ b/tests/qemu-iotests/020.out
@@ -1078,7 +1078,8 @@
Testing failing commit
-Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 backing_file=json:{'driver': 'raw',,
+Formatting 'TEST_DIR/t.IMGFMT.base', fmt=IMGFMT size=1048576
+Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1048576 backing_file=json:{'driver': 'IMGFMT',,
'file': {
'driver': 'blkdebug',,
'inject-error': [{
@@ -1087,7 +1088,8 @@
'once': true
}],,
'image': {
- 'driver': 'null-co'
+ 'driver': 'file',,
+ 'filename': 'TEST_DIR/t.IMGFMT.base'
}}}
wrote 65536/65536 bytes at offset 0
64 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
diff --git a/tests/qemu-iotests/051 b/tests/qemu-iotests/051
index dba8816..0c3be16 100755
--- a/tests/qemu-iotests/051
+++ b/tests/qemu-iotests/051
@@ -131,6 +131,8 @@
echo === Enable and disable lazy refcounting on the command line, plus some invalid values ===
echo
+_make_test_img -o compat=1.1 "$size"
+
run_qemu -drive file="$TEST_IMG",format=qcow2,lazy-refcounts=on
run_qemu -drive file="$TEST_IMG",format=qcow2,lazy-refcounts=off
run_qemu -drive file="$TEST_IMG",format=qcow2,lazy-refcounts=
diff --git a/tests/qemu-iotests/051.out b/tests/qemu-iotests/051.out
index e3c6eab..dd9846d 100644
--- a/tests/qemu-iotests/051.out
+++ b/tests/qemu-iotests/051.out
@@ -77,6 +77,7 @@
=== Enable and disable lazy refcounting on the command line, plus some invalid values ===
+Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=134217728
Testing: -drive file=TEST_DIR/t.qcow2,format=qcow2,lazy-refcounts=on
QEMU X.Y.Z monitor - type 'help' for more information
(qemu) quit
diff --git a/tests/qemu-iotests/051.pc.out b/tests/qemu-iotests/051.pc.out
index f2c5622..830c118 100644
--- a/tests/qemu-iotests/051.pc.out
+++ b/tests/qemu-iotests/051.pc.out
@@ -77,6 +77,7 @@
=== Enable and disable lazy refcounting on the command line, plus some invalid values ===
+Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=134217728
Testing: -drive file=TEST_DIR/t.qcow2,format=qcow2,lazy-refcounts=on
QEMU X.Y.Z monitor - type 'help' for more information
(qemu) quit
diff --git a/tests/qemu-iotests/059 b/tests/qemu-iotests/059
index a1c34ee..40f89ea 100755
--- a/tests/qemu-iotests/059
+++ b/tests/qemu-iotests/059
@@ -152,7 +152,9 @@
echo
echo "=== Testing afl image with a very large capacity ==="
_use_sample_img afl9.vmdk.bz2
-_img_info
+# The sed makes this test pass on machines with little RAM
+# (and also with 32 bit builds)
+_img_info | sed -e 's/Cannot allocate memory/Invalid argument/'
_cleanup_test_img
# success, all done
diff --git a/tests/qemu-iotests/059.out b/tests/qemu-iotests/059.out
index f6dce79..1ac5d56 100644
--- a/tests/qemu-iotests/059.out
+++ b/tests/qemu-iotests/059.out
@@ -2358,5 +2358,5 @@
0x140000000 0x10000 0x50000 TEST_DIR/t-s003.vmdk
=== Testing afl image with a very large capacity ===
-qemu-img: Can't get image size 'TEST_DIR/afl9.IMGFMT': File too large
+qemu-img: Could not open 'TEST_DIR/afl9.IMGFMT': Could not open 'TEST_DIR/afl9.IMGFMT': Invalid argument
*** done
diff --git a/tests/qemu-iotests/060 b/tests/qemu-iotests/060
index 14797dd..6c7407f 100755
--- a/tests/qemu-iotests/060
+++ b/tests/qemu-iotests/060
@@ -335,7 +335,8 @@
# Let's write to it!
$QEMU_IO -c "write 0 64k" "$TEST_IMG" | _filter_qemu_io
-# Can't repair this yet (TODO: We can just deallocate the cluster)
+echo '--- Repairing ---'
+_check_test_img -r all
echo
echo '=== Discarding with an unaligned refblock ==='
diff --git a/tests/qemu-iotests/060.out b/tests/qemu-iotests/060.out
index c4cb7c6..25d5c39 100644
--- a/tests/qemu-iotests/060.out
+++ b/tests/qemu-iotests/060.out
@@ -317,6 +317,15 @@
64 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
qcow2: Marking image as corrupt: Preallocated zero cluster offset 0x2a00 unaligned (guest offset: 0); further corruption events will be suppressed
write failed: Input/output error
+--- Repairing ---
+Repairing offset=2a00: Preallocated zero cluster is not properly aligned; L2 entry corrupted.
+The following inconsistencies were found and repaired:
+
+ 0 leaked clusters
+ 1 corruptions
+
+Double checking the fixed image now...
+No errors were found on the image.
=== Discarding with an unaligned refblock ===
diff --git a/tests/qemu-iotests/067 b/tests/qemu-iotests/067
index 9d561ef..fe259f6 100755
--- a/tests/qemu-iotests/067
+++ b/tests/qemu-iotests/067
@@ -57,7 +57,8 @@
{
do_run_qemu "$@" 2>&1 | _filter_testdir | _filter_qmp | _filter_qemu \
| _filter_actual_image_size \
- | _filter_generated_node_ids | _filter_qmp_events
+ | _filter_generated_node_ids | _filter_qmp_events \
+ | _filter_img_info
}
size=128M
diff --git a/tests/qemu-iotests/067.out b/tests/qemu-iotests/067.out
index 58e83c4..2e71cff 100644
--- a/tests/qemu-iotests/067.out
+++ b/tests/qemu-iotests/067.out
@@ -3,7 +3,7 @@
=== -drive/-device and device_del ===
-Testing: -drive file=TEST_DIR/t.qcow2,format=qcow2,if=none,id=disk -device virtio-blk,drive=disk,id=virtio0
+Testing: -drive file=TEST_DIR/t.IMGFMT,format=IMGFMT,if=none,id=disk -device virtio-blk,drive=disk,id=virtio0
{
QMP_VERSION
}
@@ -23,26 +23,17 @@
"detect_zeroes": "off",
"image": {
"virtual-size": 134217728,
- "filename": "TEST_DIR/t.qcow2",
+ "filename": "TEST_DIR/t.IMGFMT",
"cluster-size": 65536,
- "format": "qcow2",
+ "format": "IMGFMT",
"actual-size": SIZE,
- "format-specific": {
- "type": "qcow2",
- "data": {
- "compat": "1.1",
- "lazy-refcounts": false,
- "refcount-bits": 16,
- "corrupt": false
- }
- },
"dirty-flag": false
},
"iops_wr": 0,
"ro": false,
"node-name": "NODE_NAME",
"backing_file_depth": 0,
- "drv": "qcow2",
+ "drv": "IMGFMT",
"iops": 0,
"bps_wr": 0,
"write_threshold": 0,
@@ -54,7 +45,7 @@
"direct": false,
"writeback": true
},
- "file": "TEST_DIR/t.qcow2",
+ "file": "TEST_DIR/t.IMGFMT",
"encryption_key_missing": false
},
"qdev": "/machine/peripheral/virtio0/virtio-backend",
@@ -81,7 +72,7 @@
=== -drive/device_add and device_del ===
-Testing: -drive file=TEST_DIR/t.qcow2,format=qcow2,if=none,id=disk
+Testing: -drive file=TEST_DIR/t.IMGFMT,format=IMGFMT,if=none,id=disk
{
QMP_VERSION
}
@@ -100,26 +91,17 @@
"detect_zeroes": "off",
"image": {
"virtual-size": 134217728,
- "filename": "TEST_DIR/t.qcow2",
+ "filename": "TEST_DIR/t.IMGFMT",
"cluster-size": 65536,
- "format": "qcow2",
+ "format": "IMGFMT",
"actual-size": SIZE,
- "format-specific": {
- "type": "qcow2",
- "data": {
- "compat": "1.1",
- "lazy-refcounts": false,
- "refcount-bits": 16,
- "corrupt": false
- }
- },
"dirty-flag": false
},
"iops_wr": 0,
"ro": false,
"node-name": "NODE_NAME",
"backing_file_depth": 0,
- "drv": "qcow2",
+ "drv": "IMGFMT",
"iops": 0,
"bps_wr": 0,
"write_threshold": 0,
@@ -131,7 +113,7 @@
"direct": false,
"writeback": true
},
- "file": "TEST_DIR/t.qcow2",
+ "file": "TEST_DIR/t.IMGFMT",
"encryption_key_missing": false
},
"type": "unknown"
@@ -183,26 +165,17 @@
"detect_zeroes": "off",
"image": {
"virtual-size": 134217728,
- "filename": "TEST_DIR/t.qcow2",
+ "filename": "TEST_DIR/t.IMGFMT",
"cluster-size": 65536,
- "format": "qcow2",
+ "format": "IMGFMT",
"actual-size": SIZE,
- "format-specific": {
- "type": "qcow2",
- "data": {
- "compat": "1.1",
- "lazy-refcounts": false,
- "refcount-bits": 16,
- "corrupt": false
- }
- },
"dirty-flag": false
},
"iops_wr": 0,
"ro": false,
"node-name": "NODE_NAME",
"backing_file_depth": 0,
- "drv": "qcow2",
+ "drv": "IMGFMT",
"iops": 0,
"bps_wr": 0,
"write_threshold": 0,
@@ -214,7 +187,7 @@
"direct": false,
"writeback": true
},
- "file": "TEST_DIR/t.qcow2",
+ "file": "TEST_DIR/t.IMGFMT",
"encryption_key_missing": false
},
"type": "unknown"
@@ -263,26 +236,17 @@
"detect_zeroes": "off",
"image": {
"virtual-size": 134217728,
- "filename": "TEST_DIR/t.qcow2",
+ "filename": "TEST_DIR/t.IMGFMT",
"cluster-size": 65536,
- "format": "qcow2",
+ "format": "IMGFMT",
"actual-size": SIZE,
- "format-specific": {
- "type": "qcow2",
- "data": {
- "compat": "1.1",
- "lazy-refcounts": false,
- "refcount-bits": 16,
- "corrupt": false
- }
- },
"dirty-flag": false
},
"iops_wr": 0,
"ro": false,
"node-name": "disk",
"backing_file_depth": 0,
- "drv": "qcow2",
+ "drv": "IMGFMT",
"iops": 0,
"bps_wr": 0,
"write_threshold": 0,
@@ -294,7 +258,7 @@
"direct": false,
"writeback": true
},
- "file": "TEST_DIR/t.qcow2",
+ "file": "TEST_DIR/t.IMGFMT",
"encryption_key_missing": false
},
{
@@ -302,7 +266,7 @@
"detect_zeroes": "off",
"image": {
"virtual-size": 197120,
- "filename": "TEST_DIR/t.qcow2",
+ "filename": "TEST_DIR/t.IMGFMT",
"format": "file",
"actual-size": SIZE,
"dirty-flag": false
@@ -323,7 +287,7 @@
"direct": false,
"writeback": true
},
- "file": "TEST_DIR/t.qcow2",
+ "file": "TEST_DIR/t.IMGFMT",
"encryption_key_missing": false
}
]
@@ -347,26 +311,17 @@
"detect_zeroes": "off",
"image": {
"virtual-size": 134217728,
- "filename": "TEST_DIR/t.qcow2",
+ "filename": "TEST_DIR/t.IMGFMT",
"cluster-size": 65536,
- "format": "qcow2",
+ "format": "IMGFMT",
"actual-size": SIZE,
- "format-specific": {
- "type": "qcow2",
- "data": {
- "compat": "1.1",
- "lazy-refcounts": false,
- "refcount-bits": 16,
- "corrupt": false
- }
- },
"dirty-flag": false
},
"iops_wr": 0,
"ro": false,
"node-name": "disk",
"backing_file_depth": 0,
- "drv": "qcow2",
+ "drv": "IMGFMT",
"iops": 0,
"bps_wr": 0,
"write_threshold": 0,
@@ -378,7 +333,7 @@
"direct": false,
"writeback": true
},
- "file": "TEST_DIR/t.qcow2",
+ "file": "TEST_DIR/t.IMGFMT",
"encryption_key_missing": false
},
{
@@ -386,7 +341,7 @@
"detect_zeroes": "off",
"image": {
"virtual-size": 197120,
- "filename": "TEST_DIR/t.qcow2",
+ "filename": "TEST_DIR/t.IMGFMT",
"format": "file",
"actual-size": SIZE,
"dirty-flag": false
@@ -407,7 +362,7 @@
"direct": false,
"writeback": true
},
- "file": "TEST_DIR/t.qcow2",
+ "file": "TEST_DIR/t.IMGFMT",
"encryption_key_missing": false
}
]
diff --git a/tests/qemu-iotests/080 b/tests/qemu-iotests/080
index 55044c7..1c2bd85 100755
--- a/tests/qemu-iotests/080
+++ b/tests/qemu-iotests/080
@@ -41,8 +41,9 @@
_supported_fmt qcow2
_supported_proto file
_supported_os Linux
-# Internal snapshots are (currently) impossible with refcount_bits=1
-_unsupported_imgopts 'refcount_bits=1[^0-9]'
+# - Internal snapshots are (currently) impossible with refcount_bits=1
+# - This is generally a test for compat=1.1 images
+_unsupported_imgopts 'refcount_bits=1[^0-9]' 'compat=0.10'
header_size=104
diff --git a/tests/qemu-iotests/089 b/tests/qemu-iotests/089
index 9bfe230..0b059ab 100755
--- a/tests/qemu-iotests/089
+++ b/tests/qemu-iotests/089
@@ -119,11 +119,11 @@
# Both options given directly and those given in the filename should be used
$QEMU_IO -c "open -o driver=qcow2 json:{\"file.filename\":\"$TEST_IMG\"}" \
- -c "info" 2>&1 | _filter_testdir | _filter_imgfmt
+ -c "info" 2>&1 | _filter_img_info
# Options given directly should be prioritized over those given in the filename
$QEMU_IO -c "open -o driver=qcow2 json:{\"driver\":\"raw\",\"file.filename\":\"$TEST_IMG\"}" \
- -c "info" 2>&1 | _filter_testdir | _filter_imgfmt
+ -c "info" 2>&1 | _filter_img_info
# success, all done
diff --git a/tests/qemu-iotests/089.out b/tests/qemu-iotests/089.out
index 18f5fdd..0bf5a13 100644
--- a/tests/qemu-iotests/089.out
+++ b/tests/qemu-iotests/089.out
@@ -38,17 +38,7 @@
format name: IMGFMT
cluster size: 64 KiB
vm state offset: 512 MiB
-Format specific information:
- compat: 1.1
- lazy refcounts: false
- refcount bits: 16
- corrupt: false
format name: IMGFMT
cluster size: 64 KiB
vm state offset: 512 MiB
-Format specific information:
- compat: 1.1
- lazy refcounts: false
- refcount bits: 16
- corrupt: false
*** done
diff --git a/tests/qemu-iotests/093 b/tests/qemu-iotests/093
index 5c36a5f..c3404a3 100755
--- a/tests/qemu-iotests/093
+++ b/tests/qemu-iotests/093
@@ -348,9 +348,9 @@
# Now eject cd0 and insert cd1
result = self.vm.qmp("blockdev-open-tray", id='dev0')
self.assert_qmp(result, 'return', {})
- result = self.vm.qmp("x-blockdev-remove-medium", id='dev0')
+ result = self.vm.qmp("blockdev-remove-medium", id='dev0')
self.assert_qmp(result, 'return', {})
- result = self.vm.qmp("x-blockdev-insert-medium", id='dev0', node_name='cd1')
+ result = self.vm.qmp("blockdev-insert-medium", id='dev0', node_name='cd1')
self.assert_qmp(result, 'return', {})
# Check that the I/O limits are still the same
@@ -359,7 +359,7 @@
self.assert_qmp(result, 'return[0]/inserted/bps', 50)
# Eject cd1
- result = self.vm.qmp("x-blockdev-remove-medium", id='dev0')
+ result = self.vm.qmp("blockdev-remove-medium", id='dev0')
self.assert_qmp(result, 'return', {})
# Check that we can't set limits if the device has no medium
diff --git a/tests/qemu-iotests/102 b/tests/qemu-iotests/102
index d7ad8d9..04b3f28 100755
--- a/tests/qemu-iotests/102
+++ b/tests/qemu-iotests/102
@@ -69,7 +69,12 @@
qemu_comm_method=monitor _launch_qemu -drive if=none,file="$TEST_IMG",id=drv0
-$QEMU_IMG resize -f raw --shrink "$TEST_IMG" $((5 * 64 * 1024))
+# Wait for a prompt to appear (so we know qemu has opened the image)
+_send_qemu_cmd '' '(qemu)'
+
+$QEMU_IMG resize --shrink --image-opts \
+ "driver=raw,file.driver=file,file.filename=$TEST_IMG,file.locking=off" \
+ $((5 * 64 * 1024))
_send_qemu_cmd $QEMU_HANDLE 'qemu-io drv0 map' 'allocated' \
| sed -e 's/^(qemu).*qemu-io drv0 map...$/(qemu) qemu-io drv0 map/'
diff --git a/tests/qemu-iotests/102.out b/tests/qemu-iotests/102.out
index ccf172a..4401b08 100644
--- a/tests/qemu-iotests/102.out
+++ b/tests/qemu-iotests/102.out
@@ -14,8 +14,9 @@
Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=65536
wrote 65536/65536 bytes at offset 0
64 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
-Image resized.
QEMU X.Y.Z monitor - type 'help' for more information
+Image resized.
+(qemu)
(qemu) qemu-io drv0 map
64 KiB (0x10000) bytes allocated at offset 0 bytes (0x0)
*** done
diff --git a/tests/qemu-iotests/103 b/tests/qemu-iotests/103
index ecbd8eb..d0cfab8 100755
--- a/tests/qemu-iotests/103
+++ b/tests/qemu-iotests/103
@@ -40,6 +40,8 @@
_supported_fmt qcow2
_supported_proto file nfs
_supported_os Linux
+# Internal snapshots are (currently) impossible with refcount_bits=1
+_unsupported_imgopts 'refcount_bits=1[^0-9]'
IMG_SIZE=64K
diff --git a/tests/qemu-iotests/118 b/tests/qemu-iotests/118
index 8a9e838..a0469b5 100755
--- a/tests/qemu-iotests/118
+++ b/tests/qemu-iotests/118
@@ -28,6 +28,14 @@
old_img = os.path.join(iotests.test_dir, 'test0.img')
new_img = os.path.join(iotests.test_dir, 'test1.img')
+def interface_to_device_name(interface):
+ if interface == 'ide':
+ return 'ide-cd'
+ elif interface == 'floppy':
+ return 'floppy'
+ else:
+ return None
+
class ChangeBaseClass(iotests.QMPTestCase):
has_opened = False
has_closed = False
@@ -63,7 +71,7 @@
class GeneralChangeTestsBaseClass(ChangeBaseClass):
- device_name = None
+ device_name = 'qdev0'
def test_change(self):
result = self.vm.qmp('change', device='drive0', target=new_img,
@@ -79,14 +87,9 @@
self.assert_qmp(result, 'return[0]/inserted/image/filename', new_img)
def test_blockdev_change_medium(self):
- if self.device_name is not None:
- result = self.vm.qmp('blockdev-change-medium',
- id=self.device_name, filename=new_img,
- format=iotests.imgfmt)
- else:
- result = self.vm.qmp('blockdev-change-medium',
- device='drive0', filename=new_img,
- format=iotests.imgfmt)
+ result = self.vm.qmp('blockdev-change-medium',
+ id=self.device_name, filename=new_img,
+ format=iotests.imgfmt)
self.assert_qmp(result, 'return', {})
@@ -99,10 +102,7 @@
self.assert_qmp(result, 'return[0]/inserted/image/filename', new_img)
def test_eject(self):
- if self.device_name is not None:
- result = self.vm.qmp('eject', id=self.device_name, force=True)
- else:
- result = self.vm.qmp('eject', device='drive0', force=True)
+ result = self.vm.qmp('eject', id=self.device_name, force=True)
self.assert_qmp(result, 'return', {})
self.wait_for_open()
@@ -113,10 +113,7 @@
self.assert_qmp_absent(result, 'return[0]/inserted')
def test_tray_eject_change(self):
- if self.device_name is not None:
- result = self.vm.qmp('eject', id=self.device_name, force=True)
- else:
- result = self.vm.qmp('eject', device='drive0', force=True)
+ result = self.vm.qmp('eject', id=self.device_name, force=True)
self.assert_qmp(result, 'return', {})
self.wait_for_open()
@@ -126,12 +123,8 @@
self.assert_qmp(result, 'return[0]/tray_open', True)
self.assert_qmp_absent(result, 'return[0]/inserted')
- if self.device_name is not None:
- result = self.vm.qmp('blockdev-change-medium', id=self.device_name,
- filename=new_img, format=iotests.imgfmt)
- else:
- result = self.vm.qmp('blockdev-change-medium', device='drive0',
- filename=new_img, format=iotests.imgfmt)
+ result = self.vm.qmp('blockdev-change-medium', id=self.device_name,
+ filename=new_img, format=iotests.imgfmt)
self.assert_qmp(result, 'return', {})
self.wait_for_close()
@@ -142,12 +135,8 @@
self.assert_qmp(result, 'return[0]/inserted/image/filename', new_img)
def test_tray_open_close(self):
- if self.device_name is not None:
- result = self.vm.qmp('blockdev-open-tray',
- id=self.device_name, force=True)
- else:
- result = self.vm.qmp('blockdev-open-tray',
- device='drive0', force=True)
+ result = self.vm.qmp('blockdev-open-tray',
+ id=self.device_name, force=True)
self.assert_qmp(result, 'return', {})
self.wait_for_open()
@@ -160,10 +149,7 @@
else:
self.assert_qmp(result, 'return[0]/inserted/image/filename', old_img)
- if self.device_name is not None:
- result = self.vm.qmp('blockdev-close-tray', id=self.device_name)
- else:
- result = self.vm.qmp('blockdev-close-tray', device='drive0')
+ result = self.vm.qmp('blockdev-close-tray', id=self.device_name)
self.assert_qmp(result, 'return', {})
if self.has_real_tray or not self.was_empty:
@@ -178,7 +164,7 @@
self.assert_qmp(result, 'return[0]/inserted/image/filename', old_img)
def test_tray_eject_close(self):
- result = self.vm.qmp('eject', device='drive0', force=True)
+ result = self.vm.qmp('eject', id=self.device_name, force=True)
self.assert_qmp(result, 'return', {})
self.wait_for_open()
@@ -188,10 +174,7 @@
self.assert_qmp(result, 'return[0]/tray_open', True)
self.assert_qmp_absent(result, 'return[0]/inserted')
- if self.device_name is not None:
- result = self.vm.qmp('blockdev-close-tray', id=self.device_name)
- else:
- result = self.vm.qmp('blockdev-close-tray', device='drive0')
+ result = self.vm.qmp('blockdev-close-tray', id=self.device_name)
self.assert_qmp(result, 'return', {})
self.wait_for_close()
@@ -202,7 +185,8 @@
self.assert_qmp_absent(result, 'return[0]/inserted')
def test_tray_open_change(self):
- result = self.vm.qmp('blockdev-open-tray', device='drive0', force=True)
+ result = self.vm.qmp('blockdev-open-tray', id=self.device_name,
+ force=True)
self.assert_qmp(result, 'return', {})
self.wait_for_open()
@@ -215,7 +199,7 @@
else:
self.assert_qmp(result, 'return[0]/inserted/image/filename', old_img)
- result = self.vm.qmp('blockdev-change-medium', device='drive0',
+ result = self.vm.qmp('blockdev-change-medium', id=self.device_name,
filename=new_img,
format=iotests.imgfmt)
self.assert_qmp(result, 'return', {})
@@ -235,12 +219,8 @@
'driver': 'file'})
self.assert_qmp(result, 'return', {})
- if self.device_name is not None:
- result = self.vm.qmp('blockdev-open-tray',
- id=self.device_name, force=True)
- else:
- result = self.vm.qmp('blockdev-open-tray',
- device='drive0', force=True)
+ result = self.vm.qmp('blockdev-open-tray',
+ id=self.device_name, force=True)
self.assert_qmp(result, 'return', {})
self.wait_for_open()
@@ -253,11 +233,8 @@
else:
self.assert_qmp(result, 'return[0]/inserted/image/filename', old_img)
- if self.device_name is not None:
- result = self.vm.qmp('x-blockdev-remove-medium',
- id=self.device_name)
- else:
- result = self.vm.qmp('x-blockdev-remove-medium', device='drive0')
+ result = self.vm.qmp('blockdev-remove-medium',
+ id=self.device_name)
self.assert_qmp(result, 'return', {})
result = self.vm.qmp('query-block')
@@ -265,12 +242,8 @@
self.assert_qmp(result, 'return[0]/tray_open', True)
self.assert_qmp_absent(result, 'return[0]/inserted')
- if self.device_name is not None:
- result = self.vm.qmp('x-blockdev-insert-medium',
- id=self.device_name, node_name='new')
- else:
- result = self.vm.qmp('x-blockdev-insert-medium',
- device='drive0', node_name='new')
+ result = self.vm.qmp('blockdev-insert-medium',
+ id=self.device_name, node_name='new')
self.assert_qmp(result, 'return', {})
result = self.vm.qmp('query-block')
@@ -278,10 +251,7 @@
self.assert_qmp(result, 'return[0]/tray_open', True)
self.assert_qmp(result, 'return[0]/inserted/image/filename', new_img)
- if self.device_name is not None:
- result = self.vm.qmp('blockdev-close-tray', id=self.device_name)
- else:
- result = self.vm.qmp('blockdev-close-tray', device='drive0')
+ result = self.vm.qmp('blockdev-close-tray', id=self.device_name)
self.assert_qmp(result, 'return', {})
self.wait_for_close()
@@ -292,7 +262,7 @@
self.assert_qmp(result, 'return[0]/inserted/image/filename', new_img)
def test_close_on_closed(self):
- result = self.vm.qmp('blockdev-close-tray', device='drive0')
+ result = self.vm.qmp('blockdev-close-tray', id=self.device_name)
# Should be a no-op
self.assert_qmp(result, 'return', {})
self.assertEquals(self.vm.get_qmp_events(wait=False), [])
@@ -301,7 +271,7 @@
if not self.has_real_tray:
return
- result = self.vm.qmp('x-blockdev-remove-medium', device='drive0')
+ result = self.vm.qmp('blockdev-remove-medium', id=self.device_name)
self.assert_qmp(result, 'error/class', 'GenericError')
def test_insert_on_closed(self):
@@ -315,7 +285,7 @@
'driver': 'file'})
self.assert_qmp(result, 'return', {})
- result = self.vm.qmp('x-blockdev-insert-medium', device='drive0',
+ result = self.vm.qmp('blockdev-insert-medium', id=self.device_name,
node_name='new')
self.assert_qmp(result, 'error/class', 'GenericError')
@@ -326,12 +296,10 @@
qemu_img('create', '-f', iotests.imgfmt, old_img, '1440k')
qemu_img('create', '-f', iotests.imgfmt, new_img, '1440k')
self.vm = iotests.VM()
- if interface == 'ide':
- self.device_name = 'qdev0'
- self.vm.add_drive(old_img, 'media=%s' % media, 'none')
- self.vm.add_device('ide-cd,drive=drive0,id=%s' % self.device_name)
- else:
- self.vm.add_drive(old_img, 'media=%s' % media, interface)
+ self.vm.add_drive(old_img, 'media=%s' % media, 'none')
+ self.vm.add_device('%s,drive=drive0,id=%s' %
+ (interface_to_device_name(interface),
+ self.device_name))
self.vm.launch()
def tearDown(self):
@@ -347,12 +315,12 @@
'driver': 'file'})
self.assert_qmp(result, 'return', {})
- result = self.vm.qmp('blockdev-open-tray', device='drive0')
+ result = self.vm.qmp('blockdev-open-tray', id=self.device_name)
self.assert_qmp(result, 'return', {})
self.wait_for_open()
- result = self.vm.qmp('x-blockdev-insert-medium', device='drive0',
+ result = self.vm.qmp('blockdev-insert-medium', id=self.device_name,
node_name='new')
self.assert_qmp(result, 'error/class', 'GenericError')
@@ -361,7 +329,10 @@
def setUp(self, media, interface):
qemu_img('create', '-f', iotests.imgfmt, new_img, '1440k')
- self.vm = iotests.VM().add_drive(None, 'media=%s' % media, interface)
+ self.vm = iotests.VM().add_drive(None, 'media=%s' % media, 'none')
+ self.vm.add_device('%s,drive=drive0,id=%s' %
+ (interface_to_device_name(interface),
+ self.device_name))
self.vm.launch()
def tearDown(self):
@@ -369,12 +340,12 @@
os.remove(new_img)
def test_remove_on_empty(self):
- result = self.vm.qmp('blockdev-open-tray', device='drive0')
+ result = self.vm.qmp('blockdev-open-tray', id=self.device_name)
self.assert_qmp(result, 'return', {})
self.wait_for_open()
- result = self.vm.qmp('x-blockdev-remove-medium', device='drive0')
+ result = self.vm.qmp('blockdev-remove-medium', id=self.device_name)
# Should be a no-op
self.assert_qmp(result, 'return', {})
@@ -410,6 +381,8 @@
self.has_opened = True
class TestChangeReadOnly(ChangeBaseClass):
+ device_name = 'qdev0'
+
def setUp(self):
qemu_img('create', '-f', iotests.imgfmt, old_img, '1440k')
qemu_img('create', '-f', iotests.imgfmt, new_img, '1440k')
@@ -425,14 +398,15 @@
def test_ro_ro_retain(self):
os.chmod(old_img, 0444)
os.chmod(new_img, 0444)
- self.vm.add_drive(old_img, 'media=disk,read-only=on', 'floppy')
+ self.vm.add_drive(old_img, 'media=disk,read-only=on', 'none')
+ self.vm.add_device('floppy,drive=drive0,id=%s' % self.device_name)
self.vm.launch()
result = self.vm.qmp('query-block')
self.assert_qmp(result, 'return[0]/inserted/ro', True)
self.assert_qmp(result, 'return[0]/inserted/image/filename', old_img)
- result = self.vm.qmp('blockdev-change-medium', device='drive0',
+ result = self.vm.qmp('blockdev-change-medium', id=self.device_name,
filename=new_img,
format=iotests.imgfmt,
read_only_mode='retain')
@@ -444,14 +418,15 @@
def test_ro_rw_retain(self):
os.chmod(old_img, 0444)
- self.vm.add_drive(old_img, 'media=disk,read-only=on', 'floppy')
+ self.vm.add_drive(old_img, 'media=disk,read-only=on', 'none')
+ self.vm.add_device('floppy,drive=drive0,id=%s' % self.device_name)
self.vm.launch()
result = self.vm.qmp('query-block')
self.assert_qmp(result, 'return[0]/inserted/ro', True)
self.assert_qmp(result, 'return[0]/inserted/image/filename', old_img)
- result = self.vm.qmp('blockdev-change-medium', device='drive0',
+ result = self.vm.qmp('blockdev-change-medium', id=self.device_name,
filename=new_img,
format=iotests.imgfmt,
read_only_mode='retain')
@@ -463,14 +438,15 @@
def test_rw_ro_retain(self):
os.chmod(new_img, 0444)
- self.vm.add_drive(old_img, 'media=disk', 'floppy')
+ self.vm.add_drive(old_img, 'media=disk', 'none')
+ self.vm.add_device('floppy,drive=drive0,id=%s' % self.device_name)
self.vm.launch()
result = self.vm.qmp('query-block')
self.assert_qmp(result, 'return[0]/inserted/ro', False)
self.assert_qmp(result, 'return[0]/inserted/image/filename', old_img)
- result = self.vm.qmp('blockdev-change-medium', device='drive0',
+ result = self.vm.qmp('blockdev-change-medium', id=self.device_name,
filename=new_img,
format=iotests.imgfmt,
read_only_mode='retain')
@@ -484,7 +460,8 @@
def test_ro_rw(self):
os.chmod(old_img, 0444)
- self.vm.add_drive(old_img, 'media=disk,read-only=on', 'floppy')
+ self.vm.add_drive(old_img, 'media=disk,read-only=on', 'none')
+ self.vm.add_device('floppy,drive=drive0,id=%s' % self.device_name)
self.vm.launch()
result = self.vm.qmp('query-block')
@@ -492,7 +469,7 @@
self.assert_qmp(result, 'return[0]/inserted/image/filename', old_img)
result = self.vm.qmp('blockdev-change-medium',
- device='drive0',
+ id=self.device_name,
filename=new_img,
format=iotests.imgfmt,
read_only_mode='read-write')
@@ -504,7 +481,8 @@
def test_rw_ro(self):
os.chmod(new_img, 0444)
- self.vm.add_drive(old_img, 'media=disk', 'floppy')
+ self.vm.add_drive(old_img, 'media=disk', 'none')
+ self.vm.add_device('floppy,drive=drive0,id=%s' % self.device_name)
self.vm.launch()
result = self.vm.qmp('query-block')
@@ -512,7 +490,7 @@
self.assert_qmp(result, 'return[0]/inserted/image/filename', old_img)
result = self.vm.qmp('blockdev-change-medium',
- device='drive0',
+ id=self.device_name,
filename=new_img,
format=iotests.imgfmt,
read_only_mode='read-only')
@@ -523,7 +501,8 @@
self.assert_qmp(result, 'return[0]/inserted/image/filename', new_img)
def test_make_rw_ro(self):
- self.vm.add_drive(old_img, 'media=disk', 'floppy')
+ self.vm.add_drive(old_img, 'media=disk', 'none')
+ self.vm.add_device('floppy,drive=drive0,id=%s' % self.device_name)
self.vm.launch()
result = self.vm.qmp('query-block')
@@ -531,7 +510,7 @@
self.assert_qmp(result, 'return[0]/inserted/image/filename', old_img)
result = self.vm.qmp('blockdev-change-medium',
- device='drive0',
+ id=self.device_name,
filename=new_img,
format=iotests.imgfmt,
read_only_mode='read-only')
@@ -543,7 +522,8 @@
def test_make_ro_rw(self):
os.chmod(new_img, 0444)
- self.vm.add_drive(old_img, 'media=disk', 'floppy')
+ self.vm.add_drive(old_img, 'media=disk', 'none')
+ self.vm.add_device('floppy,drive=drive0,id=%s' % self.device_name)
self.vm.launch()
result = self.vm.qmp('query-block')
@@ -551,7 +531,7 @@
self.assert_qmp(result, 'return[0]/inserted/image/filename', old_img)
result = self.vm.qmp('blockdev-change-medium',
- device='drive0',
+ id=self.device_name,
filename=new_img,
format=iotests.imgfmt,
read_only_mode='read-write')
@@ -563,14 +543,15 @@
def test_make_rw_ro_by_retain(self):
os.chmod(old_img, 0444)
- self.vm.add_drive(old_img, 'media=disk,read-only=on', 'floppy')
+ self.vm.add_drive(old_img, 'media=disk,read-only=on', 'none')
+ self.vm.add_device('floppy,drive=drive0,id=%s' % self.device_name)
self.vm.launch()
result = self.vm.qmp('query-block')
self.assert_qmp(result, 'return[0]/inserted/ro', True)
self.assert_qmp(result, 'return[0]/inserted/image/filename', old_img)
- result = self.vm.qmp('blockdev-change-medium', device='drive0',
+ result = self.vm.qmp('blockdev-change-medium', id=self.device_name,
filename=new_img,
format=iotests.imgfmt,
read_only_mode='retain')
@@ -582,14 +563,15 @@
def test_make_ro_rw_by_retain(self):
os.chmod(new_img, 0444)
- self.vm.add_drive(old_img, 'media=disk', 'floppy')
+ self.vm.add_drive(old_img, 'media=disk', 'none')
+ self.vm.add_device('floppy,drive=drive0,id=%s' % self.device_name)
self.vm.launch()
result = self.vm.qmp('query-block')
self.assert_qmp(result, 'return[0]/inserted/ro', False)
self.assert_qmp(result, 'return[0]/inserted/image/filename', old_img)
- result = self.vm.qmp('blockdev-change-medium', device='drive0',
+ result = self.vm.qmp('blockdev-change-medium', id=self.device_name,
filename=new_img,
format=iotests.imgfmt,
read_only_mode='retain')
@@ -601,7 +583,8 @@
def test_rw_ro_cycle(self):
os.chmod(new_img, 0444)
- self.vm.add_drive(old_img, 'media=disk', 'floppy')
+ self.vm.add_drive(old_img, 'media=disk', 'none')
+ self.vm.add_device('floppy,drive=drive0,id=%s' % self.device_name)
self.vm.launch()
result = self.vm.qmp('query-block')
@@ -620,13 +603,13 @@
self.assert_qmp(result, 'return[0]/inserted/ro', False)
self.assert_qmp(result, 'return[0]/inserted/image/filename', old_img)
- result = self.vm.qmp('x-blockdev-remove-medium', device='drive0')
+ result = self.vm.qmp('blockdev-remove-medium', id=self.device_name)
self.assert_qmp(result, 'return', {})
result = self.vm.qmp('query-block')
self.assert_qmp_absent(result, 'return[0]/inserted')
- result = self.vm.qmp('x-blockdev-insert-medium', device='drive0',
+ result = self.vm.qmp('blockdev-insert-medium', id=self.device_name,
node_name='new')
self.assert_qmp(result, 'return', {})
@@ -644,11 +627,14 @@
class TestBlockJobsAfterCycle(ChangeBaseClass):
+ device_name = 'qdev0'
+
def setUp(self):
- qemu_img('create', '-f', iotests.imgfmt, old_img, '1M')
+ qemu_img('create', '-f', iotests.imgfmt, old_img, '1440K')
self.vm = iotests.VM()
self.vm.add_drive_raw("id=drive0,driver=null-co,if=none")
+ self.vm.add_device('floppy,drive=drive0,id=%s' % self.device_name)
self.vm.launch()
result = self.vm.qmp('query-block')
@@ -656,7 +642,7 @@
# For device-less BBs, calling blockdev-open-tray or blockdev-close-tray
# is not necessary
- result = self.vm.qmp('x-blockdev-remove-medium', device='drive0')
+ result = self.vm.qmp('blockdev-remove-medium', id=self.device_name)
self.assert_qmp(result, 'return', {})
result = self.vm.qmp('query-block')
@@ -669,7 +655,7 @@
'driver': 'file'})
self.assert_qmp(result, 'return', {})
- result = self.vm.qmp('x-blockdev-insert-medium', device='drive0',
+ result = self.vm.qmp('blockdev-insert-medium', id=self.device_name,
node_name='node0')
self.assert_qmp(result, 'return', {})
diff --git a/tests/qemu-iotests/130 b/tests/qemu-iotests/130
index e7e43de..2c4b94d 100755
--- a/tests/qemu-iotests/130
+++ b/tests/qemu-iotests/130
@@ -45,6 +45,8 @@
_supported_proto generic
_unsupported_proto vxhs
_supported_os Linux
+# We are going to use lazy-refcounts
+_unsupported_imgopts 'compat=0.10'
qemu_comm_method="monitor"
diff --git a/tests/qemu-iotests/137 b/tests/qemu-iotests/137
index eb91e51..5a01250 100755
--- a/tests/qemu-iotests/137
+++ b/tests/qemu-iotests/137
@@ -41,6 +41,8 @@
_supported_fmt qcow2
_supported_proto file
_supported_os Linux
+# We are going to use lazy-refcounts
+_unsupported_imgopts 'compat=0.10'
_make_test_img 64M
diff --git a/tests/qemu-iotests/139 b/tests/qemu-iotests/139
index f8f0280..cc7fe33 100644
--- a/tests/qemu-iotests/139
+++ b/tests/qemu-iotests/139
@@ -133,7 +133,7 @@
# Insert a BlockDriverState
def insertDrive(self, device, node):
self.checkBlockDriverState(node)
- result = self.vm.qmp('x-blockdev-insert-medium',
+ result = self.vm.qmp('blockdev-insert-medium',
id = device, node_name = node)
self.assert_qmp(result, 'return', {})
self.checkBlockDriverState(node)
diff --git a/tests/qemu-iotests/155 b/tests/qemu-iotests/155
index 0b86ea4..fc9fa97 100755
--- a/tests/qemu-iotests/155
+++ b/tests/qemu-iotests/155
@@ -51,36 +51,30 @@
target_real_backing = None
def setUp(self):
- qemu_img('create', '-f', iotests.imgfmt, back0_img, '1M')
+ qemu_img('create', '-f', iotests.imgfmt, back0_img, '1440K')
qemu_img('create', '-f', iotests.imgfmt, '-b', back0_img, back1_img)
qemu_img('create', '-f', iotests.imgfmt, '-b', back1_img, back2_img)
qemu_img('create', '-f', iotests.imgfmt, '-b', back2_img, source_img)
self.vm = iotests.VM()
- self.vm.add_drive(None, '', 'none')
- self.vm.launch()
-
# Add the BDS via blockdev-add so it stays around after the mirror block
# job has been completed
- result = self.vm.qmp('blockdev-add',
- node_name='source',
- driver=iotests.imgfmt,
- file={'driver': 'file',
- 'filename': source_img})
- self.assert_qmp(result, 'return', {})
-
- result = self.vm.qmp('x-blockdev-insert-medium',
- device='drive0', node_name='source')
- self.assert_qmp(result, 'return', {})
+ blockdev = {'node-name': 'source',
+ 'driver': iotests.imgfmt,
+ 'file': {'driver': 'file',
+ 'filename': source_img}}
+ self.vm.add_blockdev(self.qmp_to_opts(blockdev))
+ self.vm.add_device('floppy,id=qdev0,drive=source')
+ self.vm.launch()
self.assertIntactSourceBackingChain()
if self.existing:
if self.target_backing:
qemu_img('create', '-f', iotests.imgfmt,
- '-b', self.target_backing, target_img, '1M')
+ '-b', self.target_backing, target_img, '1440K')
else:
- qemu_img('create', '-f', iotests.imgfmt, target_img, '1M')
+ qemu_img('create', '-f', iotests.imgfmt, target_img, '1440K')
if self.cmd == 'blockdev-mirror':
options = { 'node-name': 'target',
@@ -104,11 +98,11 @@
except OSError:
pass
- def findBlockNode(self, node_name, id=None):
- if id:
+ def findBlockNode(self, node_name, qdev=None):
+ if qdev:
result = self.vm.qmp('query-block')
for device in result['return']:
- if device['device'] == id:
+ if device['qdev'] == qdev:
if node_name:
self.assert_qmp(device, 'inserted/node-name', node_name)
return device['inserted']
@@ -118,7 +112,7 @@
if node['node-name'] == node_name:
return node
- self.fail('Cannot find node %s/%s' % (id, node_name))
+ self.fail('Cannot find node %s/%s' % (qdev, node_name))
def assertIntactSourceBackingChain(self):
node = self.findBlockNode('source')
@@ -155,22 +149,23 @@
class MirrorBaseClass(BaseClass):
def runMirror(self, sync):
if self.cmd == 'blockdev-mirror':
- result = self.vm.qmp(self.cmd, device='drive0', sync=sync,
- target='target')
+ result = self.vm.qmp(self.cmd, job_id='mirror-job', device='source',
+ sync=sync, target='target')
else:
if self.existing:
mode = 'existing'
else:
mode = 'absolute-paths'
- result = self.vm.qmp(self.cmd, device='drive0', sync=sync,
- target=target_img, format=iotests.imgfmt,
- mode=mode, node_name='target')
+ result = self.vm.qmp(self.cmd, job_id='mirror-job', device='source',
+ sync=sync, target=target_img,
+ format=iotests.imgfmt, mode=mode,
+ node_name='target')
self.assert_qmp(result, 'return', {})
self.vm.event_wait('BLOCK_JOB_READY')
- result = self.vm.qmp('block-job-complete', device='drive0')
+ result = self.vm.qmp('block-job-complete', device='mirror-job')
self.assert_qmp(result, 'return', {})
self.vm.event_wait('BLOCK_JOB_COMPLETED')
@@ -178,21 +173,21 @@
def testFull(self):
self.runMirror('full')
- node = self.findBlockNode('target', 'drive0')
+ node = self.findBlockNode('target', 'qdev0')
self.assertCorrectBackingImage(node, None)
self.assertIntactSourceBackingChain()
def testTop(self):
self.runMirror('top')
- node = self.findBlockNode('target', 'drive0')
+ node = self.findBlockNode('target', 'qdev0')
self.assertCorrectBackingImage(node, back2_img)
self.assertIntactSourceBackingChain()
def testNone(self):
self.runMirror('none')
- node = self.findBlockNode('target', 'drive0')
+ node = self.findBlockNode('target', 'qdev0')
self.assertCorrectBackingImage(node, source_img)
self.assertIntactSourceBackingChain()
@@ -233,17 +228,18 @@
existing = False
def testCommit(self):
- result = self.vm.qmp('block-commit', device='drive0', base=back1_img)
+ result = self.vm.qmp('block-commit', job_id='commit-job',
+ device='source', base=back1_img)
self.assert_qmp(result, 'return', {})
self.vm.event_wait('BLOCK_JOB_READY')
- result = self.vm.qmp('block-job-complete', device='drive0')
+ result = self.vm.qmp('block-job-complete', device='commit-job')
self.assert_qmp(result, 'return', {})
self.vm.event_wait('BLOCK_JOB_COMPLETED')
- node = self.findBlockNode(None, 'drive0')
+ node = self.findBlockNode(None, 'qdev0')
self.assert_qmp(node, 'image' + '/backing-image' * 0 + '/filename',
back1_img)
self.assert_qmp(node, 'image' + '/backing-image' * 1 + '/filename',
diff --git a/tests/qemu-iotests/176 b/tests/qemu-iotests/176
index b8dc17c..d38b3ae 100755
--- a/tests/qemu-iotests/176
+++ b/tests/qemu-iotests/176
@@ -48,6 +48,8 @@
_supported_fmt qcow2
_supported_proto file
_supported_os Linux
+# Persistent dirty bitmaps require compat=1.1
+_unsupported_imgopts 'compat=0.10'
function run_qemu()
{
diff --git a/tests/qemu-iotests/177 b/tests/qemu-iotests/177
index 2899097..396986d 100755
--- a/tests/qemu-iotests/177
+++ b/tests/qemu-iotests/177
@@ -2,7 +2,7 @@
#
# Test corner cases with unusual block geometries
#
-# Copyright (C) 2016-2017 Red Hat, Inc.
+# Copyright (C) 2016-2018 Red Hat, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
@@ -37,13 +37,15 @@
. ./common.rc
. ./common.filter
+# This test is runnable under compat=0.10; see test 204 for additional
+# tests specific to compat=1.1.
+
_supported_fmt qcow2
_supported_proto file
CLUSTER_SIZE=1M
size=128M
options=driver=blkdebug,image.driver=qcow2
-nested_opts=image.file.driver=file,image.file.filename=$TEST_IMG
echo
echo "== setting up files =="
@@ -51,7 +53,7 @@
TEST_IMG="$TEST_IMG.base" _make_test_img $size
$QEMU_IO -c "write -P 11 0 $size" "$TEST_IMG.base" | _filter_qemu_io
_make_test_img -b "$TEST_IMG.base"
-$QEMU_IO -c "write -P 22 0 110M" "$TEST_IMG" | _filter_qemu_io
+$QEMU_IO -c "write -P 22 0 $size" "$TEST_IMG" | _filter_qemu_io
# Limited to 64k max-transfer
echo
@@ -82,13 +84,6 @@
-c "discard 80000001 30M" | _filter_qemu_io
echo
-echo "== block status smaller than alignment =="
-limits=align=4k
-$QEMU_IO -c "open -o $options,$limits blkdebug::$TEST_IMG" \
- -c "alloc 1 1" -c "alloc 0x6dffff0 1000" -c "alloc 127m 5P" \
- -c map | _filter_qemu_io
-
-echo
echo "== verify image content =="
function verify_io()
@@ -110,13 +105,10 @@
echo read -P 0 32M 32M
echo read -P 22 64M 13M
echo read -P $discarded 77M 29M
- echo read -P 22 106M 4M
- echo read -P 11 110M 18M
+ echo read -P 22 106M 22M
}
verify_io | $QEMU_IO -r "$TEST_IMG" | _filter_qemu_io
-$QEMU_IMG map --image-opts "$options,$nested_opts,align=4k" \
- | _filter_qemu_img_map
_check_test_img
diff --git a/tests/qemu-iotests/177.out b/tests/qemu-iotests/177.out
index f788b55..e887542 100644
--- a/tests/qemu-iotests/177.out
+++ b/tests/qemu-iotests/177.out
@@ -5,8 +5,8 @@
wrote 134217728/134217728 bytes at offset 0
128 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=134217728 backing_file=TEST_DIR/t.IMGFMT.base
-wrote 115343360/115343360 bytes at offset 0
-110 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
+wrote 134217728/134217728 bytes at offset 0
+128 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
== constrained alignment and max-transfer ==
wrote 131072/131072 bytes at offset 1000
@@ -26,13 +26,6 @@
discard 31457280/31457280 bytes at offset 80000001
30 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
-== block status smaller than alignment ==
-1/1 bytes allocated at offset 1 bytes
-16/1000 bytes allocated at offset 110 MiB
-0/1048576 bytes allocated at offset 127 MiB
-110 MiB (0x6e00000) bytes allocated at offset 0 bytes (0x0)
-18 MiB (0x1200000) bytes not allocated at offset 110 MiB (0x6e00000)
-
== verify image content ==
read 1000/1000 bytes at offset 0
1000 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
@@ -50,14 +43,7 @@
13 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
read 30408704/30408704 bytes at offset 80740352
29 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
-read 4194304/4194304 bytes at offset 111149056
-4 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
-read 18874368/18874368 bytes at offset 115343360
-18 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
-Offset Length File
-0 0x800000 TEST_DIR/t.IMGFMT
-0x900000 0x2400000 TEST_DIR/t.IMGFMT
-0x3c00000 0x1100000 TEST_DIR/t.IMGFMT
-0x6a00000 0x400000 TEST_DIR/t.IMGFMT
+read 23068672/23068672 bytes at offset 111149056
+22 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
No errors were found on the image.
*** done
diff --git a/tests/qemu-iotests/184 b/tests/qemu-iotests/184
index ee96c99..2b68284 100755
--- a/tests/qemu-iotests/184
+++ b/tests/qemu-iotests/184
@@ -27,18 +27,12 @@
here=`pwd`
status=1 # failure is the default!
-_cleanup()
-{
- _cleanup_test_img
-}
-trap "_cleanup; exit \$status" 0 1 2 3 15
+trap "exit \$status" 0 1 2 3 15
# get standard environment, filters and checks
. ./common.rc
. ./common.filter
-_supported_fmt qcow2
-_supported_proto file
_supported_os Linux
function do_run_qemu()
@@ -55,7 +49,6 @@
| _filter_actual_image_size
}
-_make_test_img 64M
test_throttle=$($QEMU_IMG --help|grep throttle)
[ "$test_throttle" = "" ] && _supported_fmt throttle
@@ -66,12 +59,8 @@
{ "execute": "qmp_capabilities" }
{ "execute": "blockdev-add",
"arguments": {
- "driver": "$IMGFMT",
- "node-name": "disk0",
- "file": {
- "driver": "file",
- "filename": "$TEST_IMG"
- }
+ "driver": "null-co",
+ "node-name": "disk0"
}
}
{ "execute": "object-add",
@@ -181,12 +170,8 @@
{ "execute": "qmp_capabilities" }
{ "execute": "blockdev-add",
"arguments": {
- "driver": "$IMGFMT",
- "node-name": "disk0",
- "file": {
- "driver": "file",
- "filename": "$TEST_IMG"
- }
+ "driver": "null-co",
+ "node-name": "disk0"
}
}
{ "execute": "blockdev-add",
diff --git a/tests/qemu-iotests/184.out b/tests/qemu-iotests/184.out
index 4dc7984..672650c 100644
--- a/tests/qemu-iotests/184.out
+++ b/tests/qemu-iotests/184.out
@@ -1,5 +1,4 @@
QA output created by 184
-Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=67108864
== checking interface ==
Testing:
@@ -28,12 +27,9 @@
"iops_rd": 0,
"detect_zeroes": "off",
"image": {
- "virtual-size": 67108864,
- "filename": "json:{\"throttle-group\": \"group0\", \"driver\": \"throttle\", \"file\": {\"driver\": \"qcow2\", \"file\": {\"driver\": \"file\", \"filename\": \"TEST_DIR/t.qcow2\"}}}",
- "cluster-size": 65536,
- "format": "throttle",
- "actual-size": SIZE,
- "dirty-flag": false
+ "virtual-size": 1073741824,
+ "filename": "json:{\"throttle-group\": \"group0\", \"driver\": \"throttle\", \"file\": {\"driver\": \"null-co\"}}",
+ "format": "throttle"
},
"iops_wr": 0,
"ro": false,
@@ -51,34 +47,22 @@
"direct": false,
"writeback": true
},
- "file": "json:{\"throttle-group\": \"group0\", \"driver\": \"throttle\", \"file\": {\"driver\": \"qcow2\", \"file\": {\"driver\": \"file\", \"filename\": \"TEST_DIR/t.qcow2\"}}}",
+ "file": "json:{\"throttle-group\": \"group0\", \"driver\": \"throttle\", \"file\": {\"driver\": \"null-co\"}}",
"encryption_key_missing": false
},
{
"iops_rd": 0,
"detect_zeroes": "off",
"image": {
- "virtual-size": 67108864,
- "filename": "TEST_DIR/t.qcow2",
- "cluster-size": 65536,
- "format": "qcow2",
- "actual-size": SIZE,
- "format-specific": {
- "type": "qcow2",
- "data": {
- "compat": "1.1",
- "lazy-refcounts": false,
- "refcount-bits": 16,
- "corrupt": false
- }
- },
- "dirty-flag": false
+ "virtual-size": 1073741824,
+ "filename": "null-co://",
+ "format": "null-co"
},
"iops_wr": 0,
"ro": false,
"node-name": "disk0",
"backing_file_depth": 0,
- "drv": "qcow2",
+ "drv": "null-co",
"iops": 0,
"bps_wr": 0,
"write_threshold": 0,
@@ -90,36 +74,7 @@
"direct": false,
"writeback": true
},
- "file": "TEST_DIR/t.qcow2",
- "encryption_key_missing": false
- },
- {
- "iops_rd": 0,
- "detect_zeroes": "off",
- "image": {
- "virtual-size": 197120,
- "filename": "TEST_DIR/t.qcow2",
- "format": "file",
- "actual-size": SIZE,
- "dirty-flag": false
- },
- "iops_wr": 0,
- "ro": false,
- "node-name": "NODE_NAME",
- "backing_file_depth": 0,
- "drv": "file",
- "iops": 0,
- "bps_wr": 0,
- "write_threshold": 0,
- "encrypted": false,
- "bps": 0,
- "bps_rd": 0,
- "cache": {
- "no-flush": false,
- "direct": false,
- "writeback": true
- },
- "file": "TEST_DIR/t.qcow2",
+ "file": "null-co://",
"encryption_key_missing": false
}
]
diff --git a/tests/qemu-iotests/191 b/tests/qemu-iotests/191
index ad785e1..dfad655 100755
--- a/tests/qemu-iotests/191
+++ b/tests/qemu-iotests/191
@@ -45,7 +45,6 @@
. ./common.qemu
_supported_fmt qcow2
-_unsupported_imgopts compat=0.10
_supported_proto file
_supported_os Linux
@@ -92,7 +91,7 @@
echo
_send_qemu_cmd $h "{ 'execute': 'query-named-block-nodes' }" "^}" |
- _filter_generated_node_ids | _filter_actual_image_size
+ _filter_generated_node_ids | _filter_actual_image_size | _filter_img_info
_send_qemu_cmd $h "{ 'execute': 'quit' }" "^}"
wait=1 _cleanup_qemu
@@ -140,7 +139,7 @@
echo
_send_qemu_cmd $h "{ 'execute': 'query-named-block-nodes' }" "^}" |
- _filter_generated_node_ids | _filter_actual_image_size
+ _filter_generated_node_ids | _filter_actual_image_size | _filter_img_info
_send_qemu_cmd $h "{ 'execute': 'quit' }" "^}"
wait=1 _cleanup_qemu
diff --git a/tests/qemu-iotests/191.out b/tests/qemu-iotests/191.out
index 73c0ed4..190c5f0 100644
--- a/tests/qemu-iotests/191.out
+++ b/tests/qemu-iotests/191.out
@@ -44,49 +44,31 @@
"image": {
"backing-image": {
"virtual-size": 67108864,
- "filename": "TEST_DIR/t.qcow2.base",
+ "filename": "TEST_DIR/t.IMGFMT.base",
"cluster-size": 65536,
- "format": "qcow2",
+ "format": "IMGFMT",
"actual-size": SIZE,
- "format-specific": {
- "type": "qcow2",
- "data": {
- "compat": "1.1",
- "lazy-refcounts": false,
- "refcount-bits": 16,
- "corrupt": false
- }
- },
"dirty-flag": false
},
- "backing-filename-format": "qcow2",
+ "backing-filename-format": "IMGFMT",
"virtual-size": 67108864,
- "filename": "TEST_DIR/t.qcow2.ovl2",
+ "filename": "TEST_DIR/t.IMGFMT.ovl2",
"cluster-size": 65536,
- "format": "qcow2",
+ "format": "IMGFMT",
"actual-size": SIZE,
- "format-specific": {
- "type": "qcow2",
- "data": {
- "compat": "1.1",
- "lazy-refcounts": false,
- "refcount-bits": 16,
- "corrupt": false
- }
- },
- "full-backing-filename": "TEST_DIR/t.qcow2.base",
- "backing-filename": "TEST_DIR/t.qcow2.base",
+ "full-backing-filename": "TEST_DIR/t.IMGFMT.base",
+ "backing-filename": "TEST_DIR/t.IMGFMT.base",
"dirty-flag": false
},
"iops_wr": 0,
"ro": false,
"node-name": "top2",
"backing_file_depth": 1,
- "drv": "qcow2",
+ "drv": "IMGFMT",
"iops": 0,
"bps_wr": 0,
"write_threshold": 0,
- "backing_file": "TEST_DIR/t.qcow2.base",
+ "backing_file": "TEST_DIR/t.IMGFMT.base",
"encrypted": false,
"bps": 0,
"bps_rd": 0,
@@ -95,7 +77,7 @@
"direct": false,
"writeback": true
},
- "file": "TEST_DIR/t.qcow2.ovl2",
+ "file": "TEST_DIR/t.IMGFMT.ovl2",
"encryption_key_missing": false
},
{
@@ -103,7 +85,7 @@
"detect_zeroes": "off",
"image": {
"virtual-size": 197120,
- "filename": "TEST_DIR/t.qcow2.ovl2",
+ "filename": "TEST_DIR/t.IMGFMT.ovl2",
"format": "file",
"actual-size": SIZE,
"dirty-flag": false
@@ -124,7 +106,7 @@
"direct": false,
"writeback": true
},
- "file": "TEST_DIR/t.qcow2.ovl2",
+ "file": "TEST_DIR/t.IMGFMT.ovl2",
"encryption_key_missing": false
},
{
@@ -133,49 +115,31 @@
"image": {
"backing-image": {
"virtual-size": 67108864,
- "filename": "TEST_DIR/t.qcow2.base",
+ "filename": "TEST_DIR/t.IMGFMT.base",
"cluster-size": 65536,
- "format": "qcow2",
+ "format": "IMGFMT",
"actual-size": SIZE,
- "format-specific": {
- "type": "qcow2",
- "data": {
- "compat": "1.1",
- "lazy-refcounts": false,
- "refcount-bits": 16,
- "corrupt": false
- }
- },
"dirty-flag": false
},
- "backing-filename-format": "qcow2",
+ "backing-filename-format": "IMGFMT",
"virtual-size": 67108864,
- "filename": "TEST_DIR/t.qcow2",
+ "filename": "TEST_DIR/t.IMGFMT",
"cluster-size": 65536,
- "format": "qcow2",
+ "format": "IMGFMT",
"actual-size": SIZE,
- "format-specific": {
- "type": "qcow2",
- "data": {
- "compat": "1.1",
- "lazy-refcounts": false,
- "refcount-bits": 16,
- "corrupt": false
- }
- },
- "full-backing-filename": "TEST_DIR/t.qcow2.base",
- "backing-filename": "TEST_DIR/t.qcow2.base",
+ "full-backing-filename": "TEST_DIR/t.IMGFMT.base",
+ "backing-filename": "TEST_DIR/t.IMGFMT.base",
"dirty-flag": false
},
"iops_wr": 0,
"ro": false,
"node-name": "top",
"backing_file_depth": 1,
- "drv": "qcow2",
+ "drv": "IMGFMT",
"iops": 0,
"bps_wr": 0,
"write_threshold": 0,
- "backing_file": "TEST_DIR/t.qcow2.base",
+ "backing_file": "TEST_DIR/t.IMGFMT.base",
"encrypted": false,
"bps": 0,
"bps_rd": 0,
@@ -184,7 +148,7 @@
"direct": false,
"writeback": true
},
- "file": "TEST_DIR/t.qcow2",
+ "file": "TEST_DIR/t.IMGFMT",
"encryption_key_missing": false
},
{
@@ -192,7 +156,7 @@
"detect_zeroes": "off",
"image": {
"virtual-size": 197120,
- "filename": "TEST_DIR/t.qcow2",
+ "filename": "TEST_DIR/t.IMGFMT",
"format": "file",
"actual-size": SIZE,
"dirty-flag": false
@@ -213,7 +177,7 @@
"direct": false,
"writeback": true
},
- "file": "TEST_DIR/t.qcow2",
+ "file": "TEST_DIR/t.IMGFMT",
"encryption_key_missing": false
},
{
@@ -222,49 +186,31 @@
"image": {
"backing-image": {
"virtual-size": 67108864,
- "filename": "TEST_DIR/t.qcow2.base",
+ "filename": "TEST_DIR/t.IMGFMT.base",
"cluster-size": 65536,
- "format": "qcow2",
+ "format": "IMGFMT",
"actual-size": SIZE,
- "format-specific": {
- "type": "qcow2",
- "data": {
- "compat": "1.1",
- "lazy-refcounts": false,
- "refcount-bits": 16,
- "corrupt": false
- }
- },
"dirty-flag": false
},
- "backing-filename-format": "qcow2",
+ "backing-filename-format": "IMGFMT",
"virtual-size": 67108864,
- "filename": "TEST_DIR/t.qcow2.mid",
+ "filename": "TEST_DIR/t.IMGFMT.mid",
"cluster-size": 65536,
- "format": "qcow2",
+ "format": "IMGFMT",
"actual-size": SIZE,
- "format-specific": {
- "type": "qcow2",
- "data": {
- "compat": "1.1",
- "lazy-refcounts": false,
- "refcount-bits": 16,
- "corrupt": false
- }
- },
- "full-backing-filename": "TEST_DIR/t.qcow2.base",
- "backing-filename": "TEST_DIR/t.qcow2.base",
+ "full-backing-filename": "TEST_DIR/t.IMGFMT.base",
+ "backing-filename": "TEST_DIR/t.IMGFMT.base",
"dirty-flag": false
},
"iops_wr": 0,
"ro": false,
"node-name": "mid",
"backing_file_depth": 1,
- "drv": "qcow2",
+ "drv": "IMGFMT",
"iops": 0,
"bps_wr": 0,
"write_threshold": 0,
- "backing_file": "TEST_DIR/t.qcow2.base",
+ "backing_file": "TEST_DIR/t.IMGFMT.base",
"encrypted": false,
"bps": 0,
"bps_rd": 0,
@@ -273,7 +219,7 @@
"direct": false,
"writeback": true
},
- "file": "TEST_DIR/t.qcow2.mid",
+ "file": "TEST_DIR/t.IMGFMT.mid",
"encryption_key_missing": false
},
{
@@ -281,7 +227,7 @@
"detect_zeroes": "off",
"image": {
"virtual-size": 393216,
- "filename": "TEST_DIR/t.qcow2.mid",
+ "filename": "TEST_DIR/t.IMGFMT.mid",
"format": "file",
"actual-size": SIZE,
"dirty-flag": false
@@ -302,7 +248,7 @@
"direct": false,
"writeback": true
},
- "file": "TEST_DIR/t.qcow2.mid",
+ "file": "TEST_DIR/t.IMGFMT.mid",
"encryption_key_missing": false
},
{
@@ -310,26 +256,17 @@
"detect_zeroes": "off",
"image": {
"virtual-size": 67108864,
- "filename": "TEST_DIR/t.qcow2.base",
+ "filename": "TEST_DIR/t.IMGFMT.base",
"cluster-size": 65536,
- "format": "qcow2",
+ "format": "IMGFMT",
"actual-size": SIZE,
- "format-specific": {
- "type": "qcow2",
- "data": {
- "compat": "1.1",
- "lazy-refcounts": false,
- "refcount-bits": 16,
- "corrupt": false
- }
- },
"dirty-flag": false
},
"iops_wr": 0,
"ro": false,
"node-name": "base",
"backing_file_depth": 0,
- "drv": "qcow2",
+ "drv": "IMGFMT",
"iops": 0,
"bps_wr": 0,
"write_threshold": 0,
@@ -341,7 +278,7 @@
"direct": false,
"writeback": true
},
- "file": "TEST_DIR/t.qcow2.base",
+ "file": "TEST_DIR/t.IMGFMT.base",
"encryption_key_missing": false
},
{
@@ -349,7 +286,7 @@
"detect_zeroes": "off",
"image": {
"virtual-size": 393216,
- "filename": "TEST_DIR/t.qcow2.base",
+ "filename": "TEST_DIR/t.IMGFMT.base",
"format": "file",
"actual-size": SIZE,
"dirty-flag": false
@@ -370,7 +307,7 @@
"direct": false,
"writeback": true
},
- "file": "TEST_DIR/t.qcow2.base",
+ "file": "TEST_DIR/t.IMGFMT.base",
"encryption_key_missing": false
}
]
@@ -447,49 +384,31 @@
"image": {
"backing-image": {
"virtual-size": 67108864,
- "filename": "TEST_DIR/t.qcow2.base",
+ "filename": "TEST_DIR/t.IMGFMT.base",
"cluster-size": 65536,
- "format": "qcow2",
+ "format": "IMGFMT",
"actual-size": SIZE,
- "format-specific": {
- "type": "qcow2",
- "data": {
- "compat": "1.1",
- "lazy-refcounts": false,
- "refcount-bits": 16,
- "corrupt": false
- }
- },
"dirty-flag": false
},
- "backing-filename-format": "qcow2",
+ "backing-filename-format": "IMGFMT",
"virtual-size": 67108864,
- "filename": "TEST_DIR/t.qcow2.ovl2",
+ "filename": "TEST_DIR/t.IMGFMT.ovl2",
"cluster-size": 65536,
- "format": "qcow2",
+ "format": "IMGFMT",
"actual-size": SIZE,
- "format-specific": {
- "type": "qcow2",
- "data": {
- "compat": "1.1",
- "lazy-refcounts": false,
- "refcount-bits": 16,
- "corrupt": false
- }
- },
- "full-backing-filename": "TEST_DIR/t.qcow2.base",
- "backing-filename": "TEST_DIR/t.qcow2.base",
+ "full-backing-filename": "TEST_DIR/t.IMGFMT.base",
+ "backing-filename": "TEST_DIR/t.IMGFMT.base",
"dirty-flag": false
},
"iops_wr": 0,
"ro": true,
"node-name": "NODE_NAME",
"backing_file_depth": 1,
- "drv": "qcow2",
+ "drv": "IMGFMT",
"iops": 0,
"bps_wr": 0,
"write_threshold": 0,
- "backing_file": "TEST_DIR/t.qcow2.base",
+ "backing_file": "TEST_DIR/t.IMGFMT.base",
"encrypted": false,
"bps": 0,
"bps_rd": 0,
@@ -498,7 +417,7 @@
"direct": false,
"writeback": true
},
- "file": "TEST_DIR/t.qcow2.ovl2",
+ "file": "TEST_DIR/t.IMGFMT.ovl2",
"encryption_key_missing": false
},
{
@@ -506,7 +425,7 @@
"detect_zeroes": "off",
"image": {
"virtual-size": 197120,
- "filename": "TEST_DIR/t.qcow2.ovl2",
+ "filename": "TEST_DIR/t.IMGFMT.ovl2",
"format": "file",
"actual-size": SIZE,
"dirty-flag": false
@@ -527,7 +446,7 @@
"direct": false,
"writeback": true
},
- "file": "TEST_DIR/t.qcow2.ovl2",
+ "file": "TEST_DIR/t.IMGFMT.ovl2",
"encryption_key_missing": false
},
{
@@ -537,68 +456,41 @@
"backing-image": {
"backing-image": {
"virtual-size": 67108864,
- "filename": "TEST_DIR/t.qcow2.base",
+ "filename": "TEST_DIR/t.IMGFMT.base",
"cluster-size": 65536,
- "format": "qcow2",
+ "format": "IMGFMT",
"actual-size": SIZE,
- "format-specific": {
- "type": "qcow2",
- "data": {
- "compat": "1.1",
- "lazy-refcounts": false,
- "refcount-bits": 16,
- "corrupt": false
- }
- },
"dirty-flag": false
},
- "backing-filename-format": "qcow2",
+ "backing-filename-format": "IMGFMT",
"virtual-size": 67108864,
- "filename": "TEST_DIR/t.qcow2.ovl2",
+ "filename": "TEST_DIR/t.IMGFMT.ovl2",
"cluster-size": 65536,
- "format": "qcow2",
+ "format": "IMGFMT",
"actual-size": SIZE,
- "format-specific": {
- "type": "qcow2",
- "data": {
- "compat": "1.1",
- "lazy-refcounts": false,
- "refcount-bits": 16,
- "corrupt": false
- }
- },
- "full-backing-filename": "TEST_DIR/t.qcow2.base",
- "backing-filename": "TEST_DIR/t.qcow2.base",
+ "full-backing-filename": "TEST_DIR/t.IMGFMT.base",
+ "backing-filename": "TEST_DIR/t.IMGFMT.base",
"dirty-flag": false
},
- "backing-filename-format": "qcow2",
+ "backing-filename-format": "IMGFMT",
"virtual-size": 67108864,
- "filename": "TEST_DIR/t.qcow2.ovl3",
+ "filename": "TEST_DIR/t.IMGFMT.ovl3",
"cluster-size": 65536,
- "format": "qcow2",
+ "format": "IMGFMT",
"actual-size": SIZE,
- "format-specific": {
- "type": "qcow2",
- "data": {
- "compat": "1.1",
- "lazy-refcounts": false,
- "refcount-bits": 16,
- "corrupt": false
- }
- },
- "full-backing-filename": "TEST_DIR/t.qcow2.ovl2",
- "backing-filename": "TEST_DIR/t.qcow2.ovl2",
+ "full-backing-filename": "TEST_DIR/t.IMGFMT.ovl2",
+ "backing-filename": "TEST_DIR/t.IMGFMT.ovl2",
"dirty-flag": false
},
"iops_wr": 0,
"ro": false,
"node-name": "top2",
"backing_file_depth": 2,
- "drv": "qcow2",
+ "drv": "IMGFMT",
"iops": 0,
"bps_wr": 0,
"write_threshold": 0,
- "backing_file": "TEST_DIR/t.qcow2.ovl2",
+ "backing_file": "TEST_DIR/t.IMGFMT.ovl2",
"encrypted": false,
"bps": 0,
"bps_rd": 0,
@@ -607,7 +499,7 @@
"direct": false,
"writeback": true
},
- "file": "TEST_DIR/t.qcow2.ovl3",
+ "file": "TEST_DIR/t.IMGFMT.ovl3",
"encryption_key_missing": false
},
{
@@ -615,7 +507,7 @@
"detect_zeroes": "off",
"image": {
"virtual-size": 197120,
- "filename": "TEST_DIR/t.qcow2.ovl3",
+ "filename": "TEST_DIR/t.IMGFMT.ovl3",
"format": "file",
"actual-size": SIZE,
"dirty-flag": false
@@ -636,7 +528,7 @@
"direct": false,
"writeback": true
},
- "file": "TEST_DIR/t.qcow2.ovl3",
+ "file": "TEST_DIR/t.IMGFMT.ovl3",
"encryption_key_missing": false
},
{
@@ -644,26 +536,17 @@
"detect_zeroes": "off",
"image": {
"virtual-size": 67108864,
- "filename": "TEST_DIR/t.qcow2.base",
+ "filename": "TEST_DIR/t.IMGFMT.base",
"cluster-size": 65536,
- "format": "qcow2",
+ "format": "IMGFMT",
"actual-size": SIZE,
- "format-specific": {
- "type": "qcow2",
- "data": {
- "compat": "1.1",
- "lazy-refcounts": false,
- "refcount-bits": 16,
- "corrupt": false
- }
- },
"dirty-flag": false
},
"iops_wr": 0,
"ro": true,
"node-name": "NODE_NAME",
"backing_file_depth": 0,
- "drv": "qcow2",
+ "drv": "IMGFMT",
"iops": 0,
"bps_wr": 0,
"write_threshold": 0,
@@ -675,7 +558,7 @@
"direct": false,
"writeback": true
},
- "file": "TEST_DIR/t.qcow2.base",
+ "file": "TEST_DIR/t.IMGFMT.base",
"encryption_key_missing": false
},
{
@@ -683,7 +566,7 @@
"detect_zeroes": "off",
"image": {
"virtual-size": 393216,
- "filename": "TEST_DIR/t.qcow2.base",
+ "filename": "TEST_DIR/t.IMGFMT.base",
"format": "file",
"actual-size": SIZE,
"dirty-flag": false
@@ -704,7 +587,7 @@
"direct": false,
"writeback": true
},
- "file": "TEST_DIR/t.qcow2.base",
+ "file": "TEST_DIR/t.IMGFMT.base",
"encryption_key_missing": false
},
{
@@ -713,49 +596,31 @@
"image": {
"backing-image": {
"virtual-size": 67108864,
- "filename": "TEST_DIR/t.qcow2.base",
+ "filename": "TEST_DIR/t.IMGFMT.base",
"cluster-size": 65536,
- "format": "qcow2",
+ "format": "IMGFMT",
"actual-size": SIZE,
- "format-specific": {
- "type": "qcow2",
- "data": {
- "compat": "1.1",
- "lazy-refcounts": false,
- "refcount-bits": 16,
- "corrupt": false
- }
- },
"dirty-flag": false
},
- "backing-filename-format": "qcow2",
+ "backing-filename-format": "IMGFMT",
"virtual-size": 67108864,
- "filename": "TEST_DIR/t.qcow2",
+ "filename": "TEST_DIR/t.IMGFMT",
"cluster-size": 65536,
- "format": "qcow2",
+ "format": "IMGFMT",
"actual-size": SIZE,
- "format-specific": {
- "type": "qcow2",
- "data": {
- "compat": "1.1",
- "lazy-refcounts": false,
- "refcount-bits": 16,
- "corrupt": false
- }
- },
- "full-backing-filename": "TEST_DIR/t.qcow2.base",
- "backing-filename": "TEST_DIR/t.qcow2.base",
+ "full-backing-filename": "TEST_DIR/t.IMGFMT.base",
+ "backing-filename": "TEST_DIR/t.IMGFMT.base",
"dirty-flag": false
},
"iops_wr": 0,
"ro": false,
"node-name": "top",
"backing_file_depth": 1,
- "drv": "qcow2",
+ "drv": "IMGFMT",
"iops": 0,
"bps_wr": 0,
"write_threshold": 0,
- "backing_file": "TEST_DIR/t.qcow2.base",
+ "backing_file": "TEST_DIR/t.IMGFMT.base",
"encrypted": false,
"bps": 0,
"bps_rd": 0,
@@ -764,7 +629,7 @@
"direct": false,
"writeback": true
},
- "file": "TEST_DIR/t.qcow2",
+ "file": "TEST_DIR/t.IMGFMT",
"encryption_key_missing": false
},
{
@@ -772,7 +637,7 @@
"detect_zeroes": "off",
"image": {
"virtual-size": 197120,
- "filename": "TEST_DIR/t.qcow2",
+ "filename": "TEST_DIR/t.IMGFMT",
"format": "file",
"actual-size": SIZE,
"dirty-flag": false
@@ -793,7 +658,7 @@
"direct": false,
"writeback": true
},
- "file": "TEST_DIR/t.qcow2",
+ "file": "TEST_DIR/t.IMGFMT",
"encryption_key_missing": false
}
]
diff --git a/tests/qemu-iotests/198 b/tests/qemu-iotests/198
index 34ef666..54eaaf5 100755
--- a/tests/qemu-iotests/198
+++ b/tests/qemu-iotests/198
@@ -91,11 +91,15 @@
echo
echo "== checking image base =="
-$QEMU_IMG info --image-opts $IMGSPECBASE | _filter_img_info | _filter_testdir | sed -e "/^disk size:/ D"
+$QEMU_IMG info --image-opts $IMGSPECBASE | _filter_img_info --format-specific \
+ | sed -e "/^disk size:/ D" -e '/refcount bits:/ D' -e '/compat:/ D' \
+ -e '/lazy refcounts:/ D' -e '/corrupt:/ D'
echo
echo "== checking image layer =="
-$QEMU_IMG info --image-opts $IMGSPECLAYER | _filter_img_info | _filter_testdir | sed -e "/^disk size:/ D"
+$QEMU_IMG info --image-opts $IMGSPECLAYER | _filter_img_info --format-specific \
+ | sed -e "/^disk size:/ D" -e '/refcount bits:/ D' -e '/compat:/ D' \
+ -e '/lazy refcounts:/ D' -e '/corrupt:/ D'
# success, all done
diff --git a/tests/qemu-iotests/198.out b/tests/qemu-iotests/198.out
index 2db565e..adb805c 100644
--- a/tests/qemu-iotests/198.out
+++ b/tests/qemu-iotests/198.out
@@ -36,9 +36,6 @@
file format: IMGFMT
virtual size: 16M (16777216 bytes)
Format specific information:
- compat: 1.1
- lazy refcounts: false
- refcount bits: 16
encrypt:
ivgen alg: plain64
hash alg: sha256
@@ -75,7 +72,6 @@
key offset: 1810432
payload offset: 2068480
master key iters: 1024
- corrupt: false
== checking image layer ==
image: json:{"encrypt.key-secret": "sec1", "driver": "IMGFMT", "file": {"driver": "file", "filename": "TEST_DIR/t.IMGFMT"}}
@@ -83,9 +79,6 @@
virtual size: 16M (16777216 bytes)
backing file: TEST_DIR/t.IMGFMT.base
Format specific information:
- compat: 1.1
- lazy refcounts: false
- refcount bits: 16
encrypt:
ivgen alg: plain64
hash alg: sha256
@@ -122,5 +115,4 @@
key offset: 1810432
payload offset: 2068480
master key iters: 1024
- corrupt: false
*** done
diff --git a/tests/qemu-iotests/201 b/tests/qemu-iotests/201
new file mode 100755
index 0000000..11f640f
--- /dev/null
+++ b/tests/qemu-iotests/201
@@ -0,0 +1,120 @@
+#!/bin/bash
+#
+# Test savevm and loadvm after live migration with postcopy flag
+#
+# Copyright (C) 2017, IBM Corporation.
+#
+# This file is derived from tests/qemu-iotests/181 by Kevin Wolf
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+seq=`basename $0`
+echo "QA output created by $seq"
+
+status=1 # failure is the default!
+
+MIG_SOCKET="${TEST_DIR}/migrate"
+
+# get standard environment, filters and checks
+. ./common.rc
+. ./common.filter
+. ./common.qemu
+
+_cleanup()
+{
+ rm -f "${MIG_SOCKET}"
+ _cleanup_test_img
+ _cleanup_qemu
+}
+trap "_cleanup; exit \$status" 0 1 2 3 15
+
+_supported_fmt qcow2
+_supported_proto generic
+_supported_os Linux
+
+# Internal snapshots are (currently) impossible with refcount_bits=1
+# This was taken from test 080
+_unsupported_imgopts 'refcount_bits=1[^0-9]'
+
+size=64M
+_make_test_img $size
+
+echo
+echo === Starting VMs ===
+echo
+
+qemu_comm_method="monitor"
+
+if [ "$IMGOPTSSYNTAX" = "true" ]; then
+ _launch_qemu \
+ -drive "${TEST_IMG}",cache=${CACHEMODE},id=disk
+else
+ _launch_qemu \
+ -drive file="${TEST_IMG}",cache=${CACHEMODE},driver=$IMGFMT,id=disk
+fi
+src=$QEMU_HANDLE
+
+if [ "$IMGOPTSSYNTAX" = "true" ]; then
+ _launch_qemu \
+ -drive "${TEST_IMG}",cache=${CACHEMODE},id=disk \
+ -incoming "unix:${MIG_SOCKET}"
+else
+ _launch_qemu \
+ -drive file="${TEST_IMG}",cache=${CACHEMODE},driver=$IMGFMT,id=disk \
+ -incoming "unix:${MIG_SOCKET}"
+fi
+dest=$QEMU_HANDLE
+
+echo
+echo === Set \'migrate_set_capability postcopy-ram on\' and migrate ===
+echo
+
+silent=yes
+_send_qemu_cmd $dest 'migrate_set_capability postcopy-ram on' "(qemu)"
+_send_qemu_cmd $src 'migrate_set_capability postcopy-ram on' "(qemu)"
+_send_qemu_cmd $src "migrate -d unix:${MIG_SOCKET}" "(qemu)"
+
+QEMU_COMM_TIMEOUT=1 qemu_cmd_repeat=10 silent=yes \
+ _send_qemu_cmd $src "info migrate" "completed\|failed"
+silent=yes _send_qemu_cmd $src "" "(qemu)"
+
+echo
+echo === Check if migration was successful ===
+echo
+
+QEMU_COMM_TIMEOUT=1 silent=yes \
+ _send_qemu_cmd $src "info migrate" "completed"
+silent=yes _send_qemu_cmd $src "" "(qemu)"
+
+echo
+echo === On destination, execute savevm and loadvm ===
+echo
+
+silent=
+_send_qemu_cmd $dest 'savevm state1' "(qemu)"
+_send_qemu_cmd $dest 'loadvm state1' "(qemu)"
+
+echo
+echo === Shut down and check image ===
+echo
+
+_send_qemu_cmd $src 'quit' ""
+_send_qemu_cmd $dest 'quit' ""
+wait=1 _cleanup_qemu
+
+_check_test_img
+
+# success, all done
+echo "*** done"
+status=0
diff --git a/tests/qemu-iotests/201.out b/tests/qemu-iotests/201.out
new file mode 100644
index 0000000..9faf06f
--- /dev/null
+++ b/tests/qemu-iotests/201.out
@@ -0,0 +1,23 @@
+QA output created by 201
+Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=67108864
+
+=== Starting VMs ===
+
+
+=== Set 'migrate_set_capability postcopy-ram on' and migrate ===
+
+
+=== Check if migration was successful ===
+
+
+=== On destination, execute savevm and loadvm ===
+
+(qemu) savevm state1
+(qemu) loadvm state1
+
+=== Shut down and check image ===
+
+(qemu) quit
+(qemu) quit
+No errors were found on the image.
+*** done
diff --git a/tests/qemu-iotests/204 b/tests/qemu-iotests/204
new file mode 100755
index 0000000..feb69d2
--- /dev/null
+++ b/tests/qemu-iotests/204
@@ -0,0 +1,119 @@
+#!/bin/bash
+#
+# Test corner cases with unusual block geometries
+#
+# Copyright (C) 2016-2018 Red Hat, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+
+# creator
+owner=eblake@redhat.com
+
+seq=`basename $0`
+echo "QA output created by $seq"
+
+here=`pwd`
+status=1 # failure is the default!
+
+_cleanup()
+{
+ _cleanup_test_img
+}
+trap "_cleanup; exit \$status" 0 1 2 3 15
+
+# get standard environment, filters and checks
+. ./common.rc
+. ./common.filter
+
+_supported_fmt qcow2
+_supported_proto file
+# This test assumes that discard leaves zero clusters; see test 177 for
+# other tests that also work in older images
+_unsupported_imgopts 'compat=0.10'
+
+CLUSTER_SIZE=1M
+size=128M
+options=driver=blkdebug,image.driver=qcow2
+nested_opts=image.file.driver=file,image.file.filename=$TEST_IMG
+
+echo
+echo "== setting up files =="
+
+TEST_IMG="$TEST_IMG.base" _make_test_img $size
+$QEMU_IO -c "write -P 11 0 $size" "$TEST_IMG.base" | _filter_qemu_io
+_make_test_img -b "$TEST_IMG.base"
+$QEMU_IO -c "write -P 22 0 110M" "$TEST_IMG" | _filter_qemu_io
+
+# Limited to 64k max-transfer
+echo
+echo "== constrained alignment and max-transfer =="
+limits=align=4k,max-transfer=64k
+$QEMU_IO -c "open -o $options,$limits blkdebug::$TEST_IMG" \
+ -c "write -P 33 1000 128k" -c "read -P 33 1000 128k" | _filter_qemu_io
+
+echo
+echo "== write zero with constrained max-transfer =="
+limits=align=512,max-transfer=64k,opt-write-zero=$CLUSTER_SIZE
+$QEMU_IO -c "open -o $options,$limits blkdebug::$TEST_IMG" \
+ -c "write -z 8003584 2093056" | _filter_qemu_io
+
+# non-power-of-2 write-zero/discard alignments
+echo
+echo "== non-power-of-2 write zeroes limits =="
+
+limits=align=512,opt-write-zero=15M,max-write-zero=15M,opt-discard=15M,max-discard=15M
+$QEMU_IO -c "open -o $options,$limits blkdebug::$TEST_IMG" \
+ -c "write -z 32M 32M" | _filter_qemu_io
+
+echo
+echo "== non-power-of-2 discard limits =="
+
+limits=align=512,opt-write-zero=15M,max-write-zero=15M,opt-discard=15M,max-discard=15M
+$QEMU_IO -c "open -o $options,$limits blkdebug::$TEST_IMG" \
+ -c "discard 80000001 30M" | _filter_qemu_io
+
+echo
+echo "== block status smaller than alignment =="
+limits=align=4k
+$QEMU_IO -c "open -o $options,$limits blkdebug::$TEST_IMG" \
+ -c "alloc 1 1" -c "alloc 0x6dffff0 1000" -c "alloc 127m 5P" \
+ -c map | _filter_qemu_io
+
+echo
+echo "== verify image content =="
+
+function verify_io()
+{
+ echo read -P 22 0 1000
+ echo read -P 33 1000 128k
+ echo read -P 22 132072 7871512
+ echo read -P 0 8003584 2093056
+ echo read -P 22 10096640 23457792
+ echo read -P 0 32M 32M
+ echo read -P 22 64M 13M
+ echo read -P 0 77M 29M
+ echo read -P 22 106M 4M
+ echo read -P 11 110M 18M
+}
+
+verify_io | $QEMU_IO -r "$TEST_IMG" | _filter_qemu_io
+$QEMU_IMG map --image-opts "$options,$nested_opts,align=4k" \
+ | _filter_qemu_img_map
+
+_check_test_img
+
+# success, all done
+echo "*** done"
+status=0
diff --git a/tests/qemu-iotests/204.out b/tests/qemu-iotests/204.out
new file mode 100644
index 0000000..f3a10fb
--- /dev/null
+++ b/tests/qemu-iotests/204.out
@@ -0,0 +1,63 @@
+QA output created by 204
+
+== setting up files ==
+Formatting 'TEST_DIR/t.IMGFMT.base', fmt=IMGFMT size=134217728
+wrote 134217728/134217728 bytes at offset 0
+128 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
+Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=134217728 backing_file=TEST_DIR/t.IMGFMT.base
+wrote 115343360/115343360 bytes at offset 0
+110 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
+
+== constrained alignment and max-transfer ==
+wrote 131072/131072 bytes at offset 1000
+128 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
+read 131072/131072 bytes at offset 1000
+128 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
+
+== write zero with constrained max-transfer ==
+wrote 2093056/2093056 bytes at offset 8003584
+1.996 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
+
+== non-power-of-2 write zeroes limits ==
+wrote 33554432/33554432 bytes at offset 33554432
+32 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
+
+== non-power-of-2 discard limits ==
+discard 31457280/31457280 bytes at offset 80000001
+30 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
+
+== block status smaller than alignment ==
+1/1 bytes allocated at offset 1 bytes
+16/1000 bytes allocated at offset 110 MiB
+0/1048576 bytes allocated at offset 127 MiB
+110 MiB (0x6e00000) bytes allocated at offset 0 bytes (0x0)
+18 MiB (0x1200000) bytes not allocated at offset 110 MiB (0x6e00000)
+
+== verify image content ==
+read 1000/1000 bytes at offset 0
+1000 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
+read 131072/131072 bytes at offset 1000
+128 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
+read 7871512/7871512 bytes at offset 132072
+7.507 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
+read 2093056/2093056 bytes at offset 8003584
+1.996 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
+read 23457792/23457792 bytes at offset 10096640
+22.371 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
+read 33554432/33554432 bytes at offset 33554432
+32 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
+read 13631488/13631488 bytes at offset 67108864
+13 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
+read 30408704/30408704 bytes at offset 80740352
+29 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
+read 4194304/4194304 bytes at offset 111149056
+4 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
+read 18874368/18874368 bytes at offset 115343360
+18 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
+Offset Length File
+0 0x800000 TEST_DIR/t.IMGFMT
+0x900000 0x2400000 TEST_DIR/t.IMGFMT
+0x3c00000 0x1100000 TEST_DIR/t.IMGFMT
+0x6a00000 0x400000 TEST_DIR/t.IMGFMT
+No errors were found on the image.
+*** done
diff --git a/tests/qemu-iotests/common.filter b/tests/qemu-iotests/common.filter
index f08248b..cb2be23 100644
--- a/tests/qemu-iotests/common.filter
+++ b/tests/qemu-iotests/common.filter
@@ -140,6 +140,15 @@
_filter_img_info()
{
+ if [[ "$1" == "--format-specific" ]]; then
+ local format_specific=1
+ shift
+ else
+ local format_specific=0
+ fi
+
+ discard=0
+ regex_json_spec_start='^ *"format-specific": \{'
sed -e "s#$IMGPROTO:$TEST_DIR#TEST_DIR#g" \
-e "s#$TEST_DIR#TEST_DIR#g" \
-e "s#$IMGFMT#IMGFMT#g" \
@@ -160,7 +169,25 @@
-e "/block_state_zero: \\(on\\|off\\)/d" \
-e "/log_size: [0-9]\\+/d" \
-e "s/iters: [0-9]\\+/iters: 1024/" \
- -e "s/uuid: [-a-f0-9]\\+/uuid: 00000000-0000-0000-0000-000000000000/"
+ -e "s/uuid: [-a-f0-9]\\+/uuid: 00000000-0000-0000-0000-000000000000/" | \
+ while IFS='' read -r line; do
+ if [[ $format_specific == 1 ]]; then
+ discard=0
+ elif [[ $line == "Format specific information:" ]]; then
+ discard=1
+ elif [[ $line =~ $regex_json_spec_start ]]; then
+ discard=2
+ regex_json_spec_end="^${line%%[^ ]*}\\},? *$"
+ fi
+ if [[ $discard == 0 ]]; then
+ echo "$line"
+ elif [[ $discard == 1 && ! $line ]]; then
+ echo
+ discard=0
+ elif [[ $discard == 2 && $line =~ $regex_json_spec_end ]]; then
+ discard=0
+ fi
+ done
}
# filter out offsets and file names from qemu-img map; good for both
diff --git a/tests/qemu-iotests/common.rc b/tests/qemu-iotests/common.rc
index dbae7d7..6fa0495 100644
--- a/tests/qemu-iotests/common.rc
+++ b/tests/qemu-iotests/common.rc
@@ -338,7 +338,7 @@
-e "s#$IMGFMT#IMGFMT#g" \
-e "/^disk size:/ D" \
-e "/actual-size/ D" | \
- while IFS='' read line; do
+ while IFS='' read -r line; do
if [[ $format_specific == 1 ]]; then
discard=0
elif [[ $line == "Format specific information:" ]]; then
diff --git a/tests/qemu-iotests/group b/tests/qemu-iotests/group
index 93d96fb..8fc4f62 100644
--- a/tests/qemu-iotests/group
+++ b/tests/qemu-iotests/group
@@ -197,5 +197,7 @@
197 rw auto quick
198 rw auto
200 rw auto
+201 rw auto migration
202 rw auto quick
203 rw auto
+204 rw auto quick
diff --git a/util/event_notifier-posix.c b/util/event_notifier-posix.c
index 6525666..73c4046 100644
--- a/util/event_notifier-posix.c
+++ b/util/event_notifier-posix.c
@@ -29,7 +29,6 @@
{
e->rfd = fd;
e->wfd = fd;
- e->cleanup = NULL;
}
#endif
@@ -66,7 +65,6 @@
e->rfd = fds[0];
e->wfd = fds[1];
}
- e->cleanup = NULL;
if (active) {
event_notifier_set(e);
}
@@ -82,11 +80,10 @@
{
if (e->rfd != e->wfd) {
close(e->rfd);
+ e->rfd = -1;
}
close(e->wfd);
- e->rfd = -1;
e->wfd = -1;
- e->cleanup = NULL;
}
int event_notifier_get_fd(const EventNotifier *e)
diff --git a/util/event_notifier-win32.c b/util/event_notifier-win32.c
index eff8670..62c53b0 100644
--- a/util/event_notifier-win32.c
+++ b/util/event_notifier-win32.c
@@ -19,7 +19,6 @@
{
e->event = CreateEvent(NULL, TRUE, FALSE, NULL);
assert(e->event);
- e->cleanup = NULL;
return 0;
}
@@ -27,7 +26,6 @@
{
CloseHandle(e->event);
e->event = NULL;
- e->cleanup = NULL;
}
HANDLE event_notifier_get_handle(EventNotifier *e)
diff --git a/util/osdep.c b/util/osdep.c
index 1231f9f..a73de0e 100644
--- a/util/osdep.c
+++ b/util/osdep.c
@@ -244,7 +244,9 @@
.l_type = fl_type,
};
qemu_probe_lock_ops();
- ret = fcntl(fd, fcntl_op_setlk, &fl);
+ do {
+ ret = fcntl(fd, fcntl_op_setlk, &fl);
+ } while (ret == -1 && errno == EINTR);
return ret == -1 ? -errno : 0;
}
