Merge tag 'pull-ppc-for-10.2-d4-20251030' of https://gitlab.com/harshpb/qemu into staging
ppc queue for 10.2
* Firmware updates for SLOF, sam460ex u-boot
* Removal of unusable e200 CPUs
* Coverity fixes for fadump
* Other minor fixes, cleanups for pegasos, spapr.
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# gpg: Signature made Thu 30 Oct 2025 09:18:11 AM CET
# gpg: using RSA key 6B810CD6D2BE10F3883D21424544E994F9D68FBB
# gpg: Good signature from "Harsh Prateek Bora <harsh.prateek.bora@gmail.com>" [undefined]
# gpg: aka "Harsh Prateek Bora <harshpb@linux.ibm.com>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6B81 0CD6 D2BE 10F3 883D 2142 4544 E994 F9D6 8FBB
* tag 'pull-ppc-for-10.2-d4-20251030' of https://gitlab.com/harshpb/qemu:
hw/ppc/pegasos: Update documentation for pegasos1
hw/ppc/pegasos2: Rename to pegasos
hw/ppc/pegasos2: Add /chosen/stdin node with VOF
hw/ppc: Fix memory leak in get_cpu_state_data()
hw/ppc: Fix missing return on allocation failure
ppc/spapr: Cleanup MSI IRQ number handling
target/ppc: Remove the unusable e200 CPUs
target/ppc/cpu_init: Simplify the setup of the TLBxCFG SPR registers
hw/ppc/sam460ex: Update u-boot-sam460ex
pseries: Update SLOF firmware image to release 20251027
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
diff --git a/MAINTAINERS b/MAINTAINERS
index a694803..030d505 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1643,16 +1643,16 @@
F: hw/ide/sii3112.c
F: hw/rtc/m41t80.c
F: pc-bios/dtb/canyonlands.dt[sb]
-F: pc-bios/u-boot-sam460ex-20100605.bin
+F: pc-bios/u-boot-sam460ex.bin
F: roms/u-boot-sam460ex
F: docs/system/ppc/amigang.rst
F: tests/functional/ppc/test_sam460ex.py
-pegasos2
+pegasos
M: BALATON Zoltan <balaton@eik.bme.hu>
L: qemu-ppc@nongnu.org
S: Maintained
-F: hw/ppc/pegasos2.c
+F: hw/ppc/pegasos.c
F: hw/pci-host/mv64361.c
F: hw/pci-host/mv643xx.h
F: include/hw/pci-host/mv64361.h
diff --git a/configs/devices/ppc-softmmu/default.mak b/configs/devices/ppc-softmmu/default.mak
index 460d15e..180ae31 100644
--- a/configs/devices/ppc-softmmu/default.mak
+++ b/configs/devices/ppc-softmmu/default.mak
@@ -13,15 +13,14 @@
# CONFIG_PPC440=n
# CONFIG_VIRTEX=n
-# For Sam460ex
+# AmigaNG
+# CONFIG_AMIGAONE=n
+# CONFIG_PEGASOS=n
# CONFIG_SAM460EX=n
# For Macs
# CONFIG_MAC_OLDWORLD=n
# CONFIG_MAC_NEWWORLD=n
-# CONFIG_AMIGAONE=n
-# CONFIG_PEGASOS2=n
-
# For PReP
# CONFIG_PREP=n
diff --git a/docs/system/ppc/amigang.rst b/docs/system/ppc/amigang.rst
index 21bb14e..e290412 100644
--- a/docs/system/ppc/amigang.rst
+++ b/docs/system/ppc/amigang.rst
@@ -1,6 +1,6 @@
-=========================================================
-AmigaNG boards (``amigaone``, ``pegasos2``, ``sam460ex``)
-=========================================================
+=======================================================================
+AmigaNG boards (``amigaone``, ``pegasos1``, ``pegasos2``, ``sam460ex``)
+=======================================================================
These PowerPC machines emulate boards that are primarily used for
running Amiga like OSes (AmigaOS 4, MorphOS and AROS) but these can
@@ -64,18 +64,23 @@
emulation is not complete yet so only frame buffer works, DRM and 3D is not
available.
-Genesi/bPlan Pegasos II (``pegasos2``)
-======================================
+Genesi/bPlan Pegasos (``pegasos1``, ``pegasos2``)
+=================================================
-The ``pegasos2`` machine emulates the Pegasos II sold by Genesi and
-designed by bPlan. Its schematics are available at
-https://www.powerdeveloper.org/platforms/pegasos/schematics.
+The ``pegasos1`` machine emulates the original Pegasos (later marked I) sold by
+Genesi and designed by bPlan. It uses the same Articia S north bridge as the
+``amigaone`` machine, otherwise it is mostly the same as the later Pegasos II.
+
+The ``pegasos2`` machine emulates the Pegasos II which is a redesigned version
+of Pegasos I to fix problems with its north bridge. Its schematics are available
+at https://www.powerdeveloper.org/platforms/pegasos/schematics.
Emulated devices
----------------
* PowerPC 7457 CPU (can also use ``-cpu g3`` or ``750cxe``)
- * Marvell MV64361 Discovery II north bridge
+ * Articia S north bridge (for ``pegasos1``)
+ * Marvell MV64361 Discovery II north bridge (for ``pegasos2``)
* VIA VT8231 south bridge
* PCI VGA compatible card (guests may need other card instead)
* PS/2 keyboard and mouse
@@ -83,9 +88,9 @@
Firmware
--------
-The Pegasos II board has an Open Firmware compliant ROM based on
+The Pegasos boards have an Open Firmware compliant ROM based on
SmartFirmware with some changes that are not open-sourced therefore
-the ROM binary cannot be included in QEMU. An updater was available
+the ROM binary cannot be included in QEMU. A Pegasos II updater was available
from bPlan, it can be found in the `Internet Archive
<http://web.archive.org/web/20071021223056/http://www.bplan-gmbh.de/up050404/up050404>`_.
The ROM image can be extracted from it with the following command:
@@ -111,7 +116,7 @@
Alternatively, it is possible to boot the kernel directly without
firmware ROM using the QEMU built-in minimal Virtual Open Firmware
-(VOF) emulation which is also supported on ``pegasos2``. For this,
+(VOF) emulation which is also supported on ``pegasos1`` and ``pegasos2``. For this,
extract the kernel ``install/powerpc/vmlinuz-chrp.initrd`` from the CD
image, then run:
diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig
index 7091d72..347dcce 100644
--- a/hw/ppc/Kconfig
+++ b/hw/ppc/Kconfig
@@ -92,7 +92,7 @@
select VT82C686
select SMBUS_EEPROM
-config PEGASOS2
+config PEGASOS
bool
default y
depends on PPC
diff --git a/hw/ppc/meson.build b/hw/ppc/meson.build
index 6b7c1f4..f7dac87 100644
--- a/hw/ppc/meson.build
+++ b/hw/ppc/meson.build
@@ -87,8 +87,8 @@
ppc_ss.add(when: 'CONFIG_VIRTEX', if_true: files('virtex_ml507.c'))
# AmigaOne
ppc_ss.add(when: 'CONFIG_AMIGAONE', if_true: files('amigaone.c'))
-# Pegasos2
-ppc_ss.add(when: 'CONFIG_PEGASOS2', if_true: files('pegasos2.c'))
+# Pegasos
+ppc_ss.add(when: 'CONFIG_PEGASOS', if_true: files('pegasos.c'))
ppc_ss.add(when: 'CONFIG_VOF', if_true: files('vof.c'))
ppc_ss.add(when: ['CONFIG_VOF', 'CONFIG_PSERIES'], if_true: files('spapr_vof.c'))
diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos.c
similarity index 99%
rename from hw/ppc/pegasos2.c
rename to hw/ppc/pegasos.c
index 3c02c53..3a498ed 100644
--- a/hw/ppc/pegasos2.c
+++ b/hw/ppc/pegasos.c
@@ -561,6 +561,7 @@
qemu_fdt_setprop(fdt, "/chosen", "qemu,boot-kernel", d, sizeof(d));
vof_build_dt(fdt, pm->vof);
+ vof_client_open_store(fdt, pm->vof, "/chosen", "stdin", "/failsafe");
vof_client_open_store(fdt, pm->vof, "/chosen", "stdout", "/failsafe");
/* Set machine->fdt for 'dumpdtb' QMP/HMP command */
diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
index 258d43f..038b98d 100644
--- a/hw/ppc/sam460ex.c
+++ b/hw/ppc/sam460ex.c
@@ -43,10 +43,7 @@
#include <libfdt.h>
#define BINARY_DEVICE_TREE_FILE "canyonlands.dtb"
-#define UBOOT_FILENAME "u-boot-sam460-20100605.bin"
-/* to extract the official U-Boot bin from the updater: */
-/* dd bs=1 skip=$(($(stat -c '%s' updater/updater-460) - 0x80000)) \
- if=updater/updater-460 of=u-boot-sam460-20100605.bin */
+#define UBOOT_FILENAME "u-boot-sam460.bin"
#define PCIE0_DCRN_BASE 0x100
#define PCIE1_DCRN_BASE 0x120
@@ -97,7 +94,7 @@
*
* Else, it's initialized to zero. And then 512KiB of ROM get
* mapped on top of its second half (0xFFF80000..0xFFFFFFFF),
- * initialized from u-boot-sam460-20100605.bin.
+ * initialized from UBOOT_FILENAME.
*
* This doesn't smell right.
*
diff --git a/hw/ppc/spapr_fadump.c b/hw/ppc/spapr_fadump.c
index fa3aeac..13cab0c 100644
--- a/hw/ppc/spapr_fadump.c
+++ b/hw/ppc/spapr_fadump.c
@@ -234,6 +234,7 @@
qemu_log_mask(LOG_GUEST_ERROR,
"FADump: Failed allocating memory (size: %zu) for copying"
" reserved memory regions\n", FADUMP_CHUNK_SIZE);
+ return false;
}
num_chunks = ceil((src_len * 1.0f) / FADUMP_CHUNK_SIZE);
@@ -452,7 +453,7 @@
static void *get_cpu_state_data(uint64_t *cpu_state_len)
{
FadumpRegSaveAreaHeader reg_save_hdr;
- FadumpRegEntry *reg_entries;
+ g_autofree FadumpRegEntry *reg_entries = NULL;
FadumpRegEntry *curr_reg_entry;
CPUState *cpu;
diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c
index 2ce3234..fc45a5d 100644
--- a/hw/ppc/spapr_irq.c
+++ b/hw/ppc/spapr_irq.c
@@ -33,7 +33,7 @@
static void spapr_irq_msi_init(SpaprMachineState *spapr)
{
- spapr->irq_map_nr = spapr_irq_nr_msis(spapr);
+ spapr->irq_map_nr = SPAPR_IRQ_NR_MSIS;
spapr->irq_map = bitmap_new(spapr->irq_map_nr);
}
@@ -277,11 +277,6 @@
sicc->dt(spapr->active_intc, nr_servers, fdt, phandle);
}
-uint32_t spapr_irq_nr_msis(SpaprMachineState *spapr)
-{
- return SPAPR_NR_XIRQS + SPAPR_XIRQ_BASE - SPAPR_IRQ_MSI;
-}
-
void spapr_irq_init(SpaprMachineState *spapr, Error **errp)
{
if (kvm_enabled() && kvm_kernel_irqchip_split()) {
diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
index bdec8f0..d596a9e 100644
--- a/hw/ppc/spapr_pci.c
+++ b/hw/ppc/spapr_pci.c
@@ -2279,7 +2279,7 @@
_FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg)));
_FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1));
_FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pe-total-#msi",
- spapr_irq_nr_msis(spapr)));
+ SPAPR_IRQ_NR_MSIS));
/* Dynamic DMA window */
if (phb->ddw_enabled) {
diff --git a/include/hw/ppc/spapr_irq.h b/include/hw/ppc/spapr_irq.h
index 5ddd110..265d43e 100644
--- a/include/hw/ppc/spapr_irq.h
+++ b/include/hw/ppc/spapr_irq.h
@@ -40,6 +40,7 @@
#define SPAPR_IRQ_MSI (SPAPR_XIRQ_BASE + 0x0300)
#define SPAPR_NR_XIRQS 0x1000
+#define SPAPR_IRQ_NR_MSIS (SPAPR_XIRQ_BASE + SPAPR_NR_XIRQS - SPAPR_IRQ_MSI)
struct SpaprMachineState;
@@ -89,7 +90,6 @@
void spapr_irq_dt(struct SpaprMachineState *spapr, uint32_t nr_servers,
void *fdt, uint32_t phandle);
-uint32_t spapr_irq_nr_msis(struct SpaprMachineState *spapr);
int spapr_irq_msi_alloc(struct SpaprMachineState *spapr, uint32_t num, bool align,
Error **errp);
void spapr_irq_msi_free(struct SpaprMachineState *spapr, int irq, uint32_t num);
diff --git a/pc-bios/README b/pc-bios/README
index d009c37..4818272 100644
--- a/pc-bios/README
+++ b/pc-bios/README
@@ -14,7 +14,7 @@
- SLOF (Slimline Open Firmware) is a free IEEE 1275 Open Firmware
implementation for certain IBM POWER hardware. The sources are at
https://gitlab.com/slof/slof, and the image currently in qemu is
- built from git tag qemu-slof-20241106.
+ built from git tag qemu-slof-20251026.
- VOF (Virtual Open Firmware) is a minimalistic firmware to work with
-machine pseries,x-vof=on. When enabled, the firmware acts as a slim shim and
diff --git a/pc-bios/meson.build b/pc-bios/meson.build
index 3c41620..9260aaa 100644
--- a/pc-bios/meson.build
+++ b/pc-bios/meson.build
@@ -74,7 +74,7 @@
'pnv-pnor.bin',
'palcode-clipper',
'u-boot.e500',
- 'u-boot-sam460-20100605.bin',
+ 'u-boot-sam460.bin',
'qemu_vga.ndrv',
'edk2-licenses.txt',
'hppa-firmware.img',
diff --git a/pc-bios/slof.bin b/pc-bios/slof.bin
index 4314e17..39b9248 100644
--- a/pc-bios/slof.bin
+++ b/pc-bios/slof.bin
Binary files differ
diff --git a/pc-bios/u-boot-sam460-20100605.bin b/pc-bios/u-boot-sam460-20100605.bin
deleted file mode 100644
index e17de77..0000000
--- a/pc-bios/u-boot-sam460-20100605.bin
+++ /dev/null
Binary files differ
diff --git a/pc-bios/u-boot-sam460.bin b/pc-bios/u-boot-sam460.bin
new file mode 100644
index 0000000..6663683
--- /dev/null
+++ b/pc-bios/u-boot-sam460.bin
Binary files differ
diff --git a/roms/Makefile b/roms/Makefile
index 4c8793c..f15189a 100644
--- a/roms/Makefile
+++ b/roms/Makefile
@@ -144,9 +144,10 @@
../pc-bios/u-boot.e500
u-boot.sam460:
- $(MAKE) -C u-boot-sam460ex Sam460ex_config
+ $(MAKE) -C u-boot-sam460ex Sam460_50_config
$(MAKE) -C u-boot-sam460ex CROSS_COMPILE=$(powerpc_cross_prefix)
- cp u-boot-sam460ex/u-boot.bin ../pc-bios/u-boot-sam460-20100605.bin
+ cp u-boot-sam460ex/u-boot.bin ../pc-bios/u-boot-sam460.bin
+ chmod -x ../pc-bios/u-boot-sam460.bin
skiboot:
$(MAKE) -C skiboot CROSS=$(powerpc64_cross_prefix)
diff --git a/roms/SLOF b/roms/SLOF
index 3a259df..b7f7552 160000
--- a/roms/SLOF
+++ b/roms/SLOF
@@ -1 +1 @@
-Subproject commit 3a259df2449fc4a4e43ab5f33f0b2c66484b4bc3
+Subproject commit b7f755248e2dcc56c02634d288e1c0ff7e0ce1c7
diff --git a/roms/u-boot-sam460ex b/roms/u-boot-sam460ex
index 60b3916..1e5f4a1 160000
--- a/roms/u-boot-sam460ex
+++ b/roms/u-boot-sam460ex
@@ -1 +1 @@
-Subproject commit 60b3916f33e617a815973c5a6df77055b2e3a588
+Subproject commit 1e5f4a1607cc6713d27ffe48dd9de84e69cfc1c2
diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c
index 89ae763..26b6deb 100644
--- a/target/ppc/cpu-models.c
+++ b/target/ppc/cpu-models.c
@@ -244,11 +244,6 @@
CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2LE)
POWERPC_DEF_SVR("mpc5200b_v21", "MPC5200B v2.1",
CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE)
- /* e200 family */
- POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, e200,
- "PowerPC e200z5 core")
- POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, e200,
- "PowerPC e200z6 core")
/* e300 family */
POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, e300,
"PowerPC e300c1 core")
diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h
index c6cd27f..a439eb3 100644
--- a/target/ppc/cpu-models.h
+++ b/target/ppc/cpu-models.h
@@ -120,10 +120,6 @@
#define CPU_POWERPC_MPC5200_v12 CPU_POWERPC_G2LEgp1
#define CPU_POWERPC_MPC5200B_v20 CPU_POWERPC_G2LEgp1
#define CPU_POWERPC_MPC5200B_v21 CPU_POWERPC_G2LEgp1
- /* e200 family */
- /* e200 cores */
- CPU_POWERPC_e200z5 = 0x81000000,
- CPU_POWERPC_e200z6 = 0x81120000,
/* e300 family */
/* e300 cores */
CPU_POWERPC_e300c1 = 0x00830010,
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 3aa3aef..86ead74 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -850,6 +850,13 @@
SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
};
+ const char *tlbcfg_names[4] = {
+ "TLB0CFG", "TLB1CFG", "TLB2CFG", "TLB3CFG",
+ };
+ const int tlbcfg_sprn[4] = {
+ SPR_BOOKE_TLB0CFG, SPR_BOOKE_TLB1CFG,
+ SPR_BOOKE_TLB2CFG, SPR_BOOKE_TLB3CFG,
+ };
int i;
/* TLB assist registers */
@@ -889,34 +896,13 @@
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
mmucfg);
- switch (env->nb_ways) {
- case 4:
- spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
+
+ assert(env->nb_ways <= ARRAY_SIZE(tlbcfg_names));
+ for (i = 0; i < env->nb_ways; i++) {
+ spr_register(env, tlbcfg_sprn[i], tlbcfg_names[i],
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
- tlbncfg[3]);
- /* Fallthru */
- case 3:
- spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- tlbncfg[2]);
- /* Fallthru */
- case 2:
- spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- tlbncfg[1]);
- /* Fallthru */
- case 1:
- spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- tlbncfg[0]);
- /* Fallthru */
- case 0:
- default:
- break;
+ tlbncfg[i]);
}
#endif
}
@@ -1825,7 +1811,7 @@
#endif
}
-static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
+static void init_excp_e500(CPUPPCState *env, target_ulong ivpr_mask)
{
#if !defined(CONFIG_USER_ONLY)
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
@@ -2796,149 +2782,6 @@
POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
}
-static void init_proc_e200(CPUPPCState *env)
-{
- register_BookE_sprs(env, 0x000000070000FFFFULL);
-
- spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
- &spr_read_spefscr, &spr_write_spefscr,
- &spr_read_spefscr, &spr_write_spefscr,
- 0x00000000);
- /* Memory management */
- register_BookE206_sprs(env, 0x0000005D, NULL, 0);
- register_usprgh_sprs(env);
-
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
- &spr_read_generic, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x00000000);
-
- spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_BOOKE_IAC3, "IAC3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_BOOKE_IAC4, "IAC4",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_MMUCSR0, "MMUCSR0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000); /* TOFIX */
-
- init_tlbs_emb(env);
- init_excp_e200(env, 0xFFFF0000UL);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* XXX: TODO: allocate internal IRQ controller */
-}
-
-POWERPC_FAMILY(e200)(ObjectClass *oc, const void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "e200 core";
- pcc->init_proc = init_proc_e200;
- pcc->check_pow = check_pow_hid0;
- pcc->check_attn = check_attn_none;
- /*
- * XXX: unimplemented instructions:
- * dcblc
- * dcbtlst
- * dcbtstls
- * icblc
- * icbtls
- * tlbivax
- * all SPE multiply-accumulate instructions
- */
- pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
- PPC_SPE | PPC_SPE_SINGLE |
- PPC_WRTEE | PPC_RFDI |
- PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
- PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
- PPC_MEM_TLBSYNC | PPC_TLBIVAX |
- PPC_BOOKE;
- pcc->msr_mask = (1ull << MSR_UCLE) |
- (1ull << MSR_SPE) |
- (1ull << MSR_POW) |
- (1ull << MSR_CE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_DWE) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR);
- pcc->mmu_model = POWERPC_MMU_BOOKE206;
- pcc->excp_model = POWERPC_EXCP_BOOKE;
- pcc->bus_model = PPC_FLAGS_INPUT_BookE;
- pcc->bfd_mach = bfd_mach_ppc_860;
- pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
- POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
- POWERPC_FLAG_BUS_CLK;
-}
-
enum fsl_e500_version {
fsl_e500v1,
fsl_e500v2,
@@ -3173,7 +3016,7 @@
}
#endif
- init_excp_e200(env, ivpr_mask);
+ init_excp_e500(env, ivpr_mask);
/* Allocate hardware IRQ controller */
ppce500_irq_init(env_archcpu(env));
}
