tree b28564457fa1f56fa01d5fe719adf144e9ac3475
parent 67d74e4c54236b53917edfa9f52efb4207064014
author Jinjie Ruan <ruanjinjie@huawei.com> 1713533582 +0100
committer Peter Maydell <peter.maydell@linaro.org> 1714036865 +0100

hw/intc/arm_gicv3: Add irq non-maskable property

A SPI, PPI or SGI interrupt can have non-maskable property. So maintain
non-maskable property in PendingIrq and GICR/GICD. Since add new device
state, it also needs to be migrated, so also save NMI info in
vmstate_gicv3_cpu and vmstate_gicv3.

Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-16-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>