commit 0cc892fd97b2d232ae45a30aec342a2e0fb148aa
author Peter Maydell <peter.maydell@linaro.org> Fri Apr 20 17:58:34 2012 +0000
committer Peter Maydell <peter.maydell@linaro.org> Sat Apr 21 18:11:35 2012 +0000
tree 3f7f864fa29ce6a00d22669b3f35664bf95d3e3f
parent 4e851c380eda2bf27ff2ded85e4c80a342e6a72f

target-arm: Move iWMMXT wCID reset to cpu_state_reset

Move the iWMMXT wCID reset to cpu_state_reset(). Since
we use the same value for all CPUs with this feature
(with the major/minor revision fields set to the QEMU
specific 'Q' value) there's no need to create an ARMCPU
field just for this.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andreas Färber <afaerber@suse.de>

target-arm/helper.c

diff --git a/target-arm/helper.c b/target-arm/helper.c
index 3e31f94..319614a 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -121,7 +121,6 @@
     case ARM_CPUID_PXA270_B1:
     case ARM_CPUID_PXA270_C0:
     case ARM_CPUID_PXA270_C5:
-        env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
         break;
     case ARM_CPUID_SA1100:
     case ARM_CPUID_SA1110:
@@ -161,6 +160,10 @@
     env->cp15.c0_cachetype = cpu->ctr;
     env->cp15.c1_sys = cpu->reset_sctlr;
 
+    if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
+        env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
+    }
+
 #if defined (CONFIG_USER_ONLY)
     env->uncached_cpsr = ARM_CPU_MODE_USR;
     /* For user mode we must enable access to coprocessors */