Merge patch series "RISCVCPUConfig related cleanups"
Daniel Henrique Barboza <dbarboza@ventanamicro.com> says:
These cleanups were suggested by LIU Zhiwei during the review of
d3e6d5762b ("Merge patch series "make write_misa a no-op and FEATURE_*
cleanups"").
* b4-shazam-merge:
target/riscv/csr.c: avoid env_archcpu() usages when reading RISCVCPUConfig
target/riscv/csr.c: use riscv_cpu_cfg() to avoid env_cpu() pointers
target/riscv/csr.c: simplify mctr()
target/riscv/csr.c: use env_archcpu() in ctr()
Message-ID: <20230224174520.92490-1-dbarboza@ventanamicro.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index ee49b63..3106f96 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -40,11 +40,46 @@
csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops;
}
+/* Predicates */
+#if !defined(CONFIG_USER_ONLY)
+static RISCVException smstateen_acc_ok(CPURISCVState *env, int index,
+ uint64_t bit)
+{
+ bool virt = riscv_cpu_virt_enabled(env);
+
+ if (env->priv == PRV_M || !riscv_cpu_cfg(env)->ext_smstateen) {
+ return RISCV_EXCP_NONE;
+ }
+
+ if (!(env->mstateen[index] & bit)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+
+ if (virt) {
+ if (!(env->hstateen[index] & bit)) {
+ return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+ }
+
+ if (env->priv == PRV_U && !(env->sstateen[index] & bit)) {
+ return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+ }
+ }
+
+ if (env->priv == PRV_U && riscv_has_ext(env, RVS)) {
+ if (!(env->sstateen[index] & bit)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ }
+
+ return RISCV_EXCP_NONE;
+}
+#endif
+
static RISCVException fs(CPURISCVState *env, int csrno)
{
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !riscv_cpu_fp_enabled(env) &&
- !RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) {
+ !riscv_cpu_cfg(env)->ext_zfinx) {
return RISCV_EXCP_ILLEGAL_INST;
}
#endif
@@ -130,7 +165,7 @@
#if !defined(CONFIG_USER_ONLY)
static RISCVException mctr(CPURISCVState *env, int csrno)
{
- RISCVCPU *cpu = env_archcpu(env);
+ int pmu_num = riscv_cpu_cfg(env)->pmu_num;
int ctr_index;
int base_csrno = CSR_MHPMCOUNTER3;
@@ -139,7 +174,7 @@
base_csrno += 0x80;
}
ctr_index = csrno - base_csrno;
- if (!cpu->cfg.pmu_num || ctr_index >= cpu->cfg.pmu_num) {
+ if (!pmu_num || ctr_index >= pmu_num) {
/* The PMU is not enabled or counter is out of range*/
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -184,9 +219,7 @@
static int aia_any(CPURISCVState *env, int csrno)
{
- RISCVCPU *cpu = env_archcpu(env);
-
- if (!cpu->cfg.ext_smaia) {
+ if (!riscv_cpu_cfg(env)->ext_smaia) {
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -195,9 +228,7 @@
static int aia_any32(CPURISCVState *env, int csrno)
{
- RISCVCPU *cpu = env_archcpu(env);
-
- if (!cpu->cfg.ext_smaia) {
+ if (!riscv_cpu_cfg(env)->ext_smaia) {
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -224,9 +255,7 @@
static int aia_smode(CPURISCVState *env, int csrno)
{
- RISCVCPU *cpu = env_archcpu(env);
-
- if (!cpu->cfg.ext_ssaia) {
+ if (!riscv_cpu_cfg(env)->ext_ssaia) {
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -235,9 +264,7 @@
static int aia_smode32(CPURISCVState *env, int csrno)
{
- RISCVCPU *cpu = env_archcpu(env);
-
- if (!cpu->cfg.ext_ssaia) {
+ if (!riscv_cpu_cfg(env)->ext_ssaia) {
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -332,9 +359,8 @@
{
bool virt = riscv_cpu_virt_enabled(env);
int index = csrno - CSR_SSTATEEN0;
- RISCVCPU *cpu = env_archcpu(env);
- if (!cpu->cfg.ext_smstateen) {
+ if (!riscv_cpu_cfg(env)->ext_smstateen) {
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -428,9 +454,7 @@
static int aia_hmode(CPURISCVState *env, int csrno)
{
- RISCVCPU *cpu = env_archcpu(env);
-
- if (!cpu->cfg.ext_ssaia) {
+ if (!riscv_cpu_cfg(env)->ext_ssaia) {
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -439,9 +463,7 @@
static int aia_hmode32(CPURISCVState *env, int csrno)
{
- RISCVCPU *cpu = env_archcpu(env);
-
- if (!cpu->cfg.ext_ssaia) {
+ if (!riscv_cpu_cfg(env)->ext_ssaia) {
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -487,9 +509,7 @@
static RISCVException seed(CPURISCVState *env, int csrno)
{
- RISCVCPU *cpu = env_archcpu(env);
-
- if (!cpu->cfg.ext_zkr) {
+ if (!riscv_cpu_cfg(env)->ext_zkr) {
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -616,7 +636,7 @@
static int read_vlenb(CPURISCVState *env, int csrno, target_ulong *val)
{
- *val = env_archcpu(env)->cfg.vlen >> 3;
+ *val = riscv_cpu_cfg(env)->vlen >> 3;
return RISCV_EXCP_NONE;
}
@@ -671,7 +691,7 @@
* The vstart CSR is defined to have only enough writable bits
* to hold the largest element index, i.e. lg2(VLEN) bits.
*/
- env->vstart = val & ~(~0ULL << ctzl(env_archcpu(env)->cfg.vlen));
+ env->vstart = val & ~(~0ULL << ctzl(riscv_cpu_cfg(env)->vlen));
return RISCV_EXCP_NONE;
}
@@ -1913,39 +1933,6 @@
return RISCV_EXCP_NONE;
}
-static RISCVException smstateen_acc_ok(CPURISCVState *env, int index,
- uint64_t bit)
-{
- bool virt = riscv_cpu_virt_enabled(env);
- RISCVCPU *cpu = env_archcpu(env);
-
- if (env->priv == PRV_M || !cpu->cfg.ext_smstateen) {
- return RISCV_EXCP_NONE;
- }
-
- if (!(env->mstateen[index] & bit)) {
- return RISCV_EXCP_ILLEGAL_INST;
- }
-
- if (virt) {
- if (!(env->hstateen[index] & bit)) {
- return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
- }
-
- if (env->priv == PRV_U && !(env->sstateen[index] & bit)) {
- return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
- }
- }
-
- if (env->priv == PRV_U && riscv_has_ext(env, RVS)) {
- if (!(env->sstateen[index] & bit)) {
- return RISCV_EXCP_ILLEGAL_INST;
- }
- }
-
- return RISCV_EXCP_NONE;
-}
-
static RISCVException read_senvcfg(CPURISCVState *env, int csrno,
target_ulong *val)
{
